f8a987a592
copied over and modified for use my CH59x soft I2C. CH32X GPIO does not have an open drain mode, so I have to implement this with RMW to the mode register. After doing this and adding missing functions needed for existing code, LED writes and EEPROM reads and writes. using the AWU for system timing so the clock speed can change. existing issues: - changing clock speed divider in soft i2c routines causes the system to crash - ADC seems to be reading, but result isn't being used
155 lines
4.7 KiB
C
155 lines
4.7 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : system_ch32x035.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2023/04/06
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* Description : CH32X035 Device Peripheral Access Layer System Source File.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32x035.h"
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#include "global.h"
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/*
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
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* reset the HSI is used as SYSCLK source).
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*/
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/* Clock Definitions */
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/*
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#ifdef SYSCLK_FREQ_8MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; // System Clock Frequency (Core Clock)
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#elif defined SYSCLK_FREQ_12MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_12MHz_HSI; // System Clock Frequency (Core Clock)
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#elif defined SYSCLK_FREQ_16MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz_HSI; // System Clock Frequency (Core Clock)
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#elif defined SYSCLK_FREQ_24MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; // System Clock Frequency (Core Clock)
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#else
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uint32_t SystemCoreClock = HSI_VALUE; // System Clock Frequency (Core Clock)
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#endif
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*/
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uint32_t SystemCoreClock;
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__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
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/* system_private_function_proto_types */
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void SetSysClock(uint32_t clock);
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/*
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#ifdef SYSCLK_FREQ_8MHz_HSI
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static void SetSysClockTo8_HSI( void );
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#elif defined SYSCLK_FREQ_12MHz_HSI
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static void SetSysClockTo12_HSI( void );
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#elif defined SYSCLK_FREQ_16MHz_HSI
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static void SetSysClockTo16_HSI( void );
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#elif defined SYSCLK_FREQ_24MHz_HSI
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static void SetSysClockTo24_HSI( void );
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#elif defined SYSCLK_FREQ_48MHz_HSI
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static void SetSysClockTo48_HSI( void );
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#endif
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*/
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static void SetSysClockToX_HSI(uint32_t div, uint32_t latency);
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/*********************************************************************
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* @fn SystemInit
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*
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
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* update the SystemCoreClock variable.
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*
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* @return none
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*/
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void SystemInit (void)
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{
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RCC->CTLR |= (uint32_t)0x00000001;
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RCC->CFGR0 |= (uint32_t)0x00000050;
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RCC->CFGR0 &= (uint32_t)0xF8FFFF5F;
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SetSysClock(SYSCLK_FREQ_NORMAL);
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}
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/*********************************************************************
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* @fn SystemCoreClockUpdate
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*
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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*
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* @return none
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0;
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SystemCoreClock = HSI_VALUE;
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tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
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if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8)
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{
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SystemCoreClock /= tmp;
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}
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else
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{
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SystemCoreClock >>= tmp;
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}
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}
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/*********************************************************************
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* @fn SetSysClock
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*
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* @brief Configures the System clock frequency, HCLK prescalers.
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*
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* @return none
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*/
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void SetSysClock(uint32_t clock)
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{
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switch (clock) {
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case SYSCLK_FREQ_48MHz_HSI: { SetSysClockToX_HSI(RCC_HPRE_DIV1, FLASH_ACTLR_LATENCY_2); break; }
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case SYSCLK_FREQ_24MHz_HSI: { SetSysClockToX_HSI(RCC_HPRE_DIV2, FLASH_ACTLR_LATENCY_1); break; }
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case SYSCLK_FREQ_16MHz_HSI: { SetSysClockToX_HSI(RCC_HPRE_DIV3, FLASH_ACTLR_LATENCY_1); break; }
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case SYSCLK_FREQ_12MHz_HSI: { SetSysClockToX_HSI(RCC_HPRE_DIV4, FLASH_ACTLR_LATENCY_0); break; }
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default: {
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SetSysClockToX_HSI(RCC_HPRE_DIV6, FLASH_ACTLR_LATENCY_0);
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clock = 8000000;
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break;
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}
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}
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SystemCoreClock = clock;
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/*
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#ifdef SYSCLK_FREQ_8MHz_HSI
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SetSysClockTo8_HSI();
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#elif defined SYSCLK_FREQ_12MHz_HSI
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SetSysClockTo12_HSI();
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#elif defined SYSCLK_FREQ_16MHz_HSI
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SetSysClockTo16_HSI();
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#elif defined SYSCLK_FREQ_24MHz_HSI
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SetSysClockTo24_HSI();
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#elif defined SYSCLK_FREQ_48MHz_HSI
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SetSysClockTo48_HSI();
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#endif
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*/
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}
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static void SetSysClockToX_HSI(uint32_t div, uint32_t latency)
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{
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uint32_t actlr;
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uint32_t cfgr0;
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/* Flash 2 wait state */
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actlr = FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
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FLASH->ACTLR = (uint32_t)actlr | FLASH_ACTLR_LATENCY_2;
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/* HCLK = SYSCLK = APB1 */
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cfgr0 = RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
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RCC->CFGR0 = (uint32_t)cfgr0 | (div & 0xf0);
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/* Flash set wait state */
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FLASH->ACTLR = (uint32_t)actlr | (latency & 0x03);
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}
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