commit 576026f7713bfcd07d579bf23f966ef7e162c5f0 Author: true Date: Sat Oct 12 21:59:33 2024 -0700 initial commit of work in progress code The V003 sub MCU code is mostly initially written, though needs to be tested and fixed. diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..5aedb0e --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +/nametag8_CH592/build_softi2c +/nametag8_V003/obj diff --git a/nametag8_CH592/Ld/Link.ld b/nametag8_CH592/Ld/Link.ld new file mode 100644 index 0000000..7c2899c --- /dev/null +++ b/nametag8_CH592/Ld/Link.ld @@ -0,0 +1,185 @@ +ENTRY( _start ) + +__stack_size = 512; + +PROVIDE( _stack_size = __stack_size ); + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 448K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K + RAM2K (xrw) : ORIGIN = 0x20006000, LENGTH = 2K +} + +SECTIONS +{ + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + /* .vector : + { + *(.vector); + } >FLASH AT>FLASH */ + + .highcodelalign : + { + . = ALIGN(4); + PROVIDE(_highcode_lma = .); + } >FLASH AT>FLASH + + .highcode : + { + . = ALIGN(4); + PROVIDE(_highcode_vma_start = .); + *(.vector); + KEEP(*(SORT_NONE(.vector_handler))) + *(.highcode); + *(.highcode.*); + . = ALIGN(4); + PROVIDE(_highcode_vma_end = .); + } >RAM AT>FLASH + + .text : + { + . = ALIGN(4); + KEEP(*(SORT_NONE(.handle_reset))) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.sdata2.*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ORIGIN(RAM) + MAX(0x800 , SIZEOF(.highcode)); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM +} + + + diff --git a/nametag8_CH592/RVMSIS/core_riscv.c b/nametag8_CH592/RVMSIS/core_riscv.c new file mode 100644 index 0000000..c101eb3 --- /dev/null +++ b/nametag8_CH592/RVMSIS/core_riscv.c @@ -0,0 +1,306 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.1.0 + * Date : 2021/06/06 + * Description : RISC-V Core Peripheral Access Layer Source File + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/nametag8_CH592/RVMSIS/core_riscv.h b/nametag8_CH592/RVMSIS/core_riscv.h new file mode 100644 index 0000000..9776816 --- /dev/null +++ b/nametag8_CH592/RVMSIS/core_riscv.h @@ -0,0 +1,624 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.1.0 + * Date : 2023/04/10 + * Description : CH592 RISC-V Core Peripheral Access Layer Header File + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CORE_RV3A_H__ +#define __CORE_RV3A_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ +#define RV_STATIC_INLINE static inline + +//typedef enum {SUCCESS = 0, ERROR = !SUCCESS} ErrorStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct +{ + __I uint32_t ISR[8]; // 0 + __I uint32_t IPR[8]; // 20H + __IO uint32_t ITHRESDR; // 40H + uint8_t RESERVED[4]; // 44H + __O uint32_t CFGR; // 48H + __I uint32_t GISR; // 4CH + __IO uint8_t VTFIDR[4]; // 50H + uint8_t RESERVED0[0x0C]; // 54H + __IO uint32_t VTFADDR[4]; // 60H + uint8_t RESERVED1[0x90]; // 70H + __O uint32_t IENR[8]; // 100H + uint8_t RESERVED2[0x60]; // 120H + __O uint32_t IRER[8]; // 180H + uint8_t RESERVED3[0x60]; // 1A0H + __O uint32_t IPSR[8]; // 200H + uint8_t RESERVED4[0x60]; // 220H + __O uint32_t IPRR[8]; // 280H + uint8_t RESERVED5[0x60]; // 2A0H + __IO uint32_t IACTR[8]; // 300H + uint8_t RESERVED6[0xE0]; // 320H + __IO uint8_t IPRIOR[256]; // 400H + uint8_t RESERVED7[0x810]; // 500H + __IO uint32_t SCTLR; // D10H +} PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +} SysTick_Type; + +#define PFIC ((PFIC_Type *)0xE000E000) +#define SysTick ((SysTick_Type *)0xE000F000) + +#define PFIC_KEY1 ((uint32_t)0xFA050000) +#define PFIC_KEY2 ((uint32_t)0xBCAF0000) +#define PFIC_KEY3 ((uint32_t)0xBEEF0000) + +/* ########################## define #################################### */ +#define __nop() __asm__ volatile("nop") + +#define read_csr(reg) ({unsigned long __tmp; \ + __asm__ volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + __asm__ volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + __asm__ volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define PFIC_EnableAllIRQ() {write_csr(0x800, 0x88);__nop();__nop();} +#define PFIC_DisableAllIRQ() {write_csr(0x800, 0x80);__nop();__nop();} +/* ########################## PFIC functions #################################### */ + +/********************************************************************* + * @fn __risc_v_enable_irq + * + * @brief recover Global Interrupt + * + * @return mpie and mie bit in mstatus. + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __risc_v_enable_irq(uint32_t mpie_mie) +{ + uint32_t result; + + __asm volatile ("csrrs %0, 0x800, %1" : \ + "=r"(result): "r"(mpie_mie) : "memory"); + return result; +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return mpie and mie bit in mstatus. + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __risc_v_disable_irq(void) +{ + uint32_t result; + + __asm volatile ("csrrc %0, 0x800, %1" : \ + "=r"(result): "r"(0x88) : "memory"); + return result & 0x88; +} + +/******************************************************************************* + * @fn PFIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + */ +__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_EnableIRQ(IRQn_Type IRQn) +{ + PFIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); +} + +/******************************************************************************* + * @fn PFIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + */ +__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_DisableIRQ(IRQn_Type IRQn) +{ + PFIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); + __nop(); + __nop(); +} + +/******************************************************************************* + * @fn PFIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1: Interrupt Enable + * 0: Interrupt Disable + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t PFIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)((PFIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); +} + +/******************************************************************************* + * @fn PFIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1: Interrupt Pending Enable + * 0: Interrupt Pending Disable + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t PFIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)((PFIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); +} + +/******************************************************************************* + * @fn PFIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + */ +__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_SetPendingIRQ(IRQn_Type IRQn) +{ + PFIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); +} + +/******************************************************************************* + * @fn PFIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + */ +__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + PFIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); +} + +/******************************************************************************* + * @fn PFIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1: Interrupt Active + * 0: Interrupt No Active. + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t PFIC_GetActive(IRQn_Type IRQn) +{ + return ((uint32_t)((PFIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); +} + +/******************************************************************************* + * @fn PFIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * @param priority - bit7: pre-emption priority + * bit6-bit4: subpriority + */ +__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + PFIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ + if(num > 3) return ; + + if (NewState != DISABLE) + { + PFIC->VTFIDR[num] = IRQn; + PFIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else{ + PFIC->VTFIDR[num] = IRQn; + PFIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + + PFIC->SCTLR |= (1<<3)|(1<<5); + +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + PFIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return None + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + */ +__attribute__((always_inline)) RV_STATIC_INLINE void __WFI(void) +{ + PFIC->SCTLR &= ~(1 << 3); // wfi + __asm__ volatile("wfi"); +} + +/********************************************************************* + * @fn PFIC_SystemReset + * + * @brief Initiate a system reset request + */ +__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_SystemReset(void) +{ + PFIC->CFGR = PFIC_KEY3 | (1 << 7); +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * addr Address pointer to data, address need to be 4byte aligned + * value value to be ADDed + * + * + * @return return memory value + add value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * addr Address pointer to data, address need to be 4byte aligned + * value value to be ANDed + * + * + * @return return memory value & and value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * @details Atomically signed max compare 32bit value with value in memory using amomax.d. + * addr Address pointer to data, address need to be 4byte aligned + * value value to be compared + * + * + * @return the bigger value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * addr Address pointer to data, address need to be 4byte aligned + * value value to be compared + * + * @return return the bigger value + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * addr Address pointer to data, address need to be 4byte aligned + * value value to be compared + * + * + * @return the smaller value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * addr Address pointer to data, address need to be 4byte aligned + * value value to be compared + * + * + * @return the smaller value + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * @details Atomically OR 32bit value with value in memory using amoor.d. + * addr Address pointer to data, address need to be 4byte aligned + * value value to be ORed + * + * + * @return return memory value | and value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * addr Address pointer to data, address need to be 4byte aligned + * newval New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * @details Atomically XOR 32bit value with value in memory using amoxor.d. + * addr Address pointer to data, address need to be 4byte aligned + * value value to be XORed + * + * + * @return return memory value ^ and value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/** + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void); + +/** + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void); + +/*** + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void); + +/** + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void); + +/** + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void); + +/** + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void); + +/** + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void); + +/** + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void); + +/** + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void); + +/** + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void); + +/** + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void); + +/** + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void); + +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFFFFFFFFFFF) +#define SysTick_CTLR_SWIE (1 << 31) +#define SysTick_CTLR_INIT (1 << 5) +#define SysTick_CTLR_MODE (1 << 4) +#define SysTick_CTLR_STRE (1 << 3) +#define SysTick_CTLR_STCLK (1 << 2) +#define SysTick_CTLR_STIE (1 << 1) +#define SysTick_CTLR_STE (1 << 0) + +#define SysTick_SR_CNTIF (1 << 0) + +RV_STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks) +{ + if((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ + + SysTick->CMP = ticks - 1; /* set reload register */ + PFIC_EnableIRQ(SysTick_IRQn); + SysTick->CTLR = SysTick_CTLR_INIT | + SysTick_CTLR_STRE | + SysTick_CTLR_STCLK | + SysTick_CTLR_STIE | + SysTick_CTLR_STE; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV3A_H__ */ diff --git a/nametag8_CH592/Startup/startup_CH592.S b/nametag8_CH592/Startup/startup_CH592.S new file mode 100644 index 0000000..3f76cba --- /dev/null +++ b/nametag8_CH592/Startup/startup_CH592.S @@ -0,0 +1,186 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : startup_CH59x.s + * Author : WCH + * Version : V1.0.0 + * Date : 2021/02/25 + * Description : + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + + .word 0 + .word 0 + .word NMI_Handler /* NMI Handler */ + .word HardFault_Handler /* Hard Fault Handler */ + .word 0xF5F9BDA9 + .word Ecall_M_Mode_Handler /* 5 */ + .word 0 + .word 0 + .word Ecall_U_Mode_Handler /* 8 */ + .word Break_Point_Handler /* 9 */ + .word 0 + .word 0 + .word SysTick_Handler /* SysTick Handler */ + .word 0 + .word SW_Handler /* SW Handler */ + .word 0 + /* External Interrupts */ + .word TMR0_IRQHandler /* 0: TMR0 */ + .word GPIOA_IRQHandler /* GPIOA */ + .word GPIOB_IRQHandler /* GPIOB */ + .word SPI0_IRQHandler /* SPI0 */ + .word BB_IRQHandler /* BLEB */ + .word LLE_IRQHandler /* BLEL */ + .word USB_IRQHandler /* USB */ + .word 0 + .word TMR1_IRQHandler /* TMR1 */ + .word TMR2_IRQHandler /* TMR2 */ + .word UART0_IRQHandler /* UART0 */ + .word UART1_IRQHandler /* UART1 */ + .word RTC_IRQHandler /* RTC */ + .word ADC_IRQHandler /* ADC */ + .word I2C_IRQHandler /* I2C */ + .word PWMX_IRQHandler /* PWMX */ + .word TMR3_IRQHandler /* TMR3 */ + .word UART2_IRQHandler /* UART2 */ + .word UART3_IRQHandler /* UART3 */ + .word WDOG_BAT_IRQHandler /* WDOG_BAT */ + + .option rvc; + + .section .vector_handler, "ax", @progbits + .weak NMI_Handler + .weak HardFault_Handler + .weak Ecall_M_Mode_Handler + .weak Ecall_U_Mode_Handler + .weak Break_Point_Handler + .weak SysTick_Handler + .weak SW_Handler + .weak TMR0_IRQHandler + .weak GPIOA_IRQHandler + .weak GPIOB_IRQHandler + .weak SPI0_IRQHandler + .weak BB_IRQHandler + .weak LLE_IRQHandler + .weak USB_IRQHandler + .weak TMR1_IRQHandler + .weak TMR2_IRQHandler + .weak UART0_IRQHandler + .weak UART1_IRQHandler + .weak RTC_IRQHandler + .weak ADC_IRQHandler + .weak I2C_IRQHandler + .weak PWMX_IRQHandler + .weak TMR3_IRQHandler + .weak UART2_IRQHandler + .weak UART3_IRQHandler + .weak WDOG_BAT_IRQHandler + +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +TMR0_IRQHandler: +GPIOA_IRQHandler: +GPIOB_IRQHandler: +SPI0_IRQHandler: +BB_IRQHandler: +LLE_IRQHandler: +USB_IRQHandler: +TMR1_IRQHandler: +TMR2_IRQHandler: +UART0_IRQHandler: +UART1_IRQHandler: +RTC_IRQHandler: +ADC_IRQHandler: +I2C_IRQHandler: +PWMX_IRQHandler: +TMR3_IRQHandler: +UART2_IRQHandler: +UART3_IRQHandler: +WDOG_BAT_IRQHandler: +1: + j 1b + + .section .handle_reset,"ax",@progbits + .weak handle_reset + .align 1 + +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop +1: + la sp, _eusrstack + +/* Load highcode code section from flash to RAM */ +2: + la a0, _highcode_lma + la a1, _highcode_vma_start + la a2, _highcode_vma_end + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b + +/* Load data section from flash to RAM */ +2: + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + /* clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + /* 流水线控制位 & 动态预测控制位 */ + li t0, 0x1f + csrw 0xbc0, t0 + /* 打开嵌套中断、硬件压栈功能 */ + li t0, 0x3 + csrw 0x804, t0 + + li t0, 0x88 + csrw mstatus, t0 + la t0, _vector_base + + /* 配置向量表模式为绝对地址模式 */ + ori t0, t0, 3 + csrw mtvec, t0 + + la t0, main + csrw mepc, t0 + + mret diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_adc.c b/nametag8_CH592/StdPeriphDriver/CH59x_adc.c new file mode 100644 index 0000000..1d1fcba --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_adc.c @@ -0,0 +1,257 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_adc.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn ADC_DataCalib_Rough + * + * @brief 采样数据粗调,获取偏差值,必须先配置ADC后调用此函数获取校准值 + * + * @param none + * + * @return 偏差 + */ +signed short ADC_DataCalib_Rough(void) // 采样数据粗调,获取偏差值 +{ + uint16_t i; + uint32_t sum = 0; + uint8_t ch = 0; // 备份通道 + uint8_t cfg = 0; // 备份 + + ch = R8_ADC_CHANNEL; + cfg = R8_ADC_CFG; + + R8_ADC_CFG |= RB_ADC_OFS_TEST; // 进入测试模式 + R8_ADC_CFG &= ~RB_ADC_DIFF_EN; // 关闭差分 + + R8_ADC_CONVERT |= RB_ADC_START; + while(R8_ADC_CONVERT & RB_ADC_START); + for(i = 0; i < 16; i++) + { + R8_ADC_CONVERT |= RB_ADC_START; + while(R8_ADC_CONVERT & RB_ADC_START); + sum += (~R16_ADC_DATA) & RB_ADC_DATA; + } + sum = (sum + 8) >> 4; + + R8_ADC_CFG = cfg; // 恢复配置值 + R8_ADC_CHANNEL = ch; + + return (2048 - sum); +} + +/********************************************************************* + * @fn ADC_ExtSingleChSampInit + * + * @brief 外部信号单通道采样初始化 + * + * @param sp - refer to ADC_SampClkTypeDef + * @param ga - refer to ADC_SignalPGATypeDef + * + * @return none + */ +void ADC_ExtSingleChSampInit(ADC_SampClkTypeDef sp, ADC_SignalPGATypeDef ga) +{ + R8_TKEY_CFG &= ~RB_TKEY_PWR_ON; + R8_ADC_CFG = RB_ADC_POWER_ON | RB_ADC_BUF_EN | (sp << 6) | ((ga&0xF) << 4); + if( ga & ADC_PGA_2_ ) + { + R8_ADC_CONVERT |= RB_ADC_PGA_GAIN2; + } + else + { + R8_ADC_CONVERT &= ~RB_ADC_PGA_GAIN2; + } +} + +/********************************************************************* + * @fn ADC_ExtDiffChSampInit + * + * @brief 外部信号差分通道采样初始化 + * + * @param sp - refer to ADC_SampClkTypeDef + * @param ga - refer to ADC_SignalPGATypeDef + * + * @return none + */ +void ADC_ExtDiffChSampInit(ADC_SampClkTypeDef sp, ADC_SignalPGATypeDef ga) +{ + R8_TKEY_CFG &= ~RB_TKEY_PWR_ON; + R8_ADC_CFG = RB_ADC_POWER_ON | RB_ADC_DIFF_EN | (sp << 6) | ((ga&0xF) << 4); + if( ga & ADC_PGA_2_ ) + { + R8_ADC_CONVERT |= RB_ADC_PGA_GAIN2; + } + else + { + R8_ADC_CONVERT &= ~RB_ADC_PGA_GAIN2; + } +} + +/********************************************************************* + * @fn ADC_InterTSSampInit + * + * @brief 内置温度传感器采样初始化 + * + * @param none + * + * @return none + */ +void ADC_InterTSSampInit(void) +{ + R8_TKEY_CFG &= ~RB_TKEY_PWR_ON; + R8_TEM_SENSOR = RB_TEM_SEN_PWR_ON; + R8_ADC_CHANNEL = CH_INTE_VTEMP; + R8_ADC_CFG = RB_ADC_POWER_ON | RB_ADC_DIFF_EN | (3 << 4); + R8_ADC_CONVERT &= ~RB_ADC_PGA_GAIN2; +} + +/********************************************************************* + * @fn ADC_InterBATSampInit + * + * @brief 内置电池电压采样初始化 + * + * @param none + * + * @return none + */ +void ADC_InterBATSampInit(void) +{ + R8_TKEY_CFG &= ~RB_TKEY_PWR_ON; + R8_ADC_CHANNEL = CH_INTE_VBAT; + R8_ADC_CFG = RB_ADC_POWER_ON | RB_ADC_BUF_EN | (0 << 4); // 使用-12dB模式 + R8_ADC_CONVERT &= ~RB_ADC_PGA_GAIN2; +} + +/********************************************************************* + * @fn TouchKey_ChSampInit + * + * @brief 触摸按键通道采样初始化 + * + * @param none + * + * @return none + */ +void TouchKey_ChSampInit(void) +{ + R8_ADC_CFG = RB_ADC_POWER_ON | RB_ADC_BUF_EN | (ADC_PGA_0 << 4) | (SampleFreq_8 << 6); + R8_ADC_CONVERT &= ~RB_ADC_PGA_GAIN2; + R8_TKEY_CFG |= RB_TKEY_PWR_ON; +} + +/********************************************************************* + * @fn ADC_ExcutSingleConver + * + * @brief ADC执行单次转换 + * + * @param none + * + * @return ADC转换后的数据 + */ +uint16_t ADC_ExcutSingleConver(void) +{ + R8_ADC_CONVERT |= RB_ADC_START; + while(R8_ADC_CONVERT & RB_ADC_START); + + return (R16_ADC_DATA & RB_ADC_DATA); +} + +/********************************************************************* + * @fn TouchKey_ExcutSingleConver + * + * @brief TouchKey转换后数据 + * + * @param charg - Touchkey充电时间,5bits有效, t=charg*Tadc + * @param disch - Touchkey放电时间,3bits有效, t=disch*Tadc + * + * @return 当前TouchKey等效数据 + */ +uint16_t TouchKey_ExcutSingleConver(uint8_t charg, uint8_t disch) +{ + R8_TKEY_COUNT = (disch << 5) | (charg & 0x1f); + R8_TKEY_CONVERT = RB_TKEY_START; + while(R8_TKEY_CONVERT & RB_TKEY_START); + return (R16_ADC_DATA & RB_ADC_DATA); +} + +/********************************************************************* + * @fn ADC_AutoConverCycle + * + * @brief 设置连续 ADC的周期 + * + * @param cycle - 采样周期计算方法为(256-cycle)*16*Tsys + * + * @return none + */ +void ADC_AutoConverCycle(uint8_t cycle) +{ + R8_ADC_AUTO_CYCLE = cycle; +} + +/********************************************************************* + * @fn ADC_DMACfg + * + * @brief 配置DMA功能 + * + * @param s - 是否打开DMA功能 + * @param startAddr - DMA 起始地址 + * @param endAddr - DMA 结束地址 + * @param m - 配置DMA模式 + * + * @return none + */ +void ADC_DMACfg(uint8_t s, uint32_t startAddr, uint32_t endAddr, ADC_DMAModeTypeDef m) +{ + if(s == DISABLE) + { + R8_ADC_CTRL_DMA &= ~(RB_ADC_DMA_ENABLE | RB_ADC_IE_DMA_END); + } + else + { + R16_ADC_DMA_BEG = startAddr&0xFFFF; + R16_ADC_DMA_END = endAddr&0xFFFF; + if(m) + { + R8_ADC_CTRL_DMA |= RB_ADC_DMA_LOOP | RB_ADC_IE_DMA_END | RB_ADC_DMA_ENABLE; + } + else + { + R8_ADC_CTRL_DMA &= ~RB_ADC_DMA_LOOP; + R8_ADC_CTRL_DMA |= RB_ADC_IE_DMA_END | RB_ADC_DMA_ENABLE; + } + } +} + +/********************************************************************* + * @fn adc_to_temperature_celsius + * + * @brief Convert ADC value to temperature(Celsius) + * + * @param adc_val - adc value + * + * @return temperature (Celsius) + */ + +int adc_to_temperature_celsius(uint16_t adc_val) +{ + uint32_t C25 = 0; + int temp; + + C25 = (*((PUINT32)ROM_CFG_TMP_25C)); + + /* current temperature = standard temperature + (adc deviation * adc linearity coefficient) */ + temp = (((C25 >> 16) & 0xFFFF) ? ((C25 >> 16) & 0xFFFF) : 25) + \ + (adc_val - ((int)(C25 & 0xFFFF))) * 100 / 283; + + return (temp); +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_clk.c b/nametag8_CH592/StdPeriphDriver/CH59x_clk.c new file mode 100644 index 0000000..fe053b8 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_clk.c @@ -0,0 +1,623 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_clk.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn LClk32K_Select + * + * @brief 32K 低频时钟来源 + * + * @param hc - 选择32K使用内部还是外部 + * + * @return none + */ +void LClk32K_Select(LClk32KTypeDef hc) +{ + uint8_t cfg = R8_CK32K_CONFIG; + + if(hc == Clk32K_LSI) + { + cfg &= ~RB_CLK_OSC32K_XT; + LSECFG_Current(LSE_RCur_100); + } + else + { + cfg |= RB_CLK_OSC32K_XT; + } + + sys_safe_access_enable(); + R8_CK32K_CONFIG = cfg; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn LClk32K_Cfg + * + * @brief 32K 低频时钟电源配置 + * + * @param hc - 选择内部32K还是外部32K + * @param s - 是否打开电源 + * + * @return none + */ +void LClk32K_Cfg(LClk32KTypeDef hc, FunctionalState s) +{ + uint8_t cfg = R8_CK32K_CONFIG; + + if(hc == Clk32K_LSI) + { + if(s == DISABLE) + { + cfg &= ~RB_CLK_INT32K_PON; + } + else + { + cfg |= RB_CLK_INT32K_PON; + } + } + else + { + if(s == DISABLE) + { + cfg &= ~RB_CLK_XT32K_PON; + } + else + { + cfg |= RB_CLK_XT32K_PON; + } + } + + sys_safe_access_enable(); + R8_CK32K_CONFIG = cfg; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn HSECFG_Current + * + * @brief HSE晶体 偏置电流配置 + * + * @param c - 75%,100%,125%,150% + * + * @return none + */ +void HSECFG_Current(HSECurrentTypeDef c) +{ + uint8_t x32M_c; + + x32M_c = R8_XT32M_TUNE; + x32M_c = (x32M_c & 0xfc) | (c & 0x03); + + sys_safe_access_enable(); + R8_XT32M_TUNE = x32M_c; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn HSECFG_Capacitance + * + * @brief HSE晶体 负载电容配置 + * + * @param c - refer to HSECapTypeDef + * + * @return none + */ +void HSECFG_Capacitance(HSECapTypeDef c) +{ + uint8_t x32M_c; + + x32M_c = R8_XT32M_TUNE; + x32M_c = (x32M_c & 0x8f) | (c << 4); + + sys_safe_access_enable(); + R8_XT32M_TUNE = x32M_c; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn LSECFG_Current + * + * @brief LSE晶体 偏置电流配置 + * + * @param c - 70%,100%,140%,200% + * + * @return none + */ +void LSECFG_Current(LSECurrentTypeDef c) +{ + uint8_t x32K_c; + + x32K_c = R8_XT32K_TUNE; + x32K_c = (x32K_c & 0xfc) | (c & 0x03); + + sys_safe_access_enable(); + R8_XT32K_TUNE = x32K_c; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn LSECFG_Capacitance + * + * @brief LSE晶体 负载电容配置 + * + * @param c - refer to LSECapTypeDef + * + * @return none + */ +void LSECFG_Capacitance(LSECapTypeDef c) +{ + uint8_t x32K_c; + + x32K_c = R8_XT32K_TUNE; + x32K_c = (x32K_c & 0x0f) | (c << 4); + + sys_safe_access_enable(); + R8_XT32K_TUNE = x32K_c; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn Calibration_LSI + * + * @brief 校准内部32K时钟 + * + * @param cali_Lv - 校准等级选择 Level_32 ：2.4ms 1000ppm (32M 主频) 1100ppm (60M 主频) + * Level_64 ：4.4ms 800ppm (32M 主频) 1000ppm (60M 主频) + * Level_128 ：8.4ms 600ppm (32M 主频) 800ppm (60M 主频) + * + * @return none + */ +void Calibration_LSI(Cali_LevelTypeDef cali_Lv) +{ + UINT64 i; + long long cnt_offset; + UINT8 retry = 0; + UINT8 retry_all = 0; + INT32 freq_sys; + UINT32 cnt_32k = 0; + UINT32 irqv = 0; + + freq_sys = GetSysClock(); + + sys_safe_access_enable(); + R8_CK32K_CONFIG &= ~RB_CLK_OSC32K_FILT; + R8_CK32K_CONFIG |= RB_CLK_OSC32K_FILT; + sys_safe_access_disable(); + LSECFG_Current(LSE_RCur_100); + + while(1) + { + // 粗调 + sys_safe_access_enable(); + R8_OSC_CAL_CTRL &= ~RB_OSC_CNT_TOTAL; + R8_OSC_CAL_CTRL |= 1; + sys_safe_access_disable(); + + while(1) + { + sys_safe_access_enable(); + R8_OSC_CAL_CTRL |= RB_OSC_CNT_EN; + R16_OSC_CAL_CNT |= RB_OSC_CAL_OV_CLR; + R16_OSC_CAL_CNT |= RB_OSC_CAL_IF; + sys_safe_access_disable(); + while( (R8_OSC_CAL_CTRL & RB_OSC_CNT_EN) == 0 ) + { + sys_safe_access_enable(); + R8_OSC_CAL_CTRL |= RB_OSC_CNT_EN; + sys_safe_access_disable(); + } + + while(!(R8_OSC_CAL_CTRL & RB_OSC_CNT_HALT)); // 用于丢弃 + + SYS_DisableAllIrq(&irqv); + sys_safe_access_enable(); + R8_OSC_CAL_CTRL &= ~RB_OSC_CNT_EN; + R8_OSC_CAL_CTRL |= RB_OSC_CNT_EN; + R16_OSC_CAL_CNT |= RB_OSC_CAL_OV_CLR; + R16_OSC_CAL_CNT |= RB_OSC_CAL_IF; + sys_safe_access_disable(); + while( (R8_OSC_CAL_CTRL & RB_OSC_CNT_EN) == 0 ) + { + sys_safe_access_enable(); + R8_OSC_CAL_CTRL |= RB_OSC_CNT_EN; + sys_safe_access_disable(); + } + + while(R8_OSC_CAL_CTRL & RB_OSC_CNT_HALT); + cnt_32k = RTC_GetCycle32k(); + while(RTC_GetCycle32k() == cnt_32k); + R16_OSC_CAL_CNT |= RB_OSC_CAL_OV_CLR; + SYS_RecoverIrq(irqv); + while(!(R8_OSC_CAL_CTRL & RB_OSC_CNT_HALT)); + i = R16_OSC_CAL_CNT; // 实时校准后采样值 + cnt_offset = (i & 0x3FFF) + R8_OSC_CAL_OV_CNT * 0x3FFF - 2000 * (freq_sys / 1000) / CAB_LSIFQ; + if(((cnt_offset > -37 * (freq_sys / 1000) / 60000) && (cnt_offset < 37 * (freq_sys / 1000) / 60000)) || retry > 2) + { + if(retry) + break; + } + retry++; + cnt_offset = (cnt_offset > 0) ? (((cnt_offset * 2) / (74 * (freq_sys/1000) / 60000)) + 1) / 2 : (((cnt_offset * 2) / (74 * (freq_sys/1000) / 60000 )) - 1) / 2; + sys_safe_access_enable(); + R16_INT32K_TUNE += cnt_offset; + sys_safe_access_disable(); + } + + // 细调 + // 配置细调参数后，丢弃2次捕获值（软件行为）上判断已有一次，这里只留一次 + sys_safe_access_enable(); + R8_OSC_CAL_CTRL &= ~RB_OSC_CNT_TOTAL; + R8_OSC_CAL_CTRL |= cali_Lv; + sys_safe_access_disable(); + while( (R8_OSC_CAL_CTRL & RB_OSC_CNT_TOTAL) != cali_Lv ) + { + sys_safe_access_enable(); + R8_OSC_CAL_CTRL |= cali_Lv; + sys_safe_access_disable(); + } + + sys_safe_access_enable(); + R8_OSC_CAL_CTRL &= ~RB_OSC_CNT_EN; + R8_OSC_CAL_CTRL |= RB_OSC_CNT_EN; + R16_OSC_CAL_CNT |= RB_OSC_CAL_OV_CLR; + R16_OSC_CAL_CNT |= RB_OSC_CAL_IF; + sys_safe_access_disable(); + while( (R8_OSC_CAL_CTRL & RB_OSC_CNT_EN) == 0 ) + { + sys_safe_access_enable(); + R8_OSC_CAL_CTRL |= RB_OSC_CNT_EN; + sys_safe_access_disable(); + } + + while(!(R8_OSC_CAL_CTRL & RB_OSC_CNT_HALT)); // 用于丢弃 + + SYS_DisableAllIrq(&irqv); + sys_safe_access_enable(); + R8_OSC_CAL_CTRL &= ~RB_OSC_CNT_EN; + R8_OSC_CAL_CTRL |= RB_OSC_CNT_EN; + R16_OSC_CAL_CNT |= RB_OSC_CAL_OV_CLR; + R16_OSC_CAL_CNT |= RB_OSC_CAL_IF; + sys_safe_access_disable(); + while( (R8_OSC_CAL_CTRL & RB_OSC_CNT_EN) == 0 ) + { + sys_safe_access_enable(); + R8_OSC_CAL_CTRL |= RB_OSC_CNT_EN; + sys_safe_access_disable(); + } + + while(R8_OSC_CAL_CTRL & RB_OSC_CNT_HALT); + cnt_32k = RTC_GetCycle32k(); + while(RTC_GetCycle32k() == cnt_32k); + R16_OSC_CAL_CNT |= RB_OSC_CAL_OV_CLR; + SYS_RecoverIrq(irqv); + while(!(R8_OSC_CAL_CTRL & RB_OSC_CNT_HALT)); + sys_safe_access_enable(); + R8_OSC_CAL_CTRL &= ~RB_OSC_CNT_EN; + sys_safe_access_disable(); + i = R16_OSC_CAL_CNT; // 实时校准后采样值 + cnt_offset = (i & 0x3FFF) + R8_OSC_CAL_OV_CNT * 0x3FFF - 4000 * (1 << cali_Lv) * (freq_sys / 1000000) / 256 * 1000/(CAB_LSIFQ/256); + cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2*(100 )) / (1366 * ((1 << cali_Lv)/8) * (freq_sys/1000) / 60000)) + 1) / 2) : ((((cnt_offset * 2*(100)) / (1366 * ((1 << cali_Lv)/8) * (freq_sys/1000) / 60000)) - 1) / 2); + if((cnt_offset > 0)&&(((R16_INT32K_TUNE>>5)+cnt_offset)>0xFF)) + { + if(retry_all>2) + { + sys_safe_access_enable(); + R16_INT32K_TUNE |= (0xFF<<5); + sys_safe_access_disable(); + return; + } + else + { + sys_safe_access_enable(); + R16_INT32K_TUNE = (R16_INT32K_TUNE&0x1F)|(0x7F<<5); + sys_safe_access_disable(); + } + } + else if((cnt_offset < 0)&&((R16_INT32K_TUNE>>5)<(-cnt_offset))) + { + if(retry_all>2) + { + sys_safe_access_enable(); + R16_INT32K_TUNE &= 0x1F; + sys_safe_access_disable(); + return; + } + else + { + sys_safe_access_enable(); + R16_INT32K_TUNE = (R16_INT32K_TUNE&0x1F)|(0x7F<<5); + sys_safe_access_disable(); + } + } + else + { + sys_safe_access_enable(); + R16_INT32K_TUNE += (cnt_offset<<5); + sys_safe_access_disable(); + return; + } + retry_all++; + + } +} + +/********************************************************************* + * @fn RTCInitTime + * + * @brief RTC时钟初始化当前时间 + * + * @param y - 配置年，MAX_Y = BEGYEAR + 44 + * @param mon - 配置月，MAX_MON = 12 + * @param d - 配置日，MAX_D = 31 + * @param h - 配置小时，MAX_H = 23 + * @param m - 配置分钟，MAX_M = 59 + * @param s - 配置秒，MAX_S = 59 + * + * @return none + */ +void RTC_InitTime(uint16_t y, uint16_t mon, uint16_t d, uint16_t h, uint16_t m, uint16_t s) +{ + uint32_t t; + uint16_t year, month, day, sec2, t32k; + volatile uint8_t clk_pin; + + year = y; + month = mon; + day = 0; + while(year > BEGYEAR) + { + day += YearLength(year - 1); + year--; + } + while(month > 1) + { + day += monthLength(IsLeapYear(y), month - 2); + month--; + } + + day += d - 1; + sec2 = (h % 24) * 1800 + m * 30 + s / 2; + t32k = (s & 1) ? (0x8000) : (0); + t = sec2; + t = t << 16 | t32k; + + do + { + clk_pin = (R8_CK32K_CONFIG & RB_32K_CLK_PIN); + } while(clk_pin != (R8_CK32K_CONFIG & RB_32K_CLK_PIN)); + if(!clk_pin) + { + while(!clk_pin) + { + do + { + clk_pin = (R8_CK32K_CONFIG & RB_32K_CLK_PIN); + } while(clk_pin != (R8_CK32K_CONFIG & RB_32K_CLK_PIN)); + } + } + + sys_safe_access_enable(); + R32_RTC_TRIG = day; + R8_RTC_MODE_CTRL |= RB_RTC_LOAD_HI; + sys_safe_access_disable(); + while((R32_RTC_TRIG & 0x3FFF) != (R32_RTC_CNT_DAY & 0x3FFF)); + sys_safe_access_enable(); + R32_RTC_TRIG = t; + R8_RTC_MODE_CTRL |= RB_RTC_LOAD_LO; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn RTC_GetTime + * + * @brief 获取当前时间 + * + * @param py - 获取到的年，MAX_Y = BEGYEAR + 44 + * @param pmon - 获取到的月，MAX_MON = 12 + * @param pd - 获取到的日，MAX_D = 31 + * @param ph - 获取到的小时，MAX_H = 23 + * @param pm - 获取到的分钟，MAX_M = 59 + * @param ps - 获取到的秒，MAX_S = 59 + * + * @return none + */ +void RTC_GetTime(uint16_t *py, uint16_t *pmon, uint16_t *pd, uint16_t *ph, uint16_t *pm, uint16_t *ps) +{ + uint32_t t; + uint16_t day, sec2, t32k; + + day = R32_RTC_CNT_DAY & 0x3FFF; + sec2 = R16_RTC_CNT_2S; + t32k = R16_RTC_CNT_32K; + + t = sec2 * 2 + ((t32k < 0x8000) ? 0 : 1); + + *py = BEGYEAR; + while(day >= YearLength(*py)) + { + day -= YearLength(*py); + (*py)++; + } + + *pmon = 0; + while(day >= monthLength(IsLeapYear(*py), *pmon)) + { + day -= monthLength(IsLeapYear(*py), *pmon); + (*pmon)++; + } + (*pmon)++; + *pd = day + 1; + *ph = t / 3600; + *pm = t % 3600 / 60; + *ps = t % 60; +} + +/********************************************************************* + * @fn RTC_SetCycle32k + * + * @brief 基于LSE/LSI时钟，配置当前RTC 周期数 + * + * @param cyc - 配置周期计数初值，MAX_CYC = 0xA8BFFFFF = 2831155199 + * + * @return none + */ +void RTC_SetCycle32k(uint32_t cyc) +{ + volatile uint8_t clk_pin; + + do + { + clk_pin = (R8_CK32K_CONFIG & RB_32K_CLK_PIN); + } while((clk_pin != (R8_CK32K_CONFIG & RB_32K_CLK_PIN)) || (!clk_pin)); + + sys_safe_access_enable(); + R32_RTC_TRIG = cyc; + R8_RTC_MODE_CTRL |= RB_RTC_LOAD_LO; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn RTC_GetCycle32k + * + * @brief 基于LSE/LSI时钟，获取当前RTC 周期数 + * + * @param none + * + * @return 当前周期数，MAX_CYC = 0xA8BFFFFF = 2831155199 + */ +uint32_t RTC_GetCycle32k(void) +{ + volatile uint32_t i; + + do + { + i = R32_RTC_CNT_32K; + } while(i != R32_RTC_CNT_32K); + + return (i); +} +/********************************************************************* + * @fn RTC_TMRFunCfg + * + * @brief RTC定时模式配置（注意定时基准固定为32768Hz） + * + * @param t - refer to RTC_TMRCycTypeDef + * + * @return none + */ +void RTC_TMRFunCfg(RTC_TMRCycTypeDef t) +{ + sys_safe_access_enable(); + R8_RTC_MODE_CTRL &= ~(RB_RTC_TMR_EN | RB_RTC_TMR_MODE); + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_RTC_MODE_CTRL |= RB_RTC_TMR_EN | (t); + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn RTC_TRIGFunCfg + * + * @brief RTC时间触发模式配置 + * + * @param cyc - 相对当前时间的触发间隔时间，基于LSE/LSI时钟周期数 + * + * @return none + */ +void RTC_TRIGFunCfg(uint32_t cyc) +{ + uint32_t t; + + t = RTC_GetCycle32k() + cyc; + if(t > RTC_MAX_COUNT) + { + t -= RTC_MAX_COUNT; + } + + sys_safe_access_enable(); + R32_RTC_TRIG = t; + R8_RTC_MODE_CTRL |= RB_RTC_TRIG_EN; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn RTC_ModeFunDisable + * + * @brief RTC 模式功能关闭 + * + * @param m - 需要关闭的当前模式 + * + * @return none + */ +void RTC_ModeFunDisable(RTC_MODETypeDef m) +{ + uint8_t i = 0; + + if(m == RTC_TRIG_MODE) + { + i |= RB_RTC_TRIG_EN; + } + else if(m == RTC_TMR_MODE) + { + i |= RB_RTC_TMR_EN; + } + + sys_safe_access_enable(); + R8_RTC_MODE_CTRL &= ~(i); + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn RTC_GetITFlag + * + * @brief 获取RTC中断标志 + * + * @param f - refer to RTC_EVENTTypeDef + * + * @return 中断标志状态 + */ +uint8_t RTC_GetITFlag(RTC_EVENTTypeDef f) +{ + if(f == RTC_TRIG_EVENT) + { + return (R8_RTC_FLAG_CTRL & RB_RTC_TRIG_FLAG); + } + else + { + return (R8_RTC_FLAG_CTRL & RB_RTC_TMR_FLAG); + } +} + +/********************************************************************* + * @fn RTC_ClearITFlag + * + * @brief 清除RTC中断标志 + * + * @param f - refer to RTC_EVENTTypeDef + * + * @return none + */ +void RTC_ClearITFlag(RTC_EVENTTypeDef f) +{ + switch(f) + { + case RTC_TRIG_EVENT: + R8_RTC_FLAG_CTRL = RB_RTC_TRIG_CLR; + break; + case RTC_TMR_EVENT: + R8_RTC_FLAG_CTRL = RB_RTC_TMR_CLR; + break; + default: + break; + } +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_flash.c b/nametag8_CH592/StdPeriphDriver/CH59x_flash.c new file mode 100644 index 0000000..a8caab8 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_flash.c @@ -0,0 +1,183 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_flash.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/* RESET_EN */ +#define RESET_Enable 0x00000008 +#define RESET_Disable 0xFFFFFFF7 + +/* LOCKUP_RST_EN */ +#define UART_NO_KEY_Enable 0x00000100 +#define UART_NO_KEY_Disable 0xFFFFFEFF + +/* BOOT_PIN */ +#define BOOT_PIN_PB22 0x00000200 +#define BOOT_PIN_PB11 0xFFFFFDFF + +/* FLASH_WRProt */ +#define FLASH_WRProt 0xFFF003FF + +/********************************************************************* + * @fn FLASH_ROM_READ + * + * @brief Read Flash + * + * @param StartAddr - read address + * @param Buffer - read buffer + * @param len - read len + * + * @return none + */ +void FLASH_ROM_READ(uint32_t StartAddr, void *Buffer, uint32_t len) +{ + uint32_t i, Length = (len + 3) >> 2; + uint32_t *pCode = (uint32_t *)StartAddr; + uint32_t *pBuf = (uint32_t *)Buffer; + + for(i = 0; i < Length; i++) + { + *pBuf++ = *pCode++; + } +} + +/********************************************************************* + * @fn UserOptionByteConfig + * + * @brief Configure User Option Byte.需在调用用户配置字生效函数后生效,且每次烧录后只能修改一次 + * (使用该函数，必须使用官方提供的.S文件，同时调用该函数后，两次上电后，两线调试接口默认关闭) + * + * @param RESET_EN - 外部复位引脚使能 + * @param BOOT_PIN - ENABLE-使用默认boot脚-PB22,DISABLE-使用boot脚-PB11 + * @param UART_NO_KEY_EN - 串口免按键下载使能 + * @param FLASHProt_Size - 写保护大小(单位4K) + * + * @return 0-Success, 1-Err + */ +uint8_t UserOptionByteConfig(FunctionalState RESET_EN, FunctionalState BOOT_PIN, FunctionalState UART_NO_KEY_EN, + uint32_t FLASHProt_Size) +{ + uint32_t s, t; + + FLASH_ROM_READ(0x14, &s, 4); + + if(s == 0xF5F9BDA9) + { + s = 0; + FLASH_EEPROM_CMD(CMD_GET_ROM_INFO, 0x7EFFC, &s, 4); + s &= 0xFF; + + if(RESET_EN == ENABLE) + s |= RESET_Enable; + else + s &= RESET_Disable; + + /* bit[7:0]-bit[31-24] */ + s |= ((~(s << 24)) & 0xFF000000); //高8位 配置信息取反； + + if(BOOT_PIN == ENABLE) + s |= BOOT_PIN_PB22; + if(UART_NO_KEY_EN == ENABLE) + s |= UART_NO_KEY_Enable; + + /* bit[23-10] */ + s &= 0xFF0003FF; + s |= ((FLASHProt_Size << 10) | (5 << 20)) & 0x00FFFC00; + + /*Write user option byte*/ + FLASH_ROM_WRITE(0x14, &s, 4); + + /* Verify user option byte */ + FLASH_ROM_READ(0x14, &t, 4); + + if(s == t) + return 0; + else + return 1; + } + + return 1; +} + +/********************************************************************* + * @fn UserOptionByteClose_SWD + * + * @brief 关两线调试接口，其余配置值保持不变.需在调用用户配置字生效函数后生效,且每次烧录后只能修改一次 + * (使用该函数，必须使用官方提供的.S文件，同时调用该函数后，两次上电后，两线调试接口默认关闭) + * + * @return 0-Success, 1-Err + */ +uint8_t UserOptionByteClose_SWD(void) +{ + uint32_t s, t; + + FLASH_ROM_READ(0x14, &s, 4); + + if(s == 0xF5F9BDA9) + { + FLASH_EEPROM_CMD(CMD_GET_ROM_INFO, 0x7EFFC, &s, 4); + + s &= ~((1 << 4) | (1 << 7)); //禁用调试功能， 禁用SPI读写FLASH + + /* bit[7:0]-bit[31-24] */ + s &= 0x00FFFFFF; + s |= ((~(s << 24)) & 0xFF000000); //高8位 配置信息取反； + + /*Write user option byte*/ + FLASH_ROM_WRITE(0x14, &s, 4); + + /* Verify user option byte */ + FLASH_ROM_READ(0x14, &t, 4); + + if(s == t) + return 0; + else + return 1; + } + + return 1; +} + +/********************************************************************* + * @fn UserOptionByte_Active + * + * @brief 用户配置字生效函数，执行后自动复位 + * + * @return 0-Success, 1-Err + */ +void UserOptionByte_Active(void) +{ + FLASH_ROM_SW_RESET(); + sys_safe_access_enable(); + R16_INT32K_TUNE = 0xFFFF; + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_RST_WDOG_CTRL |= RB_SOFTWARE_RESET; + sys_safe_access_disable(); + while(1); +} + +/********************************************************************* + * @fn GET_UNIQUE_ID + * + * @brief get 64 bit unique ID + * + * @param Buffer - Pointer to the buffer where data should be stored, Must be aligned to 4 bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +void GET_UNIQUE_ID(uint8_t *Buffer) +{ + FLASH_EEPROM_CMD( CMD_GET_ROM_INFO, ROM_CFG_MAC_ADDR, Buffer, 0 ); + Buffer[6] = 0; + Buffer[7] = 0; +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_gpio.c b/nametag8_CH592/StdPeriphDriver/CH59x_gpio.c new file mode 100644 index 0000000..0f1fdbd --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_gpio.c @@ -0,0 +1,263 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_gpio.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn GPIOA_ModeCfg + * + * @brief GPIOA端口引脚模式配置 + * + * @param pin - PA0-PA15 + * @param mode - 输入输出类型 + * + * @return none + */ +void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode) +{ + switch(mode) + { + case GPIO_ModeIN_Floating: + R32_PA_PD_DRV &= ~pin; + R32_PA_PU &= ~pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU: + R32_PA_PD_DRV &= ~pin; + R32_PA_PU |= pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD: + R32_PA_PD_DRV |= pin; + R32_PA_PU &= ~pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeOut_PP_5mA: + R32_PA_PD_DRV &= ~pin; + R32_PA_DIR |= pin; + break; + + case GPIO_ModeOut_PP_20mA: + R32_PA_PD_DRV |= pin; + R32_PA_DIR |= pin; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn GPIOB_ModeCfg + * + * @brief GPIOB端口引脚模式配置 + * + * @param pin - PB0-PB23 + * @param mode - 输入输出类型 + * + * @return none + */ +void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode) +{ + switch(mode) + { + case GPIO_ModeIN_Floating: + R32_PB_PD_DRV &= ~pin; + R32_PB_PU &= ~pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU: + R32_PB_PD_DRV &= ~pin; + R32_PB_PU |= pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD: + R32_PB_PD_DRV |= pin; + R32_PB_PU &= ~pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeOut_PP_5mA: + R32_PB_PD_DRV &= ~pin; + R32_PB_DIR |= pin; + break; + + case GPIO_ModeOut_PP_20mA: + R32_PB_PD_DRV |= pin; + R32_PB_DIR |= pin; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn GPIOA_ITModeCfg + * + * @brief GPIOA引脚中断模式配置 + * + * @param pin - PA0-PA15 + * @param mode - 触发类型 + * + * @return none + */ +void GPIOA_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode) +{ + switch(mode) + { + case GPIO_ITMode_LowLevel: // 低电平触发 + R16_PA_INT_MODE &= ~pin; + R32_PA_CLR |= pin; + break; + + case GPIO_ITMode_HighLevel: // 高电平触发 + R16_PA_INT_MODE &= ~pin; + R32_PA_OUT |= pin; + break; + + case GPIO_ITMode_FallEdge: // 下降沿触发 + R16_PA_INT_MODE |= pin; + R32_PA_CLR |= pin; + break; + + case GPIO_ITMode_RiseEdge: // 上升沿触发 + R16_PA_INT_MODE |= pin; + R32_PA_OUT |= pin; + break; + + default: + break; + } + R16_PA_INT_IF = pin; + R16_PA_INT_EN |= pin; +} + +/********************************************************************* + * @fn GPIOB_ITModeCfg + * + * @brief GPIOB引脚中断模式配置 + * + * @param pin - PB0-PB23 + * @param mode - 触发类型 + * + * @return none + */ +void GPIOB_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode) +{ + uint32_t Pin = pin | ((pin & (GPIO_Pin_22 | GPIO_Pin_23)) >> 14); + switch(mode) + { + case GPIO_ITMode_LowLevel: // 低电平触发 + R16_PB_INT_MODE &= ~Pin; + R32_PB_CLR |= pin; + break; + + case GPIO_ITMode_HighLevel: // 高电平触发 + R16_PB_INT_MODE &= ~Pin; + R32_PB_OUT |= pin; + break; + + case GPIO_ITMode_FallEdge: // 下降沿触发 + R16_PB_INT_MODE |= Pin; + R32_PB_CLR |= pin; + break; + + case GPIO_ITMode_RiseEdge: // 上升沿触发 + R16_PB_INT_MODE |= Pin; + R32_PB_OUT |= pin; + break; + + default: + break; + } + R16_PB_INT_IF = Pin; + R16_PB_INT_EN |= Pin; +} + +/********************************************************************* + * @fn GPIOPinRemap + * + * @brief 外设功能引脚映射 + * + * @param s - 是否使能映射 + * @param perph - RB_RF_ANT_SW_EN - RF antenna switch control output on PA4/PA5/PA12/PA13/PA14/PA15 + * RB_PIN_U0_INV - RXD0/RXD0_/TXD0/TXD0_ invert input/output + * RB_PIN_INTX - INTX: INT24/INT25 PB8/PB9 -> INT24_/INT25_ PB22/PB23 + * RB_PIN_MODEM - MODEM: PA6/PA7 -> PB12/PB13 + * RB_PIN_I2C - I2C: PB14/PB15 -> PB14/PB15 + * RB_PIN_PWMX - PWMX: PA12/PA13 -> PA6/PA7 + * RB_PIN_SPI0 - SPI0: PA12/PA13/PA14/PA15 -> PB12/PB13/PB14/PB15 + * RB_PIN_UART3 - UART3: PA4/PA5 -> PA4/PA5 + * RB_PIN_UART2 - UART2: PB22/PB23 -> PA6/PA7 + * RB_PIN_UART1 - UART1: PA8/PA9 -> PB12/PB13 + * RB_PIN_UART0 - UART0: PB4/PB7 -> PA15/PA14 + * RB_PIN_TMR3 - TMR2: PB22 -> PB22 + * RB_PIN_TMR2 - TMR2: PA11 -> PB11 + * RB_PIN_TMR1 - TMR1: PA10 -> PB10 + * RB_PIN_TMR0 - TMR0: PA9 -> PB23 + * + * @return none + */ +void GPIOPinRemap(FunctionalState s, uint16_t perph) +{ + if(s) + { + R16_PIN_ALTERNATE |= perph; + } + else + { + R16_PIN_ALTERNATE &= ~perph; + } +} + +/********************************************************************* + * @fn GPIOAGPPCfg + * + * @brief 模拟外设GPIO引脚功能控制 + * + * @param s - ENABLE - 打开模拟外设功能，关闭数字功能 + * DISABLE - 启用数字功能，关闭模拟外设功能 + * @param perph - RB_PIN_ADC8_9_IE - ADC/TKEY 9/8通道 + * RB_PIN_ADC6_7_IE - ADC/TKEY 7/6通道 + * RB_PIN_ADC10_IE - ADC/TKEY 10通道 + * RB_PIN_ADC11_IE - ADC/TKEY 11 通道 + * RB_PIN_USB2_DP_PU - USB2 U2D+引脚内部上拉电阻 + * RB_PIN_USB2_IE - USB2引脚 + * RB_PIN_USB_DP_PU - USB UD+引脚内部上拉电阻 + * RB_PIN_USB_IE - USB 引脚 + * RB_PIN_ADC0_IE - ADC/TKEY 0 通道 + * RB_PIN_ADC1_IE - ADC/TKEY 1 通道 + * RB_PIN_ADC12_IE - ADC/TKEY 12 通道 + * RB_PIN_ADC13_IE - ADC/TKEY 13 通道 + * RB_PIN_XT32K_IE - 32KHz晶振LSE引脚 + * RB_PIN_ADC2_3_IE - ADC/TKEY 2/3 通道 + * RB_PIN_ADC4_5_IE - ADC/TKEY 4/5 通道 + * + * @return none + */ +void GPIOAGPPCfg(FunctionalState s, uint16_t perph) +{ + if(s) + { + R16_PIN_ANALOG_IE |= perph; + } + else + { + R16_PIN_ANALOG_IE &= ~perph; + } +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_i2c.c b/nametag8_CH592/StdPeriphDriver/CH59x_i2c.c new file mode 100644 index 0000000..51c4a09 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_i2c.c @@ -0,0 +1,672 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_i2c.c + * Author : WCH + * Version : V1.0 + * Date : 2021/03/15 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * + * @param I2C_Mode - refer to I2C_ModeTypeDef + * @param I2C_ClockSpeed - Specifies the clock frequency(Hz). + * This parameter must be set to a value lower than 400kHz + * @param I2C_DutyCycle - Specifies the I2C fast mode duty cycle.refer to I2C_DutyTypeDef + * @param I2C_Ack - Enables or disables the acknowledgement.refer to I2C_AckTypeDef + * @param I2C_AckAddr - Specifies if 7-bit or 10-bit address is acknowledged.refer to I2C_AckAddrTypeDef + * @param I2C_OwnAddress1 - Specifies the first device own address. + * This parameter can be a 7-bit or 10-bit address. + * + * @return none + */ +void I2C_Init(I2C_ModeTypeDef I2C_Mode, UINT32 I2C_ClockSpeed, I2C_DutyTypeDef I2C_DutyCycle, + I2C_AckTypeDef I2C_Ack, I2C_AckAddrTypeDef I2C_AckAddr, UINT16 I2C_OwnAddress1) +{ + uint32_t sysClock; + uint16_t tmpreg; + + I2C_SoftwareResetCmd(ENABLE); + I2C_SoftwareResetCmd(DISABLE); + + sysClock = GetSysClock(); + + R16_I2C_CTRL2 &= ~RB_I2C_FREQ; + R16_I2C_CTRL2 |= (sysClock / 1000000); + + R16_I2C_CTRL1 &= ~RB_I2C_PE; + + if(I2C_ClockSpeed <= 100000) + { + tmpreg = (sysClock / (I2C_ClockSpeed << 1)) & RB_I2C_CCR; + + if(tmpreg < 0x04) + tmpreg = 0x04; + + R16_I2C_RTR = (((sysClock / 1000000) + 1) > 0x3F) ? 0x3F : ((sysClock / 1000000) + 1); + } + else + { + if(I2C_DutyCycle == I2C_DutyCycle_2) + { + tmpreg = (sysClock / (I2C_ClockSpeed * 3)) & RB_I2C_CCR; + } + else + { + tmpreg = (sysClock / (I2C_ClockSpeed * 25)) & RB_I2C_CCR; + tmpreg |= I2C_DutyCycle_16_9; + } + + if(tmpreg == 0) + { + tmpreg |= (uint16_t)0x0001; + } + + tmpreg |= RB_I2C_F_S; + R16_I2C_RTR = (uint16_t)((((sysClock / 1000000) * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + R16_I2C_CKCFGR = tmpreg; + + R16_I2C_CTRL1 |= RB_I2C_PE; + + R16_I2C_CTRL1 &= ~(RB_I2C_SMBUS | RB_I2C_SMBTYPE | RB_I2C_ACK); + R16_I2C_CTRL1 |= I2C_Mode | I2C_Ack; + + R16_I2C_OADDR1 &= ~0xFFFF; + R16_I2C_OADDR1 |= I2C_AckAddr | I2C_OwnAddress1; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_PE; + else + R16_I2C_CTRL1 &= ~RB_I2C_PE; +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_START; + else + R16_I2C_CTRL1 &= ~RB_I2C_START; +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_STOP; + else + R16_I2C_CTRL1 &= ~RB_I2C_STOP; +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_ACK; + else + R16_I2C_CTRL1 &= ~RB_I2C_ACK; +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(uint8_t Address) +{ + R16_I2C_OADDR2 &= ~RB_I2C_ADD2; + R16_I2C_OADDR2 |= (uint16_t)(Address & RB_I2C_ADD2); +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_OADDR2 |= RB_I2C_ENDUAL; + else + R16_I2C_OADDR2 &= ~RB_I2C_ENDUAL; +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_ENGC; + else + R16_I2C_CTRL1 &= ~RB_I2C_ENGC; +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_ITTypeDef I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL2 |= I2C_IT; + else + R16_I2C_CTRL2 &= (uint16_t)~I2C_IT; +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(uint8_t Data) +{ + R16_I2C_DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(void) +{ + return (uint8_t)R16_I2C_DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param Address - specifies the slave address which will be transmitted. + * @param I2C_Direction - specifies whether the I2C device will be a Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + Address |= OADDR1_ADD0_Set; + else + Address &= OADDR1_ADD0_Reset; + + R16_I2C_DATAR = Address; +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_SWRST; + else + R16_I2C_CTRL1 &= ~RB_I2C_SWRST; +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the last received byte. + * + * @return none + */ +void I2C_NACKPositionConfig(uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + R16_I2C_CTRL1 |= I2C_NACKPosition_Next; + else + R16_I2C_CTRL1 &= I2C_NACKPosition_Current; +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + R16_I2C_CTRL1 |= I2C_SMBusAlert_Low; + else + R16_I2C_CTRL1 &= I2C_SMBusAlert_High; +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_PEC; + else + R16_I2C_CTRL1 &= ~RB_I2C_PEC; +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + R16_I2C_CTRL1 |= I2C_PECPosition_Next; + else + R16_I2C_CTRL1 &= I2C_PECPosition_Current; +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_ENPEC; + else + R16_I2C_CTRL1 &= ~RB_I2C_ENPEC; +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(void) +{ + return (R16_I2C_STAR2 >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ARPCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + R16_I2C_CTRL1 |= RB_I2C_EBARP; + else + R16_I2C_CTRL1 &= ~RB_I2C_EBARP; +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + R16_I2C_CTRL1 |= RB_I2C_NOSTRETCH; + else + R16_I2C_CTRL1 &= ~RB_I2C_NOSTRETCH; +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + R16_I2C_CKCFGR &= ~I2C_DutyCycle_16_9; + else + R16_I2C_CKCFGR |= I2C_DutyCycle_16_9; +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed as parameter. + * + * @param I2C_EVENT - specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3. + * I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED : EV4. + * I2C_EVENT_MASTER_MODE_SELECT : EV5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6. + * I2C_EVENT_MASTER_BYTE_RECEIVED : EV7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9. + * + * @return 1 - SUCCESS or 0 - ERROR. + */ +uint8_t I2C_CheckEvent(uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + uint8_t status = 0; + + flag1 = R16_I2C_STAR1; + flag2 = R16_I2C_STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = !0; + } + else + { + status = 0; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @return The last event. + */ +uint32_t I2C_GetLastEvent(void) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = R16_I2C_STAR1; + flag2 = R16_I2C_STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed as parameter. + * + * @param I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE - Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)BA_I2C; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * + * @return none + */ +void I2C_ClearFlag(uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + R16_I2C_STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param II2C_IT - specifies the interrupt source to check. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE - Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (R16_I2C_CTRL2)); + I2C_IT &= FLAG_Mask; + + if(((R16_I2C_STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * + * @return none + */ +void I2C_ClearITPendingBit(uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + R16_I2C_STAR1 = (uint16_t)~flagpos; +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_lcd.c b/nametag8_CH592/StdPeriphDriver/CH59x_lcd.c new file mode 100644 index 0000000..04c0052 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_lcd.c @@ -0,0 +1,32 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_lcd.c + * Author : WCH + * Version : V1.0 + * Date : 2018/12/15 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" +#include "CH59x_lcd.h" + +/******************************************************************************* +* Function Name : LCD_DefInit +* Description : LCD段式屏驱动初始化配置 +* Input : duty 占空比 +* bias 偏压比 +* Return : None +*******************************************************************************/ +void LCD_Init(LCDDutyTypeDef duty, LCDBiasTypeDef bias) +{ + R32_PIN_CONFIG2 = 0xfffeff3f; // 关闭数字输入 + R16_PIN_ALTERNATE |= RB_DEBUG_EN; // 操作LCD时，需关闭debug + R32_LCD_CMD = 0x1ffff << 8; + R32_LCD_CMD |= RB_LCD_SYS_EN | RB_LCD_ON | + (LCD_CLK_128 << 5) | + (duty << 3) | + (bias << 2); +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_pwm.c b/nametag8_CH592/StdPeriphDriver/CH59x_pwm.c new file mode 100644 index 0000000..915fb4d --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_pwm.c @@ -0,0 +1,171 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_pwm.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn PWMX_CycleCfg + * + * @brief PWM4-PWM11周期配置 + * + * @param cyc - refer to PWMX_CycleTypeDef + * + * @return none + */ +void PWMX_CycleCfg(PWMX_CycleTypeDef cyc) +{ + switch(cyc) + { + case PWMX_Cycle_256: + R8_PWM_CONFIG = R8_PWM_CONFIG & 0xf0; + break; + + case PWMX_Cycle_255: + R8_PWM_CONFIG = (R8_PWM_CONFIG & 0xf0) | 0x01; + break; + + case PWMX_Cycle_128: + R8_PWM_CONFIG = (R8_PWM_CONFIG & 0xf0) | (1 << 2); + break; + + case PWMX_Cycle_127: + R8_PWM_CONFIG = (R8_PWM_CONFIG & 0xf0) | (1 << 2) | 0x01; + break; + + case PWMX_Cycle_64: + R8_PWM_CONFIG = (R8_PWM_CONFIG & 0xf0) | (2 << 2); + break; + + case PWMX_Cycle_63: + R8_PWM_CONFIG = (R8_PWM_CONFIG & 0xf0) | (2 << 2) | 0x01; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn PWMX_16bit_CycleCfg + * + * @brief PWM4-PWM9 16位周期配置 + * + * @param cyc - 16位周期 + * + * @return none + */ +void PWMX_16bit_CycleCfg(uint16_t cyc) +{ + R8_PWM_CONFIG = (R8_PWM_CONFIG & 0xf0) | (3 << 2); + R32_PWM_REG_CYCLE = cyc; +} + +/********************************************************************* + * @fn PWMX_16bit_ACTOUT + * + * @brief PWM4-PWM9 通道16位输出波形配置 + * + * @param ch - select channel of pwm, refer to channel of PWM define + * @param da - effective pulse width + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param s - control pwmx function, ENABLE or DISABLE + * + * @return none + */ +void PWMX_16bit_ACTOUT(uint8_t ch, uint16_t da, PWMX_PolarTypeDef pr, FunctionalState s) +{ + uint8_t i; + + if(s == DISABLE) + { + R8_PWM_OUT_EN &= ~(ch); + } + else + { + (pr) ? (R8_PWM_POLAR |= (ch)) : (R8_PWM_POLAR &= ~(ch)); + for(i = 0; i < 6; i++) + { + if((ch >> i) & 1) + { + if(i<4) + { + *((volatile uint16_t *)((&R16_PWM4_DATA) + i)) = da; + } + else + { + *((volatile uint16_t *)((&R16_PWM8_DATA) + (i-4))) = da; + } + } + } + R8_PWM_OUT_EN |= (ch); + } +} + +/********************************************************************* + * @fn PWMX_ACTOUT + * + * @brief PWM4-PWM11通道输出波形配置 + * + * @param ch - select channel of pwm, refer to channel of PWM define + * @param da - effective pulse width + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param s - control pwmx function, ENABLE or DISABLE + * + * @return none + */ +void PWMX_ACTOUT(uint8_t ch, uint8_t da, PWMX_PolarTypeDef pr, FunctionalState s) +{ + uint8_t i; + + if(s == DISABLE) + { + R8_PWM_OUT_EN &= ~(ch); + } + else + { + (pr) ? (R8_PWM_POLAR |= (ch)) : (R8_PWM_POLAR &= ~(ch)); + for(i = 0; i < 8; i++) + { + if((ch >> i) & 1) + { + *((volatile uint8_t *)((&R8_PWM4_DATA) + i)) = da; + } + } + R8_PWM_OUT_EN |= (ch); + } +} + +/********************************************************************* + * @fn PWMX_AlterOutCfg + * + * @brief PWM 交替输出模式配置 + * + * @param ch - select group of PWM alternate output + * RB_PWM4_5_STAG_EN - PWM4 和 PWM5 通道交替输出 + * RB_PWM6_7_STAG_EN - PWM6 和 PWM7 通道交替输出 + * RB_PWM8_9_STAG_EN - PWM8 和 PWM9 通道交替输出 + * RB_PWM10_11_STAG_EN - PWM10 和 PWM11 通道交替输出 + * @param s - control pwmx function, ENABLE or DISABLE + * + * @return none + */ +void PWMX_AlterOutCfg(uint8_t ch, FunctionalState s) +{ + if(s == DISABLE) + { + R8_PWM_CONFIG &= ~(ch); + } + else + { + R8_PWM_CONFIG |= (ch); + } +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_pwr.c b/nametag8_CH592/StdPeriphDriver/CH59x_pwr.c new file mode 100644 index 0000000..0183448 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_pwr.c @@ -0,0 +1,409 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_pwr.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn PWR_DCDCCfg + * + * @brief 启用内部DC/DC电源，用于节约系统功耗 + * + * @param s - 是否打开DCDC电源 + * + * @return none + */ +void PWR_DCDCCfg(FunctionalState s) +{ + uint16_t adj = R16_AUX_POWER_ADJ; + uint16_t plan = R16_POWER_PLAN; + + if(s == DISABLE) + { + + adj &= ~RB_DCDC_CHARGE; + plan &= ~(RB_PWR_DCDC_EN | RB_PWR_DCDC_PRE); // 旁路 DC/DC + sys_safe_access_enable(); + R16_AUX_POWER_ADJ = adj; + R16_POWER_PLAN = plan; + sys_safe_access_disable(); + } + else + { + uint32_t HW_Data[2]; + FLASH_EEPROM_CMD(CMD_GET_ROM_INFO, ROM_CFG_ADR_HW, HW_Data, 0); + if((HW_Data[0]) & (1 << 13)) + { + return; + } + adj |= RB_DCDC_CHARGE; + plan |= RB_PWR_DCDC_PRE; + sys_safe_access_enable(); + R16_AUX_POWER_ADJ = adj; + R16_POWER_PLAN = plan; + sys_safe_access_disable(); + DelayUs(10); + sys_safe_access_enable(); + R16_POWER_PLAN |= RB_PWR_DCDC_EN; + sys_safe_access_disable(); + } +} + +/********************************************************************* + * @fn PWR_UnitModCfg + * + * @brief 可控单元模块的电源控制 + * + * @param s - 是否打开电源 + * @param unit - please refer to unit of controllable power supply + * + * @return none + */ +void PWR_UnitModCfg(FunctionalState s, uint8_t unit) +{ + uint8_t ck32k_cfg = R8_CK32K_CONFIG; + + if(s == DISABLE) //关闭 + { + ck32k_cfg &= ~(unit & 0x03); + } + else //打开 + { + ck32k_cfg |= (unit & 0x03); + } + + sys_safe_access_enable(); + R8_CK32K_CONFIG = ck32k_cfg; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn PWR_PeriphClkCfg + * + * @brief 外设时钟控制位 + * + * @param s - 是否打开对应外设时钟 + * @param perph - please refer to Peripher CLK control bit define + * + * @return none + */ +void PWR_PeriphClkCfg(FunctionalState s, uint16_t perph) +{ + uint32_t sleep_ctrl = R32_SLEEP_CONTROL; + + if(s == DISABLE) + { + sleep_ctrl |= perph; + } + else + { + sleep_ctrl &= ~perph; + } + + sys_safe_access_enable(); + R32_SLEEP_CONTROL = sleep_ctrl; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn PWR_PeriphWakeUpCfg + * + * @brief 睡眠唤醒源配置 + * + * @param s - 是否打开此外设睡眠唤醒功能 + * @param perph - 需要设置的唤醒源 + * RB_SLP_USB_WAKE - USB 为唤醒源 + * RB_SLP_RTC_WAKE - RTC 为唤醒源 + * RB_SLP_GPIO_WAKE - GPIO 为唤醒源 + * RB_SLP_BAT_WAKE - BAT 为唤醒源 + * @param mode - refer to WakeUP_ModeypeDef + * + * @return none + */ +void PWR_PeriphWakeUpCfg(FunctionalState s, uint8_t perph, WakeUP_ModeypeDef mode) +{ + uint8_t m; + + if(s == DISABLE) + { + sys_safe_access_enable(); + R8_SLP_WAKE_CTRL &= ~perph; + sys_safe_access_disable(); + if(perph & RB_SLP_GPIO_WAKE) + { + sys_safe_access_enable(); + R8_SLP_WAKE_CTRL &= ~RB_GPIO_WAKE_MODE; + sys_safe_access_disable(); + } + } + else + { + switch(mode) + { + case Short_Delay: + m = 0x01; + break; + + case Long_Delay: + m = 0x00; + break; + + default: + m = 0x01; + break; + } + + sys_safe_access_enable(); + R8_SLP_WAKE_CTRL |= RB_WAKE_EV_MODE | perph; + sys_safe_access_disable(); + if(perph & RB_SLP_GPIO_WAKE) + { + sys_safe_access_enable(); + R8_SLP_WAKE_CTRL |= RB_GPIO_WAKE_MODE; + sys_safe_access_disable(); + } + sys_safe_access_enable(); + R8_SLP_POWER_CTRL &= ~(RB_WAKE_DLY_MOD); + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_SLP_POWER_CTRL |= m; + sys_safe_access_disable(); + } +} + +/********************************************************************* + * @fn PowerMonitor + * + * @brief 电源监控 + * + * @param s - 是否打开此功能 + * @param vl - refer to VolM_LevelypeDef + * + * @return none + */ +void PowerMonitor(FunctionalState s, VolM_LevelypeDef vl) +{ + uint8_t ctrl = R8_BAT_DET_CTRL; + uint8_t cfg = R8_BAT_DET_CFG; + + if(s == DISABLE) + { + sys_safe_access_enable(); + R8_BAT_DET_CTRL = 0; + sys_safe_access_disable(); + } + else + { + if(vl & 0x80) + { + cfg = vl & 0x03; + ctrl = RB_BAT_MON_EN | ((vl >> 2) & 1); + } + else + { + + cfg = vl & 0x03; + ctrl = RB_BAT_DET_EN; + } + sys_safe_access_enable(); + R8_BAT_DET_CTRL = ctrl; + R8_BAT_DET_CFG = cfg; + sys_safe_access_disable(); + + mDelayuS(1); + sys_safe_access_enable(); + R8_BAT_DET_CTRL |= RB_BAT_LOW_IE | RB_BAT_LOWER_IE; + sys_safe_access_disable(); + } +} + +/********************************************************************* + * @fn LowPower_Idle + * + * @brief 低功耗-Idle模式 + * + * @param none + * + * @return none + */ +__HIGH_CODE +void LowPower_Idle(void) +{ + FLASH_ROM_SW_RESET(); + R8_FLASH_CTRL = 0x04; //flash关闭 + + PFIC->SCTLR &= ~(1 << 2); // sleep + __WFI(); + __nop(); + __nop(); +} + +/********************************************************************* + * @fn LowPower_Halt + * + * @brief 低功耗-Halt模式，此低功耗切到HSI/5时钟运行，唤醒后需要用户自己重新选择系统时钟源 + * + * @param none + * + * @return none + */ +__HIGH_CODE +void LowPower_Halt(void) +{ + uint8_t x32Kpw, x32Mpw; + + FLASH_ROM_SW_RESET(); + R8_FLASH_CTRL = 0x04; //flash关闭 + x32Kpw = R8_XT32K_TUNE; + x32Mpw = R8_XT32M_TUNE; + x32Mpw = (x32Mpw & 0xfc) | 0x03; // 150%额定电流 + x32Kpw = (x32Kpw & 0xfc) | 0x01; // LSE驱动电流降低到额定电流 + + sys_safe_access_enable(); + R8_BAT_DET_CTRL = 0; // 关闭电压监控 + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_XT32K_TUNE = x32Kpw; + R8_XT32M_TUNE = x32Mpw; + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_PLL_CONFIG |= (1 << 5); + sys_safe_access_disable(); + + PFIC->SCTLR |= (1 << 2); //deep sleep + __WFI(); + __nop(); + __nop(); + sys_safe_access_enable(); + R8_PLL_CONFIG &= ~(1 << 5); + sys_safe_access_disable(); +} + +/******************************************************************************* +* Function Name : LowPower_Sleep +* Description : 低功耗-Sleep模式。 + 注意当主频为80M时，睡眠唤醒中断不可调用flash内代码，且退出此函数前需要加上30us延迟。 +* Input : rm: + RB_PWR_RAM2K - 2K retention SRAM 供电 + RB_PWR_RAM24K - 24K main SRAM 供电 + RB_PWR_EXTEND - USB 和 BLE 单元保留区域供电 + RB_PWR_XROM - FlashROM 供电 + NULL - 以上单元都断电 +* Return : None +*******************************************************************************/ +__HIGH_CODE +void LowPower_Sleep(uint16_t rm) +{ + __attribute__((aligned(4))) uint8_t MacAddr[6] = {0}; + uint8_t x32Kpw, x32Mpw; + uint16_t power_plan; + + GetMACAddress(MacAddr); + + x32Kpw = R8_XT32K_TUNE; + x32Mpw = R8_XT32M_TUNE; + x32Mpw = (x32Mpw & 0xfc) | 0x03; // 150%额定电流 + x32Kpw = (x32Kpw & 0xfc) | 0x01; // LSE驱动电流降低到额定电流 + + sys_safe_access_enable(); + R8_BAT_DET_CTRL = 0; // 关闭电压监控 + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_XT32K_TUNE = x32Kpw; + R8_XT32M_TUNE = x32Mpw; + sys_safe_access_disable(); + + sys_safe_access_enable(); + R16_POWER_PLAN &= ~RB_XT_PRE_EN; + sys_safe_access_disable(); + + PFIC->SCTLR |= (1 << 2); //deep sleep + + power_plan = R16_POWER_PLAN & (RB_PWR_DCDC_EN | RB_PWR_DCDC_PRE); + power_plan |= RB_PWR_PLAN_EN | RB_PWR_CORE | rm | (2<<11); + + sys_safe_access_enable(); + R8_SLP_POWER_CTRL |= RB_RAM_RET_LV; + R16_POWER_PLAN = power_plan; + sys_safe_access_disable(); + if((rm & RB_XT_PRE_EN) == 0) + { + sys_safe_access_enable(); + R8_PLL_CONFIG |= (1 << 5); + sys_safe_access_disable(); + } + + __WFI(); + __nop(); + __nop(); + + sys_safe_access_enable(); + R16_POWER_PLAN &= ~RB_XT_PRE_EN; + sys_safe_access_disable(); + + if((rm & RB_XT_PRE_EN) == 0) + { + sys_safe_access_enable(); + R8_PLL_CONFIG &= ~(1 << 5); + sys_safe_access_disable(); + DelayUs(20); + } +} + +/********************************************************************* + * @fn LowPower_Shutdown + * + * @brief 低功耗-Shutdown模式，此低功耗切到HSI/5时钟运行，唤醒后需要用户自己重新选择系统时钟源 + * @note 注意调用此函数，DCDC功能强制关闭，唤醒后可以手动再次打开 + * + * @param rm - 供电模块选择 + * RB_PWR_RAM2K - 2K retention SRAM 供电 + * RB_PWR_RAM16K - 16K main SRAM 供电 + * NULL - 以上单元都断电 + * + * @return none + */ +__HIGH_CODE +void LowPower_Shutdown(uint16_t rm) +{ + uint8_t x32Kpw, x32Mpw; + + FLASH_ROM_SW_RESET(); + x32Kpw = R8_XT32K_TUNE; + x32Mpw = R8_XT32M_TUNE; + x32Mpw = (x32Mpw & 0xfc) | 0x03; // 150%额定电流 + x32Kpw = (x32Kpw & 0xfc) | 0x01; // LSE驱动电流降低到额定电流 + + sys_safe_access_enable(); + R8_BAT_DET_CTRL = 0; // 关闭电压监控 + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_XT32K_TUNE = x32Kpw; + R8_XT32M_TUNE = x32Mpw; + sys_safe_access_disable(); + SetSysClock(CLK_SOURCE_HSE_6_4MHz); + + PFIC->SCTLR |= (1 << 2); //deep sleep + + sys_safe_access_enable(); + R8_SLP_POWER_CTRL |= RB_RAM_RET_LV; + sys_safe_access_disable(); + sys_safe_access_enable(); + R16_POWER_PLAN = RB_PWR_PLAN_EN | rm; + sys_safe_access_disable(); + __WFI(); + __nop(); + __nop(); + FLASH_ROM_SW_RESET(); + sys_safe_access_enable(); + R8_RST_WDOG_CTRL |= RB_SOFTWARE_RESET; + sys_safe_access_disable(); +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_spi0.c b/nametag8_CH592/StdPeriphDriver/CH59x_spi0.c new file mode 100644 index 0000000..42672ef --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_spi0.c @@ -0,0 +1,370 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_SPI0.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn SPI0_MasterDefInit + * + * @brief 主机模式默认初始化：模式0+3线全双工+8MHz + * + * @param none + * + * @return none + */ +void SPI0_MasterDefInit(void) +{ + R8_SPI0_CLOCK_DIV = 4; // 主频时钟4分频 + R8_SPI0_CTRL_MOD = RB_SPI_ALL_CLEAR; + R8_SPI0_CTRL_MOD = RB_SPI_MOSI_OE | RB_SPI_SCK_OE; + R8_SPI0_CTRL_CFG |= RB_SPI_AUTO_IF; // 访问BUFFER/FIFO自动清除IF_BYTE_END标志 + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; // 不启动DMA方式 +} + +/********************************************************************* + * @fn SPI0_CLKCfg + * + * @brief SPI0 基准时钟配置，= d*Tsys + * + * @param c - 时钟分频系数 + * + * @return none + */ +void SPI0_CLKCfg(uint8_t c) +{ + if(c == 2) + { + R8_SPI0_CTRL_CFG |= RB_SPI_MST_DLY_EN; + } + else + { + R8_SPI0_CTRL_CFG &= ~RB_SPI_MST_DLY_EN; + } + R8_SPI0_CLOCK_DIV = c; +} + +/********************************************************************* + * @fn SPI0_DataMode + * + * @brief 设置数据流模式 + * + * @param m - 数据流模式 refer to ModeBitOrderTypeDef + * + * @return none + */ +void SPI0_DataMode(ModeBitOrderTypeDef m) +{ + switch(m) + { + case Mode0_LowBitINFront: + R8_SPI0_CTRL_MOD &= ~RB_SPI_MST_SCK_MOD; + R8_SPI0_CTRL_CFG |= RB_SPI_BIT_ORDER; + break; + case Mode0_HighBitINFront: + R8_SPI0_CTRL_MOD &= ~RB_SPI_MST_SCK_MOD; + R8_SPI0_CTRL_CFG &= ~RB_SPI_BIT_ORDER; + break; + case Mode3_LowBitINFront: + R8_SPI0_CTRL_MOD |= RB_SPI_MST_SCK_MOD; + R8_SPI0_CTRL_CFG |= RB_SPI_BIT_ORDER; + break; + case Mode3_HighBitINFront: + R8_SPI0_CTRL_MOD |= RB_SPI_MST_SCK_MOD; + R8_SPI0_CTRL_CFG &= ~RB_SPI_BIT_ORDER; + break; + default: + break; + } +} + +/********************************************************************* + * @fn SPI0_MasterSendByte + * + * @brief 发送单字节 (buffer) + * + * @param d - 发送字节 + * + * @return none + */ +void SPI0_MasterSendByte(uint8_t d) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R8_SPI0_BUFFER = d; + while(!(R8_SPI0_INT_FLAG & RB_SPI_FREE)); +} + +/********************************************************************* + * @fn SPI0_MasterRecvByte + * + * @brief 接收单字节 (buffer) + * + * @param none + * + * @return 接收到的字节 + */ +uint8_t SPI0_MasterRecvByte(void) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R8_SPI0_BUFFER = 0xFF; // 启动传输 + while(!(R8_SPI0_INT_FLAG & RB_SPI_FREE)); + return (R8_SPI0_BUFFER); +} + +/********************************************************************* + * @fn SPI0_MasterTrans + * + * @brief 使用FIFO连续发送多字节 + * + * @param pbuf - 待发送的数据内容首地址 + * @param len - 请求发送的数据长度，最大4095 + * + * @return none + */ +void SPI0_MasterTrans(uint8_t *pbuf, uint16_t len) +{ + uint16_t sendlen; + + sendlen = len; + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; // 设置数据方向为输出 + R16_SPI0_TOTAL_CNT = sendlen; // 设置要发送的数据长度 + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; + while(sendlen) + { + if(R8_SPI0_FIFO_COUNT < SPI_FIFO_SIZE) + { + R8_SPI0_FIFO = *pbuf; + pbuf++; + sendlen--; + } + } + while(R8_SPI0_FIFO_COUNT != 0); // 等待FIFO中的数据全部发送完成 +} + +/********************************************************************* + * @fn SPI0_MasterRecv + * + * @brief 使用FIFO连续接收多字节 + * + * @param pbuf - 待接收的数据首地址 + * @param len - 待接收的数据长度，最大4095 + * + * @return none + */ +void SPI0_MasterRecv(uint8_t *pbuf, uint16_t len) +{ + uint16_t readlen; + + readlen = len; + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; // 设置数据方向为输入 + R16_SPI0_TOTAL_CNT = len; // 设置需要接收的数据长度，FIFO方向为输入长度不为0则会启动传输 */ + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; + while(readlen) + { + if(R8_SPI0_FIFO_COUNT) + { + *pbuf = R8_SPI0_FIFO; + pbuf++; + readlen--; + } + } +} + +/********************************************************************* + * @fn SPI0_MasterDMATrans + * + * @brief DMA方式连续发送数据 + * + * @param pbuf - 待发送数据起始地址,需要四字节对其 + * @param len - 待发送数据长度 + * + * @return none + */ +void SPI0_MasterDMATrans(uint8_t *pbuf, uint16_t len) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R16_SPI0_DMA_BEG = (uint32_t)pbuf; + R16_SPI0_DMA_END = (uint32_t)(pbuf + len); + R16_SPI0_TOTAL_CNT = len; + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END | RB_SPI_IF_DMA_END; + R8_SPI0_CTRL_CFG |= RB_SPI_DMA_ENABLE; + while(!(R8_SPI0_INT_FLAG & RB_SPI_IF_CNT_END)); + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; +} + +/********************************************************************* + * @fn SPI0_MasterDMARecv + * + * @brief DMA方式连续接收数据 + * + * @param pbuf - 待接收数据存放起始地址,需要四字节对其 + * @param len - 待接收数据长度 + * + * @return none + */ +void SPI0_MasterDMARecv(uint8_t *pbuf, uint16_t len) +{ + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; + R16_SPI0_DMA_BEG = (uint32_t)pbuf; + R16_SPI0_DMA_END = (uint32_t)(pbuf + len); + R16_SPI0_TOTAL_CNT = len; + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END | RB_SPI_IF_DMA_END; + R8_SPI0_CTRL_CFG |= RB_SPI_DMA_ENABLE; + while(!(R8_SPI0_INT_FLAG & RB_SPI_IF_CNT_END)); + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; +} + +/********************************************************************* + * @fn SPI0_SlaveInit + * + * @brief 设备模式默认初始化，建议设置MISO的GPIO对应为输入模式 + * + * @return none + */ +void SPI0_SlaveInit(void) +{ + R8_SPI0_CTRL_MOD = RB_SPI_ALL_CLEAR; + R8_SPI0_CTRL_MOD = RB_SPI_MISO_OE | RB_SPI_MODE_SLAVE; + R8_SPI0_CTRL_CFG |= RB_SPI_AUTO_IF; +} + +/********************************************************************* + * @fn SPI0_SlaveRecvByte + * + * @brief 从机模式，接收一字节数据 + * + * @return 接收到数据 + */ +uint8_t SPI0_SlaveRecvByte(void) +{ + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; + while(R8_SPI0_FIFO_COUNT == 0); + return R8_SPI0_FIFO; +} + +/********************************************************************* + * @fn SPI0_SlaveSendByte + * + * @brief 从机模式，发送一字节数据 + * + * @param d - 待发送数据 + * + * @return none + */ +void SPI0_SlaveSendByte(uint8_t d) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R8_SPI0_FIFO = d; + while(R8_SPI0_FIFO_COUNT != 0); // 等待发送完成 +} + +/********************************************************************* + * @fn SPI0_SlaveRecv + * + * @brief 从机模式，接收多字节数据 + * + * @param pbuf - 接收收数据存放起始地址 + * @param len - 请求接收数据长度 + * + * @return none + */ +__HIGH_CODE +void SPI0_SlaveRecv(uint8_t *pbuf, uint16_t len) +{ + uint16_t revlen; + + revlen = len; + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; + while(revlen) + { + if(R8_SPI0_FIFO_COUNT) + { + *pbuf = R8_SPI0_FIFO; + pbuf++; + revlen--; + } + } +} + +/********************************************************************* + * @fn SPI0_SlaveTrans + * + * @brief 从机模式，发送多字节数据 + * + * @param pbuf - 待发送的数据内容首地址 + * @param len - 请求发送的数据长度，最大4095 + * + * @return none + */ +__HIGH_CODE +void SPI0_SlaveTrans(uint8_t *pbuf, uint16_t len) +{ + uint16_t sendlen; + + sendlen = len; + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; // 设置数据方向为输出 + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; + while(sendlen) + { + if(R8_SPI0_FIFO_COUNT < SPI_FIFO_SIZE) + { + R8_SPI0_FIFO = *pbuf; + pbuf++; + sendlen--; + } + } + while(R8_SPI0_FIFO_COUNT != 0); // 等待FIFO中的数据全部发送完成 +} + +/********************************************************************* + * @fn SPI0_SlaveDMARecv + * + * @brief DMA方式连续接收数据 + * + * @param pbuf - 待接收数据存放起始地址,需要四字节对其 + * @param len - 待接收数据长度 + * + * @return none + */ +void SPI0_SlaveDMARecv(uint8_t *pbuf, uint16_t len) +{ + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; + R16_SPI0_DMA_BEG = (uint32_t)pbuf; + R16_SPI0_DMA_END = (uint32_t)(pbuf + len); + R16_SPI0_TOTAL_CNT = len; + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END | RB_SPI_IF_DMA_END; + R8_SPI0_CTRL_CFG |= RB_SPI_DMA_ENABLE; + while(!(R8_SPI0_INT_FLAG & RB_SPI_IF_CNT_END)); + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; +} + +/********************************************************************* + * @fn SPI0_SlaveDMATrans + * + * @brief DMA方式连续发送数据 + * + * @param pbuf - 待发送数据起始地址,需要四字节对其 + * @param len - 待发送数据长度 + * + * @return none + */ +void SPI0_SlaveDMATrans(uint8_t *pbuf, uint16_t len) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R16_SPI0_DMA_BEG = (uint32_t)pbuf; + R16_SPI0_DMA_END = (uint32_t)(pbuf + len); + R16_SPI0_TOTAL_CNT = len; + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END | RB_SPI_IF_DMA_END; + R8_SPI0_CTRL_CFG |= RB_SPI_DMA_ENABLE; + while(!(R8_SPI0_INT_FLAG & RB_SPI_IF_CNT_END)); + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_sys.c b/nametag8_CH592/StdPeriphDriver/CH59x_sys.c new file mode 100644 index 0000000..9f72958 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_sys.c @@ -0,0 +1,367 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_SYS.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn SetSysClock + * + * @brief 配置系统运行时钟 + * + * @param sc - 系统时钟源选择 refer to SYS_CLKTypeDef + * + * @return none + */ +__HIGH_CODE +void SetSysClock(SYS_CLKTypeDef sc) +{ + sys_safe_access_enable(); + R8_PLL_CONFIG &= ~(1 << 5); // + sys_safe_access_disable(); + if(sc & 0x20) // HSE div + { + sys_safe_access_enable(); + R32_CLK_SYS_CFG = (0 << 6) | (sc & 0x1f) | RB_TX_32M_PWR_EN | RB_PLL_PWR_EN; + __nop(); + __nop(); + __nop(); + __nop(); + sys_safe_access_disable(); + sys_safe_access_enable(); + SAFEOPERATE; + R8_FLASH_CFG = 0X51; + sys_safe_access_disable(); + } + + else if(sc & 0x40) // PLL div + { + sys_safe_access_enable(); + R32_CLK_SYS_CFG = (1 << 6) | (sc & 0x1f) | RB_TX_32M_PWR_EN | RB_PLL_PWR_EN; + __nop(); + __nop(); + __nop(); + __nop(); + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_FLASH_CFG = 0X52; + sys_safe_access_disable(); + } + else + { + sys_safe_access_enable(); + R32_CLK_SYS_CFG |= RB_CLK_SYS_MOD; + sys_safe_access_disable(); + } + //更改FLASH clk的驱动能力 + sys_safe_access_enable(); + R8_PLL_CONFIG |= 1 << 7; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn GetSysClock + * + * @brief 获取当前系统时钟 + * + * @param none + * + * @return Hz + */ +uint32_t GetSysClock(void) +{ + uint16_t rev; + + rev = R32_CLK_SYS_CFG & 0xff; + if((rev & 0x40) == (0 << 6)) + { // 32M进行分频 + return (32000000 / (rev & 0x1f)); + } + else if((rev & RB_CLK_SYS_MOD) == (1 << 6)) + { // PLL进行分频 + return (480000000 / (rev & 0x1f)); + } + else + { // 32K做主频 + return (32000); + } +} + +/********************************************************************* + * @fn SYS_GetInfoSta + * + * @brief 获取当前系统信息状态 + * + * @param i - refer to SYS_InfoStaTypeDef + * + * @return 是否开启 + */ +uint8_t SYS_GetInfoSta(SYS_InfoStaTypeDef i) +{ + if(i == STA_SAFEACC_ACT) + { + return (R8_SAFE_ACCESS_SIG & RB_SAFE_ACC_ACT); + } + else + { + return (R8_GLOB_CFG_INFO & (1 << i)); + } +} + +/********************************************************************* + * @fn SYS_ResetExecute + * + * @brief 执行系统软件复位 + * + * @param none + * + * @return none + */ +__HIGH_CODE +void SYS_ResetExecute(void) +{ + FLASH_ROM_SW_RESET(); + sys_safe_access_enable(); + R8_RST_WDOG_CTRL |= RB_SOFTWARE_RESET; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn SYS_DisableAllIrq + * + * @brief 关闭所有中断，并保留当前中断值 + * + * @param pirqv - 当前保留中断值 + * + * @return none + */ +void SYS_DisableAllIrq(uint32_t *pirqv) +{ + *pirqv = (PFIC->ISR[0] >> 8) | (PFIC->ISR[1] << 24); + PFIC->IRER[0] = 0xffffffff; + PFIC->IRER[1] = 0xffffffff; +} + +/********************************************************************* + * @fn SYS_RecoverIrq + * + * @brief 恢复之前关闭的中断值 + * + * @param irq_status - 当前保留中断值 + * + * @return none + */ +void SYS_RecoverIrq(uint32_t irq_status) +{ + PFIC->IENR[0] = (irq_status << 8); + PFIC->IENR[1] = (irq_status >> 24); +} + +/********************************************************************* + * @fn SYS_GetSysTickCnt + * + * @brief 获取当前系统(SYSTICK)计数值 + * + * @param none + * + * @return 当前计数值 + */ +uint32_t SYS_GetSysTickCnt(void) +{ + uint32_t val; + + val = SysTick->CNT; + return (val); +} + +/********************************************************************* + * @fn WWDG_ITCfg + * + * @brief 看门狗定时器溢出中断使能 + * + * @param s - 溢出是否中断 + * + * @return none + */ +void WWDG_ITCfg(FunctionalState s) +{ + uint8_t ctrl = R8_RST_WDOG_CTRL; + + if(s == DISABLE) + { + ctrl &= ~RB_WDOG_INT_EN; + } + else + { + ctrl |= RB_WDOG_INT_EN; + } + + sys_safe_access_enable(); + R8_RST_WDOG_CTRL = ctrl; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn WWDG_ResetCfg + * + * @brief 看门狗定时器复位功能 + * + * @param s - 溢出是否复位 + * + * @return none + */ +void WWDG_ResetCfg(FunctionalState s) +{ + uint8_t ctrl = R8_RST_WDOG_CTRL; + + if(s == DISABLE) + { + ctrl &= ~RB_WDOG_RST_EN; + } + else + { + ctrl |= RB_WDOG_RST_EN; + } + + sys_safe_access_enable(); + R8_RST_WDOG_CTRL = ctrl; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief 清除看门狗中断标志，重新加载计数值也可清除 + * + * @param none + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + sys_safe_access_enable(); + R8_RST_WDOG_CTRL |= RB_WDOG_INT_FLAG; + sys_safe_access_disable(); +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief 硬件错误中断，进入后执行复位，复位类型为上电复位 + * + * @param none + * + * @return none + */ +__INTERRUPT +__HIGH_CODE +__attribute__((weak)) +void HardFault_Handler(void) +{ + FLASH_ROM_SW_RESET(); + sys_safe_access_enable(); + R16_INT32K_TUNE = 0xFFFF; + sys_safe_access_disable(); + sys_safe_access_enable(); + R8_RST_WDOG_CTRL |= RB_SOFTWARE_RESET; + sys_safe_access_disable(); + while(1); +} + +/********************************************************************* + * @fn mDelayuS + * + * @brief uS 延时 + * + * @param t - 时间参数 + * + * @return none + */ +__HIGH_CODE +void mDelayuS(uint16_t t) +{ + uint32_t i; +#if(FREQ_SYS == 80000000) + i = t * 20; +#elif(FREQ_SYS == 60000000) + i = t * 15; +#elif(FREQ_SYS == 48000000) + i = t * 12; +#elif(FREQ_SYS == 40000000) + i = t * 10; +#elif(FREQ_SYS == 32000000) + i = t << 3; +#elif(FREQ_SYS == 24000000) + i = t * 6; +#elif(FREQ_SYS == 16000000) + i = t << 2; +#elif(FREQ_SYS == 8000000) + i = t << 1; +#elif(FREQ_SYS == 4000000) + i = t; +#elif(FREQ_SYS == 2000000) + i = t >> 1; +#elif(FREQ_SYS == 1000000) + i = t >> 2; +#else + i = t << 1; +#endif + do + { + __nop(); + } while(--i); +} + +/********************************************************************* + * @fn mDelaymS + * + * @brief mS 延时 + * + * @param t - 时间参数 + * + * @return none + */ +__HIGH_CODE +void mDelaymS(uint16_t t) +{ + uint16_t i; + + for(i = 0; i < t; i++) + { + mDelayuS(1000); + } +} + +#ifdef DEBUG +int _write(int fd, char *buf, int size) +{ + int i; + for(i = 0; i < size; i++) + { +#if DEBUG == Debug_UART0 + while(R8_UART0_TFC == UART_FIFO_SIZE); /* 等待数据发送 */ + R8_UART0_THR = *buf++; /* 发送数据 */ +#elif DEBUG == Debug_UART1 + while(R8_UART1_TFC == UART_FIFO_SIZE); /* 等待数据发送 */ + R8_UART1_THR = *buf++; /* 发送数据 */ +#elif DEBUG == Debug_UART2 + while(R8_UART2_TFC == UART_FIFO_SIZE); /* 等待数据发送 */ + R8_UART2_THR = *buf++; /* 发送数据 */ +#elif DEBUG == Debug_UART3 + while(R8_UART3_TFC == UART_FIFO_SIZE); /* 等待数据发送 */ + R8_UART3_THR = *buf++; /* 发送数据 */ +#endif + } + return size; +} + +#endif + diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_timer0.c b/nametag8_CH592/StdPeriphDriver/CH59x_timer0.c new file mode 100644 index 0000000..1e2971b --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_timer0.c @@ -0,0 +1,75 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_timer0.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn TMR0_TimerInit + * + * @brief 定时功能初始化 + * + * @param t - 定时时间，基于当前系统时钟Tsys, 最长定时周期 67108864 + * + * @return none + */ +void TMR0_TimerInit(uint32_t t) +{ + R32_TMR0_CNT_END = t; + R8_TMR0_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR0_CTRL_MOD = RB_TMR_COUNT_EN; +} + +/********************************************************************* + * @fn TMR0_EXTSingleCounterInit + * + * @brief 边沿计数功能初始化 + * + * @param cap - 采集计数类型 + * + * @return none + */ +void TMR0_EXTSingleCounterInit(CapModeTypeDef cap) +{ + R8_TMR0_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR0_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_CAP_COUNT | RB_TMR_MODE_IN | (cap << 6); +} + +/********************************************************************* + * @fn TMR0_PWMInit + * + * @brief PWM 输出初始化 + * + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param ts - set pwm repeat times, refer to PWM_RepeatTsTypeDef + * + * @return none + */ +void TMR0_PWMInit(PWMX_PolarTypeDef pr, PWM_RepeatTsTypeDef ts) +{ + R8_TMR0_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR0_CTRL_MOD = (pr << 4) | (ts << 6); +} + +/********************************************************************* + * @fn TMR0_CapInit + * + * @brief 外部信号捕捉功能初始化 + * + * @param cap - select capture mode, refer to CapModeTypeDef + * + * @return none + */ +void TMR0_CapInit(CapModeTypeDef cap) +{ + R8_TMR0_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR0_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_MODE_IN | (cap << 6); +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_timer1.c b/nametag8_CH592/StdPeriphDriver/CH59x_timer1.c new file mode 100644 index 0000000..40ddacf --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_timer1.c @@ -0,0 +1,104 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_timer1.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn TMR1_TimerInit + * + * @brief 定时功能初始化 + * + * @param t - 定时时间，基于当前系统时钟Tsys, 最长定时周期 67108864 + * + * @return none + */ +void TMR1_TimerInit(uint32_t t) +{ + R32_TMR1_CNT_END = t; + R8_TMR1_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR1_CTRL_MOD = RB_TMR_COUNT_EN; +} + +/********************************************************************* + * @fn TMR1_EXTSingleCounterInit + * + * @brief 边沿计数功能初始化 + * + * @param cap - 采集计数类型 + * + * @return none + */ +void TMR1_EXTSingleCounterInit(CapModeTypeDef cap) +{ + R8_TMR1_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR1_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_CAP_COUNT | RB_TMR_MODE_IN | (cap << 6); +} + +/********************************************************************* + * @fn TMR1_PWMInit + * + * @brief PWM 输出初始化 + * + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param ts - set pwm repeat times, refer to PWM_RepeatTsTypeDef + * + * @return none + */ +void TMR1_PWMInit(PWMX_PolarTypeDef pr, PWM_RepeatTsTypeDef ts) +{ + R8_TMR1_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR1_CTRL_MOD = (pr << 4) | (ts << 6); +} + +/********************************************************************* + * @fn TMR1_CapInit + * + * @brief 外部信号捕捉功能初始化 + * + * @param cap - select capture mode, refer to CapModeTypeDef + * + * @return none + */ +void TMR1_CapInit(CapModeTypeDef cap) +{ + R8_TMR1_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR1_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_MODE_IN | (cap << 6); +} + +/********************************************************************* + * @fn TMR1_DMACfg + * + * @brief 配置DMA功能 + * + * @param s - 是否打开DMA功能 + * @param startAddr - DMA 起始地址 + * @param endAddr - DMA 结束地址 + * @param m - 配置DMA模式 + * + * @return none + */ +void TMR1_DMACfg(uint8_t s, uint16_t startAddr, uint16_t endAddr, DMAModeTypeDef m) +{ + if(s == DISABLE) + { + R8_TMR1_CTRL_DMA = 0; + } + else + { + R16_TMR1_DMA_BEG = startAddr; + R16_TMR1_DMA_END = endAddr; + if(m) + R8_TMR1_CTRL_DMA = RB_TMR_DMA_LOOP | RB_TMR_DMA_ENABLE; + else + R8_TMR1_CTRL_DMA = RB_TMR_DMA_ENABLE; + } +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_timer2.c b/nametag8_CH592/StdPeriphDriver/CH59x_timer2.c new file mode 100644 index 0000000..7bfd7f3 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_timer2.c @@ -0,0 +1,104 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_timer2.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn TMR2_TimerInit + * + * @brief 定时功能初始化 + * + * @param t - 定时时间，基于当前系统时钟Tsys, 最长定时周期 67108864 + * + * @return none + */ +void TMR2_TimerInit(uint32_t t) +{ + R32_TMR2_CNT_END = t; + R8_TMR2_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR2_CTRL_MOD = RB_TMR_COUNT_EN; +} + +/********************************************************************* + * @fn TMR2_EXTSingleCounterInit + * + * @brief 边沿计数功能初始化 + * + * @param cap - 采集计数类型 + * + * @return none + */ +void TMR2_EXTSingleCounterInit(CapModeTypeDef cap) +{ + R8_TMR2_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR2_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_CAP_COUNT | RB_TMR_MODE_IN | (cap << 6); +} + +/********************************************************************* + * @fn TMR2_PWMInit + * + * @brief PWM 输出初始化 + * + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param ts - set pwm repeat times, refer to PWM_RepeatTsTypeDef + * + * @return none + */ +void TMR2_PWMInit(PWMX_PolarTypeDef pr, PWM_RepeatTsTypeDef ts) +{ + R8_TMR2_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR2_CTRL_MOD = (pr << 4) | (ts << 6); +} + +/********************************************************************* + * @fn TMR2_CapInit + * + * @brief 外部信号捕捉功能初始化 + * + * @param cap - select capture mode, refer to CapModeTypeDef + * + * @return none + */ +void TMR2_CapInit(CapModeTypeDef cap) +{ + R8_TMR2_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR2_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_MODE_IN | (cap << 6); +} + +/********************************************************************* + * @fn TMR2_DMACfg + * + * @brief 配置DMA功能 + * + * @param s - 是否打开DMA功能 + * @param startAddr - DMA 起始地址 + * @param endAddr - DMA 结束地址 + * @param m - 配置DMA模式 + * + * @return none + */ +void TMR2_DMACfg(uint8_t s, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef m) +{ + if(s == DISABLE) + { + R8_TMR2_CTRL_DMA = 0; + } + else + { + R16_TMR2_DMA_BEG = startAddr&0xFFFF; + R16_TMR2_DMA_END = endAddr&0xFFFF; + if(m) + R8_TMR2_CTRL_DMA = RB_TMR_DMA_LOOP | RB_TMR_DMA_ENABLE; + else + R8_TMR2_CTRL_DMA = RB_TMR_DMA_ENABLE; + } +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_timer3.c b/nametag8_CH592/StdPeriphDriver/CH59x_timer3.c new file mode 100644 index 0000000..43e2334 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_timer3.c @@ -0,0 +1,75 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_timer3.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn TMR3_TimerInit + * + * @brief 定时功能初始化 + * + * @param t - 定时时间，基于当前系统时钟Tsys, 最长定时周期 67108864 + * + * @return none + */ +void TMR3_TimerInit(uint32_t t) +{ + R32_TMR3_CNT_END = t; + R8_TMR3_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR3_CTRL_MOD = RB_TMR_COUNT_EN; +} + +/********************************************************************* + * @fn TMR3_EXTSingleCounterInit + * + * @brief 边沿计数功能初始化 + * + * @param cap - 采集计数类型 + * + * @return none + */ +void TMR3_EXTSingleCounterInit(CapModeTypeDef cap) +{ + R8_TMR3_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR3_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_CAP_COUNT | RB_TMR_MODE_IN | (cap << 6); +} + +/********************************************************************* + * @fn TMR3_PWMInit + * + * @brief PWM 输出初始化 + * + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param ts - set pwm repeat times, refer to PWM_RepeatTsTypeDef + * + * @return none + */ +void TMR3_PWMInit(PWMX_PolarTypeDef pr, PWM_RepeatTsTypeDef ts) +{ + R8_TMR3_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR3_CTRL_MOD = (pr << 4) | (ts << 6); +} + +/********************************************************************* + * @fn TMR3_CapInit + * + * @brief 外部信号捕捉功能初始化 + * + * @param cap - select capture mode, refer to CapModeTypeDef + * + * @return none + */ +void TMR3_CapInit(CapModeTypeDef cap) +{ + R8_TMR3_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR3_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_MODE_IN | (cap << 6); +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_uart0.c b/nametag8_CH592/StdPeriphDriver/CH59x_uart0.c new file mode 100644 index 0000000..72610ce --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_uart0.c @@ -0,0 +1,151 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_uart0.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn UART0_DefInit + * + * @brief 串口默认初始化配置 + * + * @param none + * + * @return none + */ +void UART0_DefInit(void) +{ + UART0_BaudRateCfg(115200); + R8_UART0_FCR = (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO打开，触发点4字节 + R8_UART0_LCR = RB_LCR_WORD_SZ; + R8_UART0_IER = RB_IER_TXD_EN; + R8_UART0_DIV = 1; +} + +/********************************************************************* + * @fn UART0_BaudRateCfg + * + * @brief 串口波特率配置 + * + * @param baudrate - 波特率 + * + * @return none + */ +void UART0_BaudRateCfg(uint32_t baudrate) +{ + uint32_t x; + + x = 10 * GetSysClock() / 8 / baudrate; + x = (x + 5) / 10; + R16_UART0_DL = (uint16_t)x; +} + +/********************************************************************* + * @fn UART0_ByteTrigCfg + * + * @brief 串口字节触发中断配置 + * + * @param b - 触发字节数 refer to UARTByteTRIGTypeDef + * + * @return none + */ +void UART0_ByteTrigCfg(UARTByteTRIGTypeDef b) +{ + R8_UART0_FCR = (R8_UART0_FCR & ~RB_FCR_FIFO_TRIG) | (b << 6); +} + +/********************************************************************* + * @fn UART0_INTCfg + * + * @brief 串口中断配置 + * + * @param s - 中断控制状态，是否使能相应中断 + * @param i - 中断类型 + * RB_IER_MODEM_CHG - 调制解调器输入状态变化中断使能位（仅 UART0 支持） + * RB_IER_LINE_STAT - 接收线路状态中断 + * RB_IER_THR_EMPTY - 发送保持寄存器空中断 + * RB_IER_RECV_RDY - 接收数据中断 + * + * @return none + */ +void UART0_INTCfg(FunctionalState s, uint8_t i) +{ + if(s) + { + R8_UART0_IER |= i; + R8_UART0_MCR |= RB_MCR_INT_OE; + } + else + { + R8_UART0_IER &= ~i; + } +} + +/********************************************************************* + * @fn UART0_Reset + * + * @brief 串口软件复位 + * + * @param none + * + * @return none + */ +void UART0_Reset(void) +{ + R8_UART0_IER = RB_IER_RESET; +} + +/********************************************************************* + * @fn UART0_SendString + * + * @brief 串口多字节发送 + * + * @param buf - 待发送的数据内容首地址 + * @param l - 待发送的数据长度 + * + * @return none + */ +void UART0_SendString(uint8_t *buf, uint16_t l) +{ + uint16_t len = l; + + while(len) + { + if(R8_UART0_TFC != UART_FIFO_SIZE) + { + R8_UART0_THR = *buf++; + len--; + } + } +} + +/********************************************************************* + * @fn UART0_RecvString + * + * @brief 串口读取多字节 + * + * @param buf - 读取数据存放缓存区首地址 + * + * @return 读取数据长度 + */ +uint16_t UART0_RecvString(uint8_t *buf) +{ + uint16_t len = 0; + + while(R8_UART0_RFC) + { + *buf++ = R8_UART0_RBR; + len++; + } + + return (len); +} + diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_uart1.c b/nametag8_CH592/StdPeriphDriver/CH59x_uart1.c new file mode 100644 index 0000000..3580a8b --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_uart1.c @@ -0,0 +1,150 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_uart1.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn UART1_DefInit + * + * @brief 串口默认初始化配置 + * + * @param none + * + * @return none + */ +void UART1_DefInit(void) +{ + UART1_BaudRateCfg(115200); + R8_UART1_FCR = (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO打开，触发点4字节 + R8_UART1_LCR = RB_LCR_WORD_SZ; + R8_UART1_IER = RB_IER_TXD_EN; + R8_UART1_DIV = 1; +} + +/********************************************************************* + * @fn UART1_BaudRateCfg + * + * @brief 串口波特率配置 + * + * @param baudrate - 波特率 + * + * @return none + */ +void UART1_BaudRateCfg(uint32_t baudrate) +{ + uint32_t x; + + x = 10 * GetSysClock() / 8 / baudrate; + x = (x + 5) / 10; + R16_UART1_DL = (uint16_t)x; +} + +/********************************************************************* + * @fn UART1_ByteTrigCfg + * + * @brief 串口字节触发中断配置 + * + * @param b - 触发字节数 refer to UARTByteTRIGTypeDef + * + * @return none + */ +void UART1_ByteTrigCfg(UARTByteTRIGTypeDef b) +{ + R8_UART1_FCR = (R8_UART1_FCR & ~RB_FCR_FIFO_TRIG) | (b << 6); +} + +/********************************************************************* + * @fn UART1_INTCfg + * + * @brief 串口中断配置 + * + * @param s - 中断控制状态，是否使能相应中断 + * @param i - 中断类型 + * RB_IER_MODEM_CHG - 调制解调器输入状态变化中断使能位（仅 UART0 支持） + * RB_IER_LINE_STAT - 接收线路状态中断 + * RB_IER_THR_EMPTY - 发送保持寄存器空中断 + * RB_IER_RECV_RDY - 接收数据中断 + * + * @return none + */ +void UART1_INTCfg(FunctionalState s, uint8_t i) +{ + if(s) + { + R8_UART1_IER |= i; + R8_UART1_MCR |= RB_MCR_INT_OE; + } + else + { + R8_UART1_IER &= ~i; + } +} + +/********************************************************************* + * @fn UART1_Reset + * + * @brief 串口软件复位 + * + * @param none + * + * @return none + */ +void UART1_Reset(void) +{ + R8_UART1_IER = RB_IER_RESET; +} + +/********************************************************************* + * @fn UART1_SendString + * + * @brief 串口多字节发送 + * + * @param buf - 待发送的数据内容首地址 + * @param l - 待发送的数据长度 + * + * @return none + */ +void UART1_SendString(uint8_t *buf, uint16_t l) +{ + uint16_t len = l; + + while(len) + { + if(R8_UART1_TFC != UART_FIFO_SIZE) + { + R8_UART1_THR = *buf++; + len--; + } + } +} + +/********************************************************************* + * @fn UART1_RecvString + * + * @brief 串口读取多字节 + * + * @param buf - 读取数据存放缓存区首地址 + * + * @return 读取数据长度 + */ +uint16_t UART1_RecvString(uint8_t *buf) +{ + uint16_t len = 0; + + while(R8_UART1_RFC) + { + *buf++ = R8_UART1_RBR; + len++; + } + + return (len); +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_uart2.c b/nametag8_CH592/StdPeriphDriver/CH59x_uart2.c new file mode 100644 index 0000000..4935b30 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_uart2.c @@ -0,0 +1,151 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_uart2.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn UART2_DefInit + * + * @brief 串口默认初始化配置 + * + * @param none + * + * @return none + */ +void UART2_DefInit(void) +{ + UART2_BaudRateCfg(115200); + R8_UART2_FCR = (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO打开，触发点4字节 + R8_UART2_LCR = RB_LCR_WORD_SZ; + R8_UART2_IER = RB_IER_TXD_EN; + R8_UART2_DIV = 1; +} + +/********************************************************************* + * @fn UART2_BaudRateCfg + * + * @brief 串口波特率配置 + * + * @param baudrate - 波特率 + * + * @return none + */ +void UART2_BaudRateCfg(uint32_t baudrate) +{ + uint32_t x; + + x = 10 * GetSysClock() / 8 / baudrate; + x = (x + 5) / 10; + R16_UART2_DL = (uint16_t)x; +} + +/********************************************************************* + * @fn UART2_ByteTrigCfg + * + * @brief 串口字节触发中断配置 + * + * @param b - 触发字节数 refer to UARTByteTRIGTypeDef + * + * @return none + */ +void UART2_ByteTrigCfg(UARTByteTRIGTypeDef b) +{ + R8_UART2_FCR = (R8_UART2_FCR & ~RB_FCR_FIFO_TRIG) | (b << 6); +} + +/********************************************************************* + * @fn UART2_INTCfg + * + * @brief 串口中断配置 + * + * @param s - 中断控制状态，是否使能相应中断 + * @param i - 中断类型 + * RB_IER_MODEM_CHG - 调制解调器输入状态变化中断使能位（仅 UART0 支持） + * RB_IER_LINE_STAT - 接收线路状态中断 + * RB_IER_THR_EMPTY - 发送保持寄存器空中断 + * RB_IER_RECV_RDY - 接收数据中断 + * + * @return none + */ +void UART2_INTCfg(FunctionalState s, uint8_t i) +{ + if(s) + { + R8_UART2_IER |= i; + R8_UART2_MCR |= RB_MCR_INT_OE; + } + else + { + R8_UART2_IER &= ~i; + } +} + +/********************************************************************* + * @fn UART2_Reset + * + * @brief 串口软件复位 + * + * @param none + * + * @return none + */ +void UART2_Reset(void) +{ + R8_UART2_IER = RB_IER_RESET; +} + +/********************************************************************* + * @fn UART2_SendString + * + * @brief 串口多字节发送 + * + * @param buf - 待发送的数据内容首地址 + * @param l - 待发送的数据长度 + * + * @return none + */ +void UART2_SendString(uint8_t *buf, uint16_t l) +{ + uint16_t len = l; + + while(len) + { + if(R8_UART2_TFC != UART_FIFO_SIZE) + { + R8_UART2_THR = *buf++; + len--; + } + } +} + +/********************************************************************* + * @fn UART2_RecvString + * + * @brief 串口读取多字节 + * + * @param buf - 读取数据存放缓存区首地址 + * + * @return 读取数据长度 + */ +uint16_t UART2_RecvString(uint8_t *buf) +{ + uint16_t len = 0; + + while(R8_UART2_RFC) + { + *buf++ = R8_UART2_RBR; + len++; + } + + return (len); +} + diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_uart3.c b/nametag8_CH592/StdPeriphDriver/CH59x_uart3.c new file mode 100644 index 0000000..56acd8e --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_uart3.c @@ -0,0 +1,151 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_uart3.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +/********************************************************************* + * @fn UART3_DefInit + * + * @brief 串口默认初始化配置 + * + * @param none + * + * @return none + */ +void UART3_DefInit(void) +{ + UART3_BaudRateCfg(115200); + R8_UART3_FCR = (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO打开，触发点4字节 + R8_UART3_LCR = RB_LCR_WORD_SZ; + R8_UART3_IER = RB_IER_TXD_EN; + R8_UART3_DIV = 1; +} + +/********************************************************************* + * @fn UART3_BaudRateCfg + * + * @brief 串口波特率配置 + * + * @param baudrate - 波特率 + * + * @return none + */ +void UART3_BaudRateCfg(uint32_t baudrate) +{ + uint32_t x; + + x = 10 * GetSysClock() / 8 / baudrate; + x = (x + 5) / 10; + R16_UART3_DL = (uint16_t)x; +} + +/********************************************************************* + * @fn UART3_ByteTrigCfg + * + * @brief 串口字节触发中断配置 + * + * @param b - 触发字节数 refer to UARTByteTRIGTypeDef + * + * @return none + */ +void UART3_ByteTrigCfg(UARTByteTRIGTypeDef b) +{ + R8_UART3_FCR = (R8_UART3_FCR & ~RB_FCR_FIFO_TRIG) | (b << 6); +} + +/********************************************************************* + * @fn UART3_INTCfg + * + * @brief 串口中断配置 + * + * @param s - 中断控制状态，是否使能相应中断 + * @param i - 中断类型 + * RB_IER_MODEM_CHG - 调制解调器输入状态变化中断使能位（仅 UART0 支持） + * RB_IER_LINE_STAT - 接收线路状态中断 + * RB_IER_THR_EMPTY - 发送保持寄存器空中断 + * RB_IER_RECV_RDY - 接收数据中断 + * + * @return none + */ +void UART3_INTCfg(FunctionalState s, uint8_t i) +{ + if(s) + { + R8_UART3_IER |= i; + R8_UART3_MCR |= RB_MCR_INT_OE; + } + else + { + R8_UART3_IER &= ~i; + } +} + +/********************************************************************* + * @fn UART3_Reset + * + * @brief 串口软件复位 + * + * @param none + * + * @return none + */ +void UART3_Reset(void) +{ + R8_UART3_IER = RB_IER_RESET; +} + +/********************************************************************* + * @fn UART3_SendString + * + * @brief 串口多字节发送 + * + * @param buf - 待发送的数据内容首地址 + * @param l - 待发送的数据长度 + * + * @return none + */ +void UART3_SendString(uint8_t *buf, uint16_t l) +{ + uint16_t len = l; + + while(len) + { + if(R8_UART3_TFC != UART_FIFO_SIZE) + { + R8_UART3_THR = *buf++; + len--; + } + } +} + +/********************************************************************* + * @fn UART3_RecvString + * + * @brief 串口读取多字节 + * + * @param buf - 读取数据存放缓存区首地址 + * + * @return 读取数据长度 + */ +uint16_t UART3_RecvString(uint8_t *buf) +{ + uint16_t len = 0; + + while(R8_UART3_RFC) + { + *buf++ = R8_UART3_RBR; + len++; + } + + return (len); +} + diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_usbdev.c b/nametag8_CH592/StdPeriphDriver/CH59x_usbdev.c new file mode 100644 index 0000000..b11ad4e --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_usbdev.c @@ -0,0 +1,113 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_usbdev.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +uint8_t *pEP0_RAM_Addr; +uint8_t *pEP1_RAM_Addr; +uint8_t *pEP2_RAM_Addr; +uint8_t *pEP3_RAM_Addr; + +/********************************************************************* + * @fn USB_DeviceInit + * + * @brief USB设备功能初始化，4个端点，8个通道。 + * + * @param none + * + * @return none + */ +void USB_DeviceInit(void) +{ + R8_USB_CTRL = 0x00; // 先设定模式,取消 RB_UC_CLR_ALL + + R8_UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN; // 端点4 OUT+IN,端点1 OUT+IN + R8_UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN; // 端点2 OUT+IN,端点3 OUT+IN + + R16_UEP0_DMA = (uint16_t)(uint32_t)pEP0_RAM_Addr; + R16_UEP1_DMA = (uint16_t)(uint32_t)pEP1_RAM_Addr; + R16_UEP2_DMA = (uint16_t)(uint32_t)pEP2_RAM_Addr; + R16_UEP3_DMA = (uint16_t)(uint32_t)pEP3_RAM_Addr; + + R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + R8_UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + R8_UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + R8_UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG; + R8_UEP4_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + + R8_USB_DEV_AD = 0x00; + R8_USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN; // 启动USB设备及DMA，在中断期间中断标志未清除前自动返回NAK + R16_PIN_ANALOG_IE |= RB_PIN_USB_IE | RB_PIN_USB_DP_PU; // 防止USB端口浮空及上拉电阻 + R8_USB_INT_FG = 0xFF; // 清中断标志 + R8_UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN; // 允许USB端口 + R8_USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER; +} + +/********************************************************************* + * @fn DevEP1_IN_Deal + * + * @brief 端点1数据上传 + * + * @param l - 上传数据长度(<64B) + * + * @return none + */ +void DevEP1_IN_Deal(uint8_t l) +{ + R8_UEP1_T_LEN = l; + R8_UEP1_CTRL = (R8_UEP1_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP2_IN_Deal + * + * @brief 端点2数据上传 + * + * @param l - 上传数据长度(<64B) + * + * @return none + */ +void DevEP2_IN_Deal(uint8_t l) +{ + R8_UEP2_T_LEN = l; + R8_UEP2_CTRL = (R8_UEP2_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP3_IN_Deal + * + * @brief 端点3数据上传 + * + * @param l - 上传数据长度(<64B) + * + * @return none + */ +void DevEP3_IN_Deal(uint8_t l) +{ + R8_UEP3_T_LEN = l; + R8_UEP3_CTRL = (R8_UEP3_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} + +/********************************************************************* + * @fn DevEP4_IN_Deal + * + * @brief 端点4数据上传 + * + * @param l - 上传数据长度(<64B) + * + * @return none + */ +void DevEP4_IN_Deal(uint8_t l) +{ + R8_UEP4_T_LEN = l; + R8_UEP4_CTRL = (R8_UEP4_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK; +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_usbhostBase.c b/nametag8_CH592/StdPeriphDriver/CH59x_usbhostBase.c new file mode 100644 index 0000000..e4a7e1a --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_usbhostBase.c @@ -0,0 +1,695 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_usbhost.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" +#if DISK_LIB_ENABLE + #include "CHRV3UFI.H" +#endif + +uint8_t UsbDevEndp0Size; // USB设备的端点0的最大包尺寸 +uint8_t FoundNewDev; +_RootHubDev ThisUsbDev; //ROOT口 +_DevOnHubPort DevOnHubPort[HUB_MAX_PORTS]; // 假定:不超过1个外部HUB,每个外部HUB不超过HUB_MAX_PORTS个端口(多了不管) + +uint8_t *pHOST_RX_RAM_Addr; +uint8_t *pHOST_TX_RAM_Addr; + +/*获取设备描述符*/ +__attribute__((aligned(4))) const uint8_t SetupGetDevDescr[] = {USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, + USB_DESCR_TYP_DEVICE, 0x00, 0x00, sizeof(USB_DEV_DESCR), 0x00}; +/*获取配置描述符*/ +__attribute__((aligned(4))) const uint8_t SetupGetCfgDescr[] = {USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, + USB_DESCR_TYP_CONFIG, 0x00, 0x00, 0x04, 0x00}; +/*设置USB地址*/ +__attribute__((aligned(4))) const uint8_t SetupSetUsbAddr[] = {USB_REQ_TYP_OUT, USB_SET_ADDRESS, USB_DEVICE_ADDR, 0x00, + 0x00, 0x00, 0x00, 0x00}; +/*设置USB配置*/ +__attribute__((aligned(4))) const uint8_t SetupSetUsbConfig[] = {USB_REQ_TYP_OUT, USB_SET_CONFIGURATION, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00}; +/*设置USB接口配置*/ +__attribute__((aligned(4))) const uint8_t SetupSetUsbInterface[] = {USB_REQ_RECIP_INTERF, USB_SET_INTERFACE, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00}; +/*清除端点STALL*/ +__attribute__((aligned(4))) const uint8_t SetupClrEndpStall[] = {USB_REQ_TYP_OUT | USB_REQ_RECIP_ENDP, USB_CLEAR_FEATURE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +/********************************************************************* + * @fn DisableRootHubPort + * + * @brief 关闭ROOT-HUB端口,实际上硬件已经自动关闭,此处只是清除一些结构状态 + * + * @param none + * + * @return none + */ +void DisableRootHubPort(void) +{ +#ifdef FOR_ROOT_UDISK_ONLY + CHRV3DiskStatus = DISK_DISCONNECT; +#endif +#ifndef DISK_BASE_BUF_LEN + ThisUsbDev.DeviceStatus = ROOT_DEV_DISCONNECT; + ThisUsbDev.DeviceAddress = 0x00; +#endif +} + +/********************************************************************* + * @fn AnalyzeRootHub + * + * @brief 分析ROOT-HUB状态,处理ROOT-HUB端口的设备插拔事件 + * 如果设备拔出,函数中调用DisableRootHubPort()函数,将端口关闭,插入事件,置相应端口的状态位 + * + * @param none + * + * @return 返回ERR_SUCCESS为没有情况,返回ERR_USB_CONNECT为检测到新连接,返回ERR_USB_DISCON为检测到断开 + */ +uint8_t AnalyzeRootHub(void) +{ + uint8_t s; + + s = ERR_SUCCESS; + + if(R8_USB_MIS_ST & RB_UMS_DEV_ATTACH) + { // 设备存在 +#ifdef DISK_BASE_BUF_LEN + if(CHRV3DiskStatus == DISK_DISCONNECT +#else + if(ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT // 检测到有设备插入 +#endif + || (R8_UHOST_CTRL & RB_UH_PORT_EN) == 0x00) + { // 检测到有设备插入,但尚未允许,说明是刚插入 + DisableRootHubPort(); // 关闭端口 +#ifdef DISK_BASE_BUF_LEN + CHRV3DiskStatus = DISK_CONNECT; +#else + ThisUsbDev.DeviceSpeed = R8_USB_MIS_ST & RB_UMS_DM_LEVEL ? 0 : 1; + ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED; //置连接标志 +#endif + PRINT("USB dev in\n"); + s = ERR_USB_CONNECT; + } + } + +#ifdef DISK_BASE_BUF_LEN + else if(CHRV3DiskStatus >= DISK_CONNECT) + { +#else + else if(ThisUsbDev.DeviceStatus >= ROOT_DEV_CONNECTED) + { //检测到设备拔出 +#endif + DisableRootHubPort(); // 关闭端口 + PRINT("USB dev out\n"); + if(s == ERR_SUCCESS) + { + s = ERR_USB_DISCON; + } + } + // R8_USB_INT_FG = RB_UIF_DETECT; // 清中断标志 + return (s); +} + +/********************************************************************* + * @fn SetHostUsbAddr + * + * @brief 设置USB主机当前操作的USB设备地址 + * + * @param addr - USB设备地址 + * + * @return none + */ +void SetHostUsbAddr(uint8_t addr) +{ + R8_USB_DEV_AD = (R8_USB_DEV_AD & RB_UDA_GP_BIT) | (addr & MASK_USB_ADDR); +} + +/********************************************************************* + * @fn SetUsbSpeed + * + * @brief 设置当前USB速度 + * + * @param FullSpeed - USB速度 + * + * @return none + */ +void SetUsbSpeed(uint8_t FullSpeed) +{ +#ifndef DISK_BASE_BUF_LEN + if(FullSpeed) // 全速 + { + R8_USB_CTRL &= ~RB_UC_LOW_SPEED; // 全速 + R8_UH_SETUP &= ~RB_UH_PRE_PID_EN; // 禁止PRE PID + } + else + { + R8_USB_CTRL |= RB_UC_LOW_SPEED; // 低速 + } +#endif + (void)FullSpeed; +} + +/********************************************************************* + * @fn ResetRootHubPort + * + * @brief 检测到设备后,复位总线,为枚举设备准备,设置为默认为全速 + * + * @param none + * + * @return none + */ +void ResetRootHubPort(void) +{ + UsbDevEndp0Size = DEFAULT_ENDP0_SIZE; //USB设备的端点0的最大包尺寸 + SetHostUsbAddr(0x00); + R8_UHOST_CTRL &= ~RB_UH_PORT_EN; // 关掉端口 + SetUsbSpeed(1); // 默认为全速 + R8_UHOST_CTRL = (R8_UHOST_CTRL & ~RB_UH_LOW_SPEED) | RB_UH_BUS_RESET; // 默认为全速,开始复位 + mDelaymS(15); // 复位时间10mS到20mS + R8_UHOST_CTRL = R8_UHOST_CTRL & ~RB_UH_BUS_RESET; // 结束复位 + mDelayuS(250); + R8_USB_INT_FG = RB_UIF_DETECT; // 清中断标志 +} + +/********************************************************************* + * @fn EnableRootHubPort + * + * @brief 使能ROOT-HUB端口,相应的bUH_PORT_EN置1开启端口,设备断开可能导致返回失败 + * + * @param none + * + * @return 返回ERR_SUCCESS为检测到新连接,返回ERR_USB_DISCON为无连接 + */ +uint8_t EnableRootHubPort(void) +{ +#ifdef DISK_BASE_BUF_LEN + if(CHRV3DiskStatus < DISK_CONNECT) + CHRV3DiskStatus = DISK_CONNECT; +#else + if(ThisUsbDev.DeviceStatus < ROOT_DEV_CONNECTED) + ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED; +#endif + if(R8_USB_MIS_ST & RB_UMS_DEV_ATTACH) + { // 有设备 +#ifndef DISK_BASE_BUF_LEN + if((R8_UHOST_CTRL & RB_UH_PORT_EN) == 0x00) + { // 尚未使能 + ThisUsbDev.DeviceSpeed = (R8_USB_MIS_ST & RB_UMS_DM_LEVEL) ? 0 : 1; + if(ThisUsbDev.DeviceSpeed == 0) + { + R8_UHOST_CTRL |= RB_UH_LOW_SPEED; // 低速 + } + } +#endif + R8_UHOST_CTRL |= RB_UH_PORT_EN; //使能HUB端口 + return (ERR_SUCCESS); + } + return (ERR_USB_DISCON); +} + +#ifndef DISK_BASE_BUF_LEN +/********************************************************************* + * @fn SelectHubPort + * + * @brief 选定需要操作的HUB口 + * + * @param HubPortIndex - 选择操作指定的ROOT-HUB端口的外部HUB的指定端口 + * + * @return None + */ +void SelectHubPort(uint8_t HubPortIndex) +{ + if(HubPortIndex) // 选择操作指定的ROOT-HUB端口的外部HUB的指定端口 + { + SetHostUsbAddr(DevOnHubPort[HubPortIndex - 1].DeviceAddress); // 设置USB主机当前操作的USB设备地址 + SetUsbSpeed(DevOnHubPort[HubPortIndex - 1].DeviceSpeed); // 设置当前USB速度 + if(DevOnHubPort[HubPortIndex - 1].DeviceSpeed == 0) // 通过外部HUB与低速USB设备通讯需要前置ID + { + R8_UEP1_CTRL |= RB_UH_PRE_PID_EN; // 启用PRE PID + mDelayuS(100); + } + } + else + { + SetHostUsbAddr(ThisUsbDev.DeviceAddress); // 设置USB主机当前操作的USB设备地址 + SetUsbSpeed(ThisUsbDev.DeviceSpeed); // 设置USB设备的速度 + } +} +#endif + +/********************************************************************* + * @fn WaitUSB_Interrupt + * + * @brief 等待USB中断 + * + * @param none + * + * @return 返回ERR_SUCCESS 数据接收或者发送成功,返回ERR_USB_UNKNOWN 数据接收或者发送失败 + */ +uint8_t WaitUSB_Interrupt(void) +{ + uint16_t i; + for(i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG & RB_UIF_TRANSFER) == 0; i--) + { + ; + } + return ((R8_USB_INT_FG & RB_UIF_TRANSFER) ? ERR_SUCCESS : ERR_USB_UNKNOWN); +} + +/********************************************************************* + * @fn USBHostTransact + * + * @brief 传输事务,输入目的端点地址/PID令牌,同步标志,以20uS为单位的NAK重试总时间(0则不重试,0xFFFF无限重试),返回0成功,超时/出错重试 + * 本子程序着重于易理解,而在实际应用中,为了提供运行速度,应该对本子程序代码进行优化 + * + * @param endp_pid - 令牌和地址, 高4位是token_pid令牌, 低4位是端点地址 + * @param tog - 同步标志 + * @param timeout - 超时时间 + * + * @return ERR_USB_UNKNOWN 超时，可能硬件异常 + * ERR_USB_DISCON 设备断开 + * ERR_USB_CONNECT 设备连接 + * ERR_SUCCESS 传输完成 + */ +uint8_t USBHostTransact(uint8_t endp_pid, uint8_t tog, uint32_t timeout) +{ + uint8_t TransRetry; + + uint8_t s, r; + uint16_t i; + + R8_UH_RX_CTRL = R8_UH_TX_CTRL = tog; + TransRetry = 0; + + do + { + R8_UH_EP_PID = endp_pid; // 指定令牌PID和目的端点号 + R8_USB_INT_FG = RB_UIF_TRANSFER; + for(i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG & RB_UIF_TRANSFER) == 0; i--) + { + ; + } + R8_UH_EP_PID = 0x00; // 停止USB传输 + if((R8_USB_INT_FG & RB_UIF_TRANSFER) == 0) + { + return (ERR_USB_UNKNOWN); + } + + if(R8_USB_INT_FG & RB_UIF_DETECT) + { // USB设备插拔事件 + // mDelayuS( 200 ); // 等待传输完成 + R8_USB_INT_FG = RB_UIF_DETECT; + s = AnalyzeRootHub(); // 分析ROOT-HUB状态 + + if(s == ERR_USB_CONNECT) + FoundNewDev = 1; +#ifdef DISK_BASE_BUF_LEN + if(CHRV3DiskStatus == DISK_DISCONNECT) + { + return (ERR_USB_DISCON); + } // USB设备断开事件 + if(CHRV3DiskStatus == DISK_CONNECT) + { + return (ERR_USB_CONNECT); + } // USB设备连接事件 +#else + if(ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT) + { + return (ERR_USB_DISCON); + } // USB设备断开事件 + if(ThisUsbDev.DeviceStatus == ROOT_DEV_CONNECTED) + { + return (ERR_USB_CONNECT); + } // USB设备连接事件 +#endif + mDelayuS(200); // 等待传输完成 + } + + if(R8_USB_INT_FG & RB_UIF_TRANSFER) // 传输完成事件 + { + if(R8_USB_INT_ST & RB_UIS_TOG_OK) + { + return (ERR_SUCCESS); + } + r = R8_USB_INT_ST & MASK_UIS_H_RES; // USB设备应答状态 + if(r == USB_PID_STALL) + { + return (r | ERR_USB_TRANSFER); + } + if(r == USB_PID_NAK) + { + if(timeout == 0) + { + return (r | ERR_USB_TRANSFER); + } + if(timeout < 0xFFFFFFFF) + { + timeout--; + } + --TransRetry; + } + else + switch(endp_pid >> 4) + { + case USB_PID_SETUP: + case USB_PID_OUT: + if(r) + { + return (r | ERR_USB_TRANSFER); + } // 不是超时/出错,意外应答 + break; // 超时重试 + case USB_PID_IN: + if(r == USB_PID_DATA0 || r == USB_PID_DATA1) + { // 不同步则需丢弃后重试 + } // 不同步重试 + else if(r) + { + return (r | ERR_USB_TRANSFER); + } // 不是超时/出错,意外应答 + break; // 超时重试 + default: + return (ERR_USB_UNKNOWN); // 不可能的情况 + break; + } + } + else + { // 其它中断,不应该发生的情况 + R8_USB_INT_FG = 0xFF; /* 清中断标志 */ + } + mDelayuS(15); + } while(++TransRetry < 3); + return (ERR_USB_TRANSFER); // 应答超时 +} + +/********************************************************************* + * @fn HostCtrlTransfer + * + * @brief 执行控制传输,8字节请求码在pSetupReq中,DataBuf为可选的收发缓冲区 + * + * @param DataBuf - 如果需要接收和发送数据,那么DataBuf需指向有效缓冲区用于存放后续数据 + * @param RetLen - 实际成功收发的总长度保存在RetLen指向的字节变量中 + * + * @return ERR_USB_BUF_OVER IN状态阶段出错 + * ERR_SUCCESS 数据交换成功 + */ +uint8_t HostCtrlTransfer(uint8_t *DataBuf, uint8_t *RetLen) +{ + uint16_t RemLen = 0; + uint8_t s, RxLen, RxCnt, TxCnt; + uint8_t *pBuf; + uint8_t *pLen; + + pBuf = DataBuf; + pLen = RetLen; + mDelayuS(200); + if(pLen) + { + *pLen = 0; // 实际成功收发的总长度 + } + + R8_UH_TX_LEN = sizeof(USB_SETUP_REQ); + s = USBHostTransact(USB_PID_SETUP << 4 | 0x00, 0x00, 200000 / 20); // SETUP阶段,200mS超时 + if(s != ERR_SUCCESS) + { + return (s); + } + R8_UH_RX_CTRL = R8_UH_TX_CTRL = RB_UH_R_TOG | RB_UH_R_AUTO_TOG | RB_UH_T_TOG | RB_UH_T_AUTO_TOG; // 默认DATA1 + R8_UH_TX_LEN = 0x01; // 默认无数据故状态阶段为IN + RemLen = pSetupReq->wLength; + PRINT("wLength: %x\n", RemLen); + if(RemLen && pBuf) // 需要收发数据 + { + PRINT("bRequestType: %x\n", pSetupReq->bRequestType); + if(pSetupReq->bRequestType & USB_REQ_TYP_IN) // 收 + { + while(RemLen) + { + mDelayuS(200); + s = USBHostTransact(USB_PID_IN << 4 | 0x00, R8_UH_RX_CTRL, 200000 / 20); // IN数据 + if(s != ERR_SUCCESS) + { + return (s); + } + RxLen = R8_USB_RX_LEN < RemLen ? R8_USB_RX_LEN : RemLen; + RemLen -= RxLen; + if(pLen) + { + *pLen += RxLen; // 实际成功收发的总长度 + } + for(RxCnt = 0; RxCnt != RxLen; RxCnt++) + { + *pBuf = pHOST_RX_RAM_Addr[RxCnt]; + pBuf++; + } + if(R8_USB_RX_LEN == 0 || (R8_USB_RX_LEN & (UsbDevEndp0Size - 1))) + { + break; // 短包 + } + } + R8_UH_TX_LEN = 0x00; // 状态阶段为OUT + } + else // 发 + { + while(RemLen) + { + mDelayuS(200); + R8_UH_TX_LEN = RemLen >= UsbDevEndp0Size ? UsbDevEndp0Size : RemLen; + for(TxCnt = 0; TxCnt != R8_UH_TX_LEN; TxCnt++) + { + pHOST_TX_RAM_Addr[TxCnt] = *pBuf; + pBuf++; + } + s = USBHostTransact(USB_PID_OUT << 4 | 0x00, R8_UH_TX_CTRL, 200000 / 20); // OUT数据 + if(s != ERR_SUCCESS) + { + return (s); + } + RemLen -= R8_UH_TX_LEN; + if(pLen) + { + *pLen += R8_UH_TX_LEN; // 实际成功收发的总长度 + } + } + PRINT("Send: %d\n", *pLen); + // R8_UH_TX_LEN = 0x01; // 状态阶段为IN + } + } + mDelayuS(200); + s = USBHostTransact((R8_UH_TX_LEN ? USB_PID_IN << 4 | 0x00 : USB_PID_OUT << 4 | 0x00), RB_UH_R_TOG | RB_UH_T_TOG, 200000 / 20); // STATUS阶段 + if(s != ERR_SUCCESS) + { + return (s); + } + if(R8_UH_TX_LEN == 0) + { + return (ERR_SUCCESS); // 状态OUT + } + if(R8_USB_RX_LEN == 0) + { + return (ERR_SUCCESS); // 状态IN,检查IN状态返回数据长度 + } + return (ERR_USB_BUF_OVER); // IN状态阶段错误 +} + +/********************************************************************* + * @fn CopySetupReqPkg + * + * @brief 复制控制传输的请求包 + * + * @param pReqPkt - 控制请求包地址 + * + * @return none + */ +void CopySetupReqPkg(const uint8_t *pReqPkt) // 复制控制传输的请求包 +{ + uint8_t i; + for(i = 0; i != sizeof(USB_SETUP_REQ); i++) + { + ((uint8_t *)pSetupReq)[i] = *pReqPkt; + pReqPkt++; + } +} + +/********************************************************************* + * @fn CtrlGetDeviceDescr + * + * @brief 获取设备描述符,返回在 pHOST_TX_RAM_Addr 中 + * + * @param none + * + * @return ERR_USB_BUF_OVER 描述符长度错误 + * ERR_SUCCESS 成功 + */ +uint8_t CtrlGetDeviceDescr(void) +{ + uint8_t s; + uint8_t len; + + UsbDevEndp0Size = DEFAULT_ENDP0_SIZE; + CopySetupReqPkg(SetupGetDevDescr); + s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + UsbDevEndp0Size = ((PUSB_DEV_DESCR)Com_Buffer)->bMaxPacketSize0; // 端点0最大包长度,这是简化处理,正常应该先获取前8字节后立即更新UsbDevEndp0Size再继续 + if(len < ((PUSB_SETUP_REQ)SetupGetDevDescr)->wLength) + { + return (ERR_USB_BUF_OVER); // 描述符长度错误 + } + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn CtrlGetConfigDescr + * + * @brief 获取配置描述符,返回在 pHOST_TX_RAM_Addr 中 + * + * @param none + * + * @return ERR_USB_BUF_OVER 描述符长度错误 + * ERR_SUCCESS 成功 + */ +uint8_t CtrlGetConfigDescr(void) +{ + uint8_t s; + uint8_t len; + + CopySetupReqPkg(SetupGetCfgDescr); + s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + if(len < ((PUSB_SETUP_REQ)SetupGetCfgDescr)->wLength) + { + return (ERR_USB_BUF_OVER); // 返回长度错误 + } + + len = ((PUSB_CFG_DESCR)Com_Buffer)->wTotalLength; + CopySetupReqPkg(SetupGetCfgDescr); + pSetupReq->wLength = len; // 完整配置描述符的总长度 + s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + +#ifdef DISK_BASE_BUF_LEN + if(len > 64) + len = 64; + memcpy(TxBuffer, Com_Buffer, len); //U盘操作时，需要拷贝到TxBuffer +#endif + + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn CtrlSetUsbAddress + * + * @brief 设置USB设备地址 + * + * @param addr - 设备地址 + * + * @return ERR_SUCCESS 成功 + */ +uint8_t CtrlSetUsbAddress(uint8_t addr) +{ + uint8_t s; + + CopySetupReqPkg(SetupSetUsbAddr); + pSetupReq->wValue = addr; // USB设备地址 + s = HostCtrlTransfer(NULL, NULL); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + SetHostUsbAddr(addr); // 设置USB主机当前操作的USB设备地址 + mDelaymS(10); // 等待USB设备完成操作 + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn CtrlSetUsbConfig + * + * @brief 设置USB设备配置 + * + * @param cfg - 配置值 + * + * @return ERR_SUCCESS 成功 + */ +uint8_t CtrlSetUsbConfig(uint8_t cfg) +{ + CopySetupReqPkg(SetupSetUsbConfig); + pSetupReq->wValue = cfg; // USB设备配置 + return (HostCtrlTransfer(NULL, NULL)); // 执行控制传输 +} + +/********************************************************************* + * @fn CtrlClearEndpStall + * + * @brief 清除端点STALL + * + * @param endp - 端点地址 + * + * @return ERR_SUCCESS 成功 + */ +uint8_t CtrlClearEndpStall(uint8_t endp) +{ + CopySetupReqPkg(SetupClrEndpStall); // 清除端点的错误 + pSetupReq->wIndex = endp; // 端点地址 + return (HostCtrlTransfer(NULL, NULL)); // 执行控制传输 +} + +/********************************************************************* + * @fn CtrlSetUsbIntercace + * + * @brief 设置USB设备接口 + * + * @param cfg - 配置值 + * + * @return ERR_SUCCESS 成功 + */ +uint8_t CtrlSetUsbIntercace(uint8_t cfg) +{ + CopySetupReqPkg(SetupSetUsbInterface); + pSetupReq->wValue = cfg; // USB设备配置 + return (HostCtrlTransfer(NULL, NULL)); // 执行控制传输 +} + +/********************************************************************* + * @fn USB_HostInit + * + * @brief USB主机功能初始化 + * + * @param none + * + * @return none + */ +void USB_HostInit(void) +{ + R8_USB_CTRL = RB_UC_HOST_MODE; + R8_UHOST_CTRL = 0; + R8_USB_DEV_AD = 0x00; + + R8_UH_EP_MOD = RB_UH_EP_TX_EN | RB_UH_EP_RX_EN; + R16_UH_RX_DMA = (uint16_t)(uint32_t)pHOST_RX_RAM_Addr; + R16_UH_TX_DMA = (uint16_t)(uint32_t)pHOST_TX_RAM_Addr; + + R8_UH_RX_CTRL = 0x00; + R8_UH_TX_CTRL = 0x00; + R8_USB_CTRL = RB_UC_HOST_MODE | RB_UC_INT_BUSY | RB_UC_DMA_EN; + R8_UH_SETUP = RB_UH_SOF_EN; + R8_USB_INT_FG = 0xFF; + DisableRootHubPort(); + R8_USB_INT_EN = RB_UIE_TRANSFER | RB_UIE_DETECT; + + FoundNewDev = 0; +} diff --git a/nametag8_CH592/StdPeriphDriver/CH59x_usbhostClass.c b/nametag8_CH592/StdPeriphDriver/CH59x_usbhostClass.c new file mode 100644 index 0000000..9589b88 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/CH59x_usbhostClass.c @@ -0,0 +1,840 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_usbhost.c + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" +#if DISK_LIB_ENABLE + #include "CHRV3UFI.H" +#endif + +/* 设置HID上传速率 */ +__attribute__((aligned(4))) const uint8_t SetupSetHIDIdle[] = {0x21, HID_SET_IDLE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; +/* 获取HID设备报表描述符 */ +__attribute__((aligned(4))) const uint8_t SetupGetHIDDevReport[] = {0x81, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_REPORT, + 0x00, 0x00, 0x41, 0x00}; +/* 获取HUB描述符 */ +__attribute__((aligned(4))) const uint8_t SetupGetHubDescr[] = {HUB_GET_HUB_DESCRIPTOR, HUB_GET_DESCRIPTOR, 0x00, + USB_DESCR_TYP_HUB, 0x00, 0x00, sizeof(USB_HUB_DESCR), 0x00}; + +__attribute__((aligned(4))) uint8_t Com_Buffer[128]; // 定义用户临时缓冲区,枚举时用于处理描述符,枚举结束也可以用作普通临时缓冲区 + +/********************************************************************* + * @fn AnalyzeHidIntEndp + * + * @brief 从描述符中分析出HID中断端点的地址,如果HubPortIndex是0保存到ROOTHUB，如果是非零值则保存到HUB下结构体 + * + * @param buf - 待分析数据缓冲区地址 HubPortIndex：0表示根HUB，非0表示外部HUB下的端口号 + * + * @return 端点数 + */ +uint8_t AnalyzeHidIntEndp(uint8_t *buf, uint8_t HubPortIndex) +{ + uint8_t i, s, l; + s = 0; + + if(HubPortIndex) + { + memset(DevOnHubPort[HubPortIndex - 1].GpVar, 0, sizeof(DevOnHubPort[HubPortIndex - 1].GpVar)); //清空数组 + } + else + { + memset(ThisUsbDev.GpVar, 0, sizeof(ThisUsbDev.GpVar)); //清空数组 + } + + for(i = 0; i < ((PUSB_CFG_DESCR)buf)->wTotalLength; i += l) // 搜索中断端点描述符,跳过配置描述符和接口描述符 + { + if(((PUSB_ENDP_DESCR)(buf + i))->bDescriptorType == USB_DESCR_TYP_ENDP // 是端点描述符 + && (((PUSB_ENDP_DESCR)(buf + i))->bmAttributes & USB_ENDP_TYPE_MASK) == USB_ENDP_TYPE_INTER // 是中断端点 + && (((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_DIR_MASK)) // 是IN端点 + { // 保存中断端点的地址,位7用于同步标志位,清0 + if(HubPortIndex) + { + DevOnHubPort[HubPortIndex - 1].GpVar[s] = ((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_ADDR_MASK; + } + else + { + ThisUsbDev.GpVar[s] = ((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_ADDR_MASK; // 中断端点的地址，可以根据需要保存wMaxPacketSize和bInterval + } + PRINT("%02x ", (uint16_t)ThisUsbDev.GpVar[s]); + s++; + if(s >= 4) + { + break; //只分析4个端点 + } + } + l = ((PUSB_ENDP_DESCR)(buf + i))->bLength; // 当前描述符长度,跳过 + if(l > 16) + { + break; + } + } + PRINT("\n"); + return (s); +} + +/********************************************************************* + * @fn AnalyzeBulkEndp + * + * @brief 分析出批量端点,GpVar[0]、GpVar[1]存放上传端点。GpVar[2]、GpVar[3]存放下传端点 + * + * @param buf - 待分析数据缓冲区地址 HubPortIndex：0表示根HUB，非0表示外部HUB下的端口号 + * + * @return 0 + */ +uint8_t AnalyzeBulkEndp(uint8_t *buf, uint8_t HubPortIndex) +{ + uint8_t i, s1, s2, l; + s1 = 0; + s2 = 2; + + if(HubPortIndex) + { + memset(DevOnHubPort[HubPortIndex - 1].GpVar, 0, sizeof(DevOnHubPort[HubPortIndex - 1].GpVar)); //清空数组 + } + else + { + memset(ThisUsbDev.GpVar, 0, sizeof(ThisUsbDev.GpVar)); //清空数组 + } + + for(i = 0; i < ((PUSB_CFG_DESCR)buf)->wTotalLength; i += l) // 搜索中断端点描述符,跳过配置描述符和接口描述符 + { + if((((PUSB_ENDP_DESCR)(buf + i))->bDescriptorType == USB_DESCR_TYP_ENDP) // 是端点描述符 + && ((((PUSB_ENDP_DESCR)(buf + i))->bmAttributes & USB_ENDP_TYPE_MASK) == USB_ENDP_TYPE_BULK)) // 是中断端点 + + { + if(HubPortIndex) + { + if(((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_DIR_MASK) + { + DevOnHubPort[HubPortIndex - 1].GpVar[s1++] = ((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_ADDR_MASK; + } + else + { + DevOnHubPort[HubPortIndex - 1].GpVar[s2++] = ((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_ADDR_MASK; + } + } + else + { + if(((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_DIR_MASK) + { + ThisUsbDev.GpVar[s1++] = ((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_ADDR_MASK; + } + else + { + ThisUsbDev.GpVar[s2++] = ((PUSB_ENDP_DESCR)(buf + i))->bEndpointAddress & USB_ENDP_ADDR_MASK; + } + } + + if(s1 == 2) + { + s1 = 1; + } + if(s2 == 4) + { + s2 = 3; + } + } + l = ((PUSB_ENDP_DESCR)(buf + i))->bLength; // 当前描述符长度,跳过 + if(l > 16) + { + break; + } + } + return (0); +} + +/********************************************************************* + * @fn InitRootDevice + * + * @brief 初始化指定ROOT-HUB端口的USB设备 + * + * @param none + * + * @return 错误码 + */ +uint8_t InitRootDevice(void) +{ + uint8_t i, s; + uint8_t cfg, dv_cls, if_cls; + + PRINT("Reset host port\n"); + ResetRootHubPort(); // 检测到设备后,复位相应端口的USB总线 + for(i = 0, s = 0; i < 100; i++) + { // 等待USB设备复位后重新连接,100mS超时 + mDelaymS(1); + if(EnableRootHubPort() == ERR_SUCCESS) + { // 使能端口 + i = 0; + s++; + if(s > 100) + { + break; // 已经稳定连接100mS + } + } + } + if(i) + { // 复位后设备没有连接 + DisableRootHubPort(); + PRINT("Disable host port because of disconnect\n"); + return (ERR_USB_DISCON); + } + SetUsbSpeed(ThisUsbDev.DeviceSpeed); // 设置当前USB速度 + + PRINT("GetDevDescr: "); + s = CtrlGetDeviceDescr(); // 获取设备描述符 + if(s == ERR_SUCCESS) + { + for(i = 0; i < ((PUSB_SETUP_REQ)SetupGetDevDescr)->wLength; i++) + { + PRINT("x%02X ", (uint16_t)(Com_Buffer[i])); + } + PRINT("\n"); + + ThisUsbDev.DeviceVID = ((PUSB_DEV_DESCR)Com_Buffer)->idVendor; //保存VID PID信息 + ThisUsbDev.DevicePID = ((PUSB_DEV_DESCR)Com_Buffer)->idProduct; + dv_cls = ((PUSB_DEV_DESCR)Com_Buffer)->bDeviceClass; + + s = CtrlSetUsbAddress(((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue); + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceAddress = ((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue; // 保存USB地址 + + PRINT("GetCfgDescr: "); + s = CtrlGetConfigDescr(); + if(s == ERR_SUCCESS) + { + for(i = 0; i < ((PUSB_CFG_DESCR)Com_Buffer)->wTotalLength; i++) + { + PRINT("x%02X ", (uint16_t)(Com_Buffer[i])); + } + PRINT("\n"); + /* 分析配置描述符,获取端点数据/各端点地址/各端点大小等,更新变量endp_addr和endp_size等 */ + cfg = ((PUSB_CFG_DESCR)Com_Buffer)->bConfigurationValue; + if_cls = ((PUSB_CFG_DESCR_LONG)Com_Buffer)->itf_descr.bInterfaceClass; // 接口类代码 + + if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_STORAGE)) + { // 是USB存储类设备,基本上确认是U盘 +#ifdef FOR_ROOT_UDISK_ONLY + CHRV3DiskStatus = DISK_USB_ADDR; + return (ERR_SUCCESS); + } + else + { + return (ERR_USB_UNSUPPORT); + } +#else + s = CtrlSetUsbConfig(cfg); // 设置USB设备配置 + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + ThisUsbDev.DeviceType = USB_DEV_CLASS_STORAGE; + PRINT("USB-Disk Ready\n"); + SetUsbSpeed(1); // 默认为全速 + return (ERR_SUCCESS); + } + } + else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_PRINTER) && ((PUSB_CFG_DESCR_LONG)Com_Buffer)->itf_descr.bInterfaceSubClass == 0x01) + { // 是打印机类设备 + s = CtrlSetUsbConfig(cfg); // 设置USB设备配置 + if(s == ERR_SUCCESS) + { + // 需保存端点信息以便主程序进行USB传输 + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + ThisUsbDev.DeviceType = USB_DEV_CLASS_PRINTER; + PRINT("USB-Print Ready\n"); + SetUsbSpeed(1); // 默认为全速 + return (ERR_SUCCESS); + } + } + else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_HID) && ((PUSB_CFG_DESCR_LONG)Com_Buffer)->itf_descr.bInterfaceSubClass <= 0x01) + { // 是HID类设备,键盘/鼠标等 + // 从描述符中分析出HID中断端点的地址 + s = AnalyzeHidIntEndp(Com_Buffer, 0); // 从描述符中分析出HID中断端点的地址 + PRINT("AnalyzeHidIntEndp %02x\n", (uint16_t)s); + // 保存中断端点的地址,位7用于同步标志位,清0 + if_cls = ((PUSB_CFG_DESCR_LONG)Com_Buffer)->itf_descr.bInterfaceProtocol; + s = CtrlSetUsbConfig(cfg); // 设置USB设备配置 + if(s == ERR_SUCCESS) + { + s = CtrlGetHIDDeviceReport(dv_cls); //获取报表描述符 + if(s == ERR_SUCCESS) + { + for(i = 0; i < 64; i++) + { + PRINT("x%02X ", (uint16_t)(Com_Buffer[i])); + } + PRINT("\n"); + } + // 需保存端点信息以便主程序进行USB传输 + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + if(if_cls == 1) + { + ThisUsbDev.DeviceType = DEV_TYPE_KEYBOARD; + // 进一步初始化,例如设备键盘指示灯LED等 + PRINT("USB-Keyboard Ready\n"); + SetUsbSpeed(1); // 默认为全速 + return (ERR_SUCCESS); + } + else if(if_cls == 2) + { + ThisUsbDev.DeviceType = DEV_TYPE_MOUSE; + // 为了以后查询鼠标状态,应该分析描述符,取得中断端口的地址,长度等信息 + PRINT("USB-Mouse Ready\n"); + SetUsbSpeed(1); // 默认为全速 + return (ERR_SUCCESS); + } + s = ERR_USB_UNSUPPORT; + } + } + else if(dv_cls == USB_DEV_CLASS_HUB) + { // 是HUB类设备,集线器等 + s = CtrlGetHubDescr(); + if(s == ERR_SUCCESS) + { + PRINT("Max Port:%02X ", (((PXUSB_HUB_DESCR)Com_Buffer)->bNbrPorts)); + ThisUsbDev.GpHUBPortNum = ((PXUSB_HUB_DESCR)Com_Buffer)->bNbrPorts; // 保存HUB的端口数量 + if(ThisUsbDev.GpHUBPortNum > HUB_MAX_PORTS) + { + ThisUsbDev.GpHUBPortNum = HUB_MAX_PORTS; // 因为定义结构DevOnHubPort时人为假定每个HUB不超过HUB_MAX_PORTS个端口 + } + s = CtrlSetUsbConfig(cfg); // 设置USB设备配置 + if(s == ERR_SUCCESS) + { + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + ThisUsbDev.DeviceType = USB_DEV_CLASS_HUB; + //需保存端点信息以便主程序进行USB传输,本来中断端点可用于HUB事件通知,但本程序使用查询状态控制传输代替 + //给HUB各端口上电,查询各端口状态,初始化有设备连接的HUB端口,初始化设备 + for(i = 1; i <= ThisUsbDev.GpHUBPortNum; i++) // 给HUB各端口都上电 + { + DevOnHubPort[i - 1].DeviceStatus = ROOT_DEV_DISCONNECT; // 清外部HUB端口上设备的状态 + s = HubSetPortFeature(i, HUB_PORT_POWER); + if(s != ERR_SUCCESS) + { + PRINT("Ext-HUB Port_%1d# power on error\n", (uint16_t)i); // 端口上电失败 + } + } + PRINT("USB-HUB Ready\n"); + SetUsbSpeed(1); // 默认为全速 + return (ERR_SUCCESS); + } + } + } + else + { // 可以进一步分析 + s = CtrlSetUsbConfig(cfg); // 设置USB设备配置 + if(s == ERR_SUCCESS) + { + // 需保存端点信息以便主程序进行USB传输 + ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS; + ThisUsbDev.DeviceType = DEV_TYPE_UNKNOW; + SetUsbSpeed(1); // 默认为全速 + return (ERR_SUCCESS); /* 未知设备初始化成功 */ + } + } +#endif + } + } + } + + PRINT("InitRootDev Err = %02X\n", (uint16_t)s); +#ifdef FOR_ROOT_UDISK_ONLY + CHRV3DiskStatus = DISK_CONNECT; +#else + ThisUsbDev.DeviceStatus = ROOT_DEV_FAILED; +#endif + SetUsbSpeed(1); // 默认为全速 + return (s); +} + +/********************************************************************* + * @fn InitDevOnHub + * + * @brief 初始化枚举外部HUB后的二级USB设备 + * + * @param HubPortIndex - 指定外部HUB + * + * @return 错误码 + */ +uint8_t InitDevOnHub(uint8_t HubPortIndex) +{ + uint8_t i, s, cfg, dv_cls, if_cls; + uint8_t ifc; + PRINT("Init dev @ExtHub-port_%1d ", (uint16_t)HubPortIndex); + if(HubPortIndex == 0) + { + return (ERR_USB_UNKNOWN); + } + SelectHubPort(HubPortIndex); // 选择操作指定的ROOT-HUB端口的外部HUB的指定端口,选择速度 + PRINT("GetDevDescr: "); + s = CtrlGetDeviceDescr(); // 获取设备描述符 + if(s != ERR_SUCCESS) + { + return (s); + } + DevOnHubPort[HubPortIndex - 1].DeviceVID = ((uint16_t)((PUSB_DEV_DESCR)Com_Buffer)->idVendor); //保存VID PID信息 + DevOnHubPort[HubPortIndex - 1].DevicePID = ((uint16_t)((PUSB_DEV_DESCR)Com_Buffer)->idProduct); + + dv_cls = ((PUSB_DEV_DESCR)Com_Buffer)->bDeviceClass; // 设备类代码 + cfg = (1 << 4) + HubPortIndex; // 计算出一个USB地址,避免地址重叠 + s = CtrlSetUsbAddress(cfg); // 设置USB设备地址 + if(s != ERR_SUCCESS) + { + return (s); + } + DevOnHubPort[HubPortIndex - 1].DeviceAddress = cfg; // 保存分配的USB地址 + PRINT("GetCfgDescr: "); + s = CtrlGetConfigDescr(); // 获取配置描述符 + if(s != ERR_SUCCESS) + { + return (s); + } + cfg = ((PUSB_CFG_DESCR)Com_Buffer)->bConfigurationValue; + for(i = 0; i < ((PUSB_CFG_DESCR)Com_Buffer)->wTotalLength; i++) + { + PRINT("x%02X ", (uint16_t)(Com_Buffer[i])); + } + PRINT("\n"); + /* 分析配置描述符,获取端点数据/各端点地址/各端点大小等,更新变量endp_addr和endp_size等 */ + if_cls = ((PXUSB_CFG_DESCR_LONG)Com_Buffer)->itf_descr.bInterfaceClass; // 接口类代码 + if(dv_cls == 0x00 && if_cls == USB_DEV_CLASS_STORAGE) // 是USB存储类设备,基本上确认是U盘 + { + AnalyzeBulkEndp(Com_Buffer, HubPortIndex); + for(i = 0; i != 4; i++) + { + PRINT("%02x ", (uint16_t)DevOnHubPort[HubPortIndex - 1].GpVar[i]); + } + PRINT("\n"); + s = CtrlSetUsbConfig(cfg); // 设置USB设备配置 + if(s == ERR_SUCCESS) + { + DevOnHubPort[HubPortIndex - 1].DeviceStatus = ROOT_DEV_SUCCESS; + DevOnHubPort[HubPortIndex - 1].DeviceType = USB_DEV_CLASS_STORAGE; + PRINT("USB-Disk Ready\n"); + SetUsbSpeed(1); // 默认为全速 + return (ERR_SUCCESS); + } + } + else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_HID) && (((PXUSB_CFG_DESCR_LONG)Com_Buffer)->itf_descr.bInterfaceSubClass <= 0x01)) // 是HID类设备,键盘/鼠标等 + { + ifc = ((PXUSB_CFG_DESCR_LONG)Com_Buffer)->cfg_descr.bNumInterfaces; + s = AnalyzeHidIntEndp(Com_Buffer, HubPortIndex); // 从描述符中分析出HID中断端点的地址 + PRINT("AnalyzeHidIntEndp %02x\n", (uint16_t)s); + if_cls = ((PXUSB_CFG_DESCR_LONG)Com_Buffer)->itf_descr.bInterfaceProtocol; + s = CtrlSetUsbConfig(cfg); // 设置USB设备配置 + if(s == ERR_SUCCESS) + { + for(dv_cls = 0; dv_cls < ifc; dv_cls++) + { + s = CtrlGetHIDDeviceReport(dv_cls); //获取报表描述符 + if(s == ERR_SUCCESS) + { + for(i = 0; i < 64; i++) + { + PRINT("x%02X ", (uint16_t)(Com_Buffer[i])); + } + PRINT("\n"); + } + } + //需保存端点信息以便主程序进行USB传输 + DevOnHubPort[HubPortIndex - 1].DeviceStatus = ROOT_DEV_SUCCESS; + if(if_cls == 1) + { + DevOnHubPort[HubPortIndex - 1].DeviceType = DEV_TYPE_KEYBOARD; + //进一步初始化,例如设备键盘指示灯LED等 + if(ifc > 1) + { + PRINT("USB_DEV_CLASS_HID Ready\n"); + DevOnHubPort[HubPortIndex - 1].DeviceType = USB_DEV_CLASS_HID; //复合HID设备 + } + PRINT("USB-Keyboard Ready\n"); + SetUsbSpeed(1); // 默认为全速 + + return (ERR_SUCCESS); + } + else if(if_cls == 2) + { + DevOnHubPort[HubPortIndex - 1].DeviceType = DEV_TYPE_MOUSE; + //为了以后查询鼠标状态,应该分析描述符,取得中断端口的地址,长度等信息 + if(ifc > 1) + { + PRINT("USB_DEV_CLASS_HID Ready\n"); + DevOnHubPort[HubPortIndex - 1].DeviceType = USB_DEV_CLASS_HID; //复合HID设备 + } + PRINT("USB-Mouse Ready\n"); + SetUsbSpeed(1); // 默认为全速 + + return (ERR_SUCCESS); + } + s = ERR_USB_UNSUPPORT; + } + } + else if(dv_cls == USB_DEV_CLASS_HUB) // 是HUB类设备,集线器等 + { + DevOnHubPort[HubPortIndex - 1].DeviceType = USB_DEV_CLASS_HUB; + PRINT("This program don't support Level 2 HUB\n"); // 需要支持多级HUB级联请参考本程序进行扩展 + s = HubClearPortFeature(i, HUB_PORT_ENABLE); // 禁止HUB端口 + if(s != ERR_SUCCESS) + { + return (s); + } + s = ERR_USB_UNSUPPORT; + } + else //其他设备 + { + AnalyzeBulkEndp(Com_Buffer, HubPortIndex); //分析出批量端点 + for(i = 0; i != 4; i++) + { + PRINT("%02x ", (uint16_t)DevOnHubPort[HubPortIndex - 1].GpVar[i]); + } + PRINT("\n"); + s = CtrlSetUsbConfig(cfg); // 设置USB设备配置 + if(s == ERR_SUCCESS) + { + //需保存端点信息以便主程序进行USB传输 + DevOnHubPort[HubPortIndex - 1].DeviceStatus = ROOT_DEV_SUCCESS; + DevOnHubPort[HubPortIndex - 1].DeviceType = dv_cls ? dv_cls : if_cls; + SetUsbSpeed(1); // 默认为全速 + return (ERR_SUCCESS); //未知设备初始化成功 + } + } + PRINT("InitDevOnHub Err = %02X\n", (uint16_t)s); + DevOnHubPort[HubPortIndex - 1].DeviceStatus = ROOT_DEV_FAILED; + SetUsbSpeed(1); // 默认为全速 + return (s); +} + +/********************************************************************* + * @fn EnumHubPort + * + * @brief 枚举指定ROOT-HUB端口上的外部HUB集线器的各个端口,检查各端口有无连接或移除事件并初始化二级USB设备 + * + * @param RootHubIndex - ROOT_HUB0和ROOT_HUB1 + * + * @return 错误码 + */ +uint8_t EnumHubPort() +{ + uint8_t i, s; + + for(i = 1; i <= ThisUsbDev.GpHUBPortNum; i++) // 查询集线器的端口是否有变化 + { + SelectHubPort(0); // 选择操作指定的ROOT-HUB端口,设置当前USB速度以及被操作设备的USB地址 + s = HubGetPortStatus(i); // 获取端口状态 + if(s != ERR_SUCCESS) + { + return (s); // 可能是该HUB断开了 + } + if(((Com_Buffer[0] & (1 << (HUB_PORT_CONNECTION & 0x07))) && (Com_Buffer[2] & (1 << (HUB_C_PORT_CONNECTION & 0x07)))) || (Com_Buffer[2] == 0x10)) + { // 发现有设备连接 + DevOnHubPort[i - 1].DeviceStatus = ROOT_DEV_CONNECTED; // 有设备连接 + DevOnHubPort[i - 1].DeviceAddress = 0x00; + s = HubGetPortStatus(i); // 获取端口状态 + if(s != ERR_SUCCESS) + { + return (s); // 可能是该HUB断开了 + } + DevOnHubPort[i - 1].DeviceSpeed = Com_Buffer[1] & (1 << (HUB_PORT_LOW_SPEED & 0x07)) ? 0 : 1; // 低速还是全速 + if(DevOnHubPort[i - 1].DeviceSpeed) + { + PRINT("Found full speed device on port %1d\n", (uint16_t)i); + } + else + { + PRINT("Found low speed device on port %1d\n", (uint16_t)i); + } + mDelaymS(200); // 等待设备上电稳定 + s = HubSetPortFeature(i, HUB_PORT_RESET); // 对有设备连接的端口复位 + if(s != ERR_SUCCESS) + { + return (s); // 可能是该HUB断开了 + } + PRINT("Reset port and then wait in\n"); + do // 查询复位端口,直到复位完成,把完成后的状态显示出来 + { + mDelaymS(1); + s = HubGetPortStatus(i); + if(s != ERR_SUCCESS) + { + return (s); // 可能是该HUB断开了 + } + } while(Com_Buffer[0] & (1 << (HUB_PORT_RESET & 0x07))); // 端口正在复位则等待 + mDelaymS(100); + s = HubClearPortFeature(i, HUB_C_PORT_RESET); // 清除复位完成标志 + // s = HubSetPortFeature( i, HUB_PORT_ENABLE ); // 启用HUB端口 + s = HubClearPortFeature(i, HUB_C_PORT_CONNECTION); // 清除连接或移除变化标志 + if(s != ERR_SUCCESS) + { + return (s); + } + s = HubGetPortStatus(i); // 再读取状态,复查设备是否还在 + if(s != ERR_SUCCESS) + { + return (s); + } + if((Com_Buffer[0] & (1 << (HUB_PORT_CONNECTION & 0x07))) == 0) + { + DevOnHubPort[i - 1].DeviceStatus = ROOT_DEV_DISCONNECT; // 设备不在了 + } + s = InitDevOnHub(i); // 初始化二级USB设备 + if(s != ERR_SUCCESS) + { + return (s); + } + SetUsbSpeed(1); // 默认为全速 + } + else if(Com_Buffer[2] & (1 << (HUB_C_PORT_ENABLE & 0x07))) // 设备连接出错 + { + HubClearPortFeature(i, HUB_C_PORT_ENABLE); // 清除连接错误标志 + PRINT("Device on port error\n"); + s = HubSetPortFeature(i, HUB_PORT_RESET); // 对有设备连接的端口复位 + if(s != ERR_SUCCESS) + return (s); // 可能是该HUB断开了 + do // 查询复位端口,直到复位完成,把完成后的状态显示出来 + { + mDelaymS(1); + s = HubGetPortStatus(i); + if(s != ERR_SUCCESS) + return (s); // 可能是该HUB断开了 + } while(Com_Buffer[0] & (1 << (HUB_PORT_RESET & 0x07))); // 端口正在复位则等待 + } + else if((Com_Buffer[0] & (1 << (HUB_PORT_CONNECTION & 0x07))) == 0) // 设备已经断开 + { + if(DevOnHubPort[i - 1].DeviceStatus >= ROOT_DEV_CONNECTED) + { + PRINT("Device on port %1d removed\n", (uint16_t)i); + } + DevOnHubPort[i - 1].DeviceStatus = ROOT_DEV_DISCONNECT; // 有设备连接 + if(Com_Buffer[2] & (1 << (HUB_C_PORT_CONNECTION & 0x07))) + { + HubClearPortFeature(i, HUB_C_PORT_CONNECTION); // 清除移除变化标志 + } + } + } + return (ERR_SUCCESS); // 返回操作成功 +} + +/********************************************************************* + * @fn EnumAllHubPort + * + * @brief 枚举所有ROOT-HUB端口下外部HUB后的二级USB设备 + * + * @return 错误码 + */ +uint8_t EnumAllHubPort(void) +{ + uint8_t s; + + if((ThisUsbDev.DeviceStatus >= ROOT_DEV_SUCCESS) && (ThisUsbDev.DeviceType == USB_DEV_CLASS_HUB)) // HUB枚举成功 + { + SelectHubPort(0); // 选择操作指定的ROOT-HUB端口,设置当前USB速度以及被操作设备的USB地址 + s = EnumHubPort(); // 枚举指定ROOT-HUB端口上的外部HUB集线器的各个端口,检查各端口有无连接或移除事件 + if(s != ERR_SUCCESS) // 可能是HUB断开了 + { + PRINT("EnumAllHubPort err = %02X\n", (uint16_t)s); + } + SetUsbSpeed(1); // 默认为全速 + } + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn SearchTypeDevice + * + * @brief 在ROOT-HUB以及外部HUB各端口上搜索指定类型的设备所在的端口号,输出端口号为0xFFFF则未搜索到. + * 当然也可以根据USB的厂商VID产品PID进行搜索(事先要记录各设备的VID和PID),以及指定搜索序号 + * + * @param type - 搜索的设备类型 + * + * @return 输出高8位为ROOT-HUB端口号,低8位为外部HUB的端口号,低8位为0则设备直接在ROOT-HUB端口上 + */ +uint16_t SearchTypeDevice(uint8_t type) +{ + uint8_t RootHubIndex; //CH554只有一个USB口,RootHubIndex = 0,只需看返回值的低八位即可 + uint8_t HubPortIndex; + + RootHubIndex = 0; + if((ThisUsbDev.DeviceType == USB_DEV_CLASS_HUB) && (ThisUsbDev.DeviceStatus >= ROOT_DEV_SUCCESS)) // 外部集线器HUB且枚举成功 + { + for(HubPortIndex = 1; HubPortIndex <= ThisUsbDev.GpHUBPortNum; HubPortIndex++) // 搜索外部HUB的各个端口 + { + if(DevOnHubPort[HubPortIndex - 1].DeviceType == type && DevOnHubPort[HubPortIndex - 1].DeviceStatus >= ROOT_DEV_SUCCESS) + { + return (((uint16_t)RootHubIndex << 8) | HubPortIndex); // 类型匹配且枚举成功 + } + } + } + if((ThisUsbDev.DeviceType == type) && (ThisUsbDev.DeviceStatus >= ROOT_DEV_SUCCESS)) + { + return ((uint16_t)RootHubIndex << 8); // 类型匹配且枚举成功,在ROOT-HUB端口上 + } + + return (0xFFFF); +} + +/********************************************************************* + * @fn SETorOFFNumLock + * + * @brief NumLock的点灯判断 + * + * @param buf - 点灯键值 + * + * @return 错误码 + */ +uint8_t SETorOFFNumLock(uint8_t *buf) +{ + uint8_t tmp[] = {0x21, 0x09, 0x00, 0x02, 0x00, 0x00, 0x01, 0x00}; + uint8_t len, s; + if((buf[2] == 0x53) & ((buf[0] | buf[1] | buf[3] | buf[4] | buf[5] | buf[6] | buf[7]) == 0)) + { + for(s = 0; s != sizeof(tmp); s++) + { + ((uint8_t *)pSetupReq)[s] = tmp[s]; + } + s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + } + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn CtrlGetHIDDeviceReport + * + * @brief 获取HID设备报表描述符,返回在TxBuffer中 + * + * @param none + * + * @return 错误码 + */ +uint8_t CtrlGetHIDDeviceReport(uint8_t infc) +{ + uint8_t s; + uint8_t len; + + CopySetupReqPkg(SetupSetHIDIdle); + pSetupReq->wIndex = infc; + s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + + CopySetupReqPkg(SetupGetHIDDevReport); + pSetupReq->wIndex = infc; + s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn CtrlGetHubDescr + * + * @brief 获取HUB描述符,返回在Com_Buffer中 + * + * @param none + * + * @return 错误码 + */ +uint8_t CtrlGetHubDescr(void) +{ + uint8_t s; + uint8_t len; + + CopySetupReqPkg(SetupGetHubDescr); + s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + if(len < ((PUSB_SETUP_REQ)SetupGetHubDescr)->wLength) + { + return (ERR_USB_BUF_OVER); // 描述符长度错误 + } + // if ( len < 4 ) return( ERR_USB_BUF_OVER ); // 描述符长度错误 + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn HubGetPortStatus + * + * @brief 查询HUB端口状态,返回在Com_Buffer中 + * + * @param HubPortIndex - 端口号 + * + * @return 错误码 + */ +uint8_t HubGetPortStatus(uint8_t HubPortIndex) +{ + uint8_t s; + uint8_t len; + + pSetupReq->bRequestType = HUB_GET_PORT_STATUS; + pSetupReq->bRequest = HUB_GET_STATUS; + pSetupReq->wValue = 0x0000; + pSetupReq->wIndex = 0x0000 | HubPortIndex; + pSetupReq->wLength = 0x0004; + s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输 + if(s != ERR_SUCCESS) + { + return (s); + } + if(len < 4) + { + return (ERR_USB_BUF_OVER); // 描述符长度错误 + } + return (ERR_SUCCESS); +} + +/********************************************************************* + * @fn HubSetPortFeature + * + * @brief 设置HUB端口特性 + * + * @param HubPortIndex - 端口号 + * @param FeatureSelt - 端口特性 + * + * @return 错误码 + */ +uint8_t HubSetPortFeature(uint8_t HubPortIndex, uint8_t FeatureSelt) +{ + pSetupReq->bRequestType = HUB_SET_PORT_FEATURE; + pSetupReq->bRequest = HUB_SET_FEATURE; + pSetupReq->wValue = 0x0000 | FeatureSelt; + pSetupReq->wIndex = 0x0000 | HubPortIndex; + pSetupReq->wLength = 0x0000; + return (HostCtrlTransfer(NULL, NULL)); // 执行控制传输 +} + +/********************************************************************* + * @fn HubClearPortFeature + * + * @brief 清除HUB端口特性 + * + * @param HubPortIndex - 端口号 + * @param FeatureSelt - 端口特性 + * + * @return 错误码 + */ +uint8_t HubClearPortFeature(uint8_t HubPortIndex, uint8_t FeatureSelt) +{ + pSetupReq->bRequestType = HUB_CLEAR_PORT_FEATURE; + pSetupReq->bRequest = HUB_CLEAR_FEATURE; + pSetupReq->wValue = 0x0000 | FeatureSelt; + pSetupReq->wIndex = 0x0000 | HubPortIndex; + pSetupReq->wLength = 0x0000; + return (HostCtrlTransfer(NULL, NULL)); // 执行控制传输 +} diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH592SFR.h b/nametag8_CH592/StdPeriphDriver/inc/CH592SFR.h new file mode 100644 index 0000000..5bc62f8 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH592SFR.h @@ -0,0 +1,1858 @@ +/* Define for CH592 */ +/* Website: http://wch.cn */ +/* Email: tech@wch.cn */ +/* Author: W.ch 2023.02 */ +/* V0.2 SpecialFunctionRegister */ + +// multi-blocks: __BASE_TYPE__, __CH592SFR_H__, __CH592USBSFR_H__, __USB_TYPE__... + +#ifndef __BASE_TYPE__ +#define __BASE_TYPE__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ********************************************************************************************************************* */ +/* Base types & constants */ + +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif +#ifndef NULL +#define NULL 0 +#endif + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT64 +typedef unsigned long long UINT64; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif +#ifndef UINT64V +typedef unsigned long long volatile UINT64V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif +#ifndef PUINT64V +typedef volatile unsigned long long *PUINT64V; +#endif + +/* ********************************************************************************************************************* */ +/* Base macros */ + +#ifndef min +#define min(a,b) (((a) < (b)) ? (a) : (b)) +#endif +#ifndef max +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifdef DEBUG +#define PRINT(X...) printf(X) +#else +#define PRINT(X...) +#endif + +/* Calculate the byte offset of a field in a structure of type */ +#define FIELD_OFFSET(Type, Field) ((UINT16)&(((Type *)0)->Field)) + +/* Calculate the size of a field in a structure of type */ +#define FIELD_SIZE(Type, Field) (sizeof(((Type *)0)->Field)) + +/* An expression that yields the type of a field in a struct */ +#define FIELD_TYPE(Type, Field) (((Type *)0)->Field) + +/* Return the number of elements in a statically sized array */ +#define NUMBER_OF(Array) (sizeof(Array)/sizeof((Array)[0])) +#define NUMBER_OF_FIELD(Type, Field) (NUMBER_OF(FIELD_TYPE(Type, Field))) + +#ifdef __cplusplus +} +#endif + +#endif // __BASE_TYPE__ + + +#ifndef __CH592SFR_H__ +#define __CH592SFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ********************************************************************************************************************* */ + +// Address Space +// CODE: 00000000H - 0007FFFFH 512K +// DATA: 20000000H - 20007FFFH 32KB +// SFR: 40000000H - 4000FFFFH 64KB +// +// SFR: 40000000H - 4000FFFFH, 64KB +// SYS: +1000H - 1BFFH, include base configuration, interrupt, GPIO, etc... +// TMR0: +2000H - 23FFH +// TMR1: +2400H - 27FFH +// TMR2: +2800H - 2BFFH +// TMR3: +2C00H - 2FFFH +// UART0: +3000H - 33FFH +// UART1: +3400H - 37FFH +// UART2: +3800H - 3BFFH +// UART3: +3C00H - 3FFFH +// SPI0: +4000H - 43FFH +// I2C: +4800H - 4BFFH +// PWMx: +5000H - 53FFH +// LCD: +6000H - 63FFH +// USB: +8000H - 83FFH +// BLE: +C000H - D3FFH + +// Register Bit Attribute / Bit Access Type +// RF: Read only for Fixed value +// RO: Read Only (internal change) +// RZ: Read only with auto clear Zero +// WO: Write Only (read zero or different) +// WA: Write only under safe Accessing mode (read zero or different) +// WZ: Write only with auto clear Zero +// RW: Read / Write +// RWA: Read / Write under safe Accessing mode +// RW1: Read / Write 1 to Clear + +/* Register name rule: + R32_* for 32 bits register (UINT32,ULONG) + R16_* for 16 bits register (UINT16,USHORT) + R8_* for 8 bits register (UINT8,UCHAR) + RB_* for bit or bit mask of 8 bit register + BA_* for base address point + b* for GPIO bit mask + Others for register address offset */ + +/* ********************************************************************************************************************* */ + +/* Independent watch-dog register */ +#define R32_IWDG_KR (*((PUINT32V)0x40001000)) // WO, watch-dog key register +#define R32_IWDG_CFG (*((PUINT32V)0x40001004)) // RW, watch-dog configuration +#define RB_RLR 0x0FFF // RW, watch-dog counter reload (write protect) +#define RB_PR 0x7000 // PR, prescale (write protect) +#define RB_PVU 0x8000 // RO, register update flag (write protect) +#define RB_COUNT 0xFF0000 // RO, watch-dog down counter +#define RB_STOP_EN 0x20000000 // RW, watch-dog stop enable (write protect) +#define RB_WR_PROTECT 0x40000000 // RO, write protect +#define RB_IWDG_EN 0x80000000 // RO, watch-dog enable + +/* System: safe accessing register */ +#define R32_SAFE_ACCESS (*((PUINT32V)0x40001040)) // RW, safe accessing +#define R8_SAFE_ACCESS_SIG (*((PUINT8V)0x40001040)) // WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode +#define RB_SAFE_ACC_MODE 0x03 // RO, current safe accessing mode: 11=safe/unlocked (SAM), other=locked (00..01..10..11) +#define RB_SAFE_ACC_ACT 0x08 // RO, indicate safe accessing status now: 0=locked, read only, 1=safe/unlocked (SAM), write enabled +#define RB_SAFE_ACC_TIMER 0x70 // RO, safe accessing timer bit mask (16*clock number) +#define SAFE_ACCESS_SIG1 0x57 // WO: safe accessing sign value step 1 +#define SAFE_ACCESS_SIG2 0xA8 // WO: safe accessing sign value step 2 +#define SAFE_ACCESS_SIG0 0x00 // WO: safe accessing sign value for disable +#define R8_CHIP_ID (*((PUINT8V)0x40001041)) // RF, chip ID register, always is ID_CH58* +#define R8_SAFE_ACCESS_ID (*((PUINT8V)0x40001042)) // RF, safe accessing ID register, always 0x0C +#define R8_WDOG_COUNT (*((PUINT8V)0x40001043)) // RW, watch-dog count, count by clock frequency Fsys/131072 + +/* System: global configuration register */ +#define R32_GLOBAL_CONFIG (*((PUINT32V)0x40001044)) // RW, global configuration +#define R8_RESET_STATUS (*((PUINT8V)0x40001044)) // RO, reset status +#define RB_RESET_FLAG 0x07 // RO: recent reset flag +#define RST_FLAG_SW 0x00 +#define RST_FLAG_RPOR 0x01 +#define RST_FLAG_WTR 0x02 +#define RST_FLAG_MR 0x03 +//#define RST_FLAG_GPWSM 0x04 // RO, power on reset flag during sleep/shutdown: 0=no power on reset during sleep/shutdown, 1=power on reset occurred during sleep/shutdown +#define RST_FLAG_GPWSM 0x05 +// RB_RESET_FLAG: recent reset flag +// 000 - SR, software reset, by RB_SOFTWARE_RESET=1 @RB_WDOG_RST_EN=0 +// 001 - RPOR, real power on reset +// 010 - WTR, watch-dog timer-out reset +// 011 - MR, external manual reset by RST pin input low +// 101 - GRWSM, global reset by waking under shutdown mode +// 1?? - LRW, power on reset occurred during sleep +#define R8_GLOB_ROM_CFG R8_RESET_STATUS // RWA, flash ROM configuration, SAM +#define RB_ROM_CODE_OFS 0x10 // RWA, code offset address selection in Flash ROM: 0=start address 0x000000, 1=start address 0x040000 +#define RB_ROM_CTRL_EN 0x20 // RWA, enable flash ROM control interface enable: 0=disable access, 1=enable access control register +#define RB_ROM_DATA_WE 0x40 // RWA, enable flash ROM data & code area being erase/write: 0=all writing protect, 1=enable data area program and erase +#define RB_ROM_CODE_WE 0x80 // RWA, enable flash ROM code area being erase/write: 0=code writing protect, 1=enable code area program and erase +#define R8_GLOB_CFG_INFO (*((PUINT8V)0x40001045)) // RO, global configuration information and status +#define RB_CFG_ROM_READ 0x01 // RO, indicate protected status of Flash ROM code and data: 0=reading protect, 1=enable read by external programmer +#define RB_CFG_RESET_EN 0x04 // RO, manual reset input enable status +#define RB_CFG_BOOT_EN 0x08 // RO, boot-loader enable status +#define RB_CFG_DEBUG_EN 0x10 // RO, debug enable status +#define RB_BOOT_LOADER 0x20 // RO, indicate boot loader status: 0=application status (by software reset), 1=boot loader status +#define R8_RST_WDOG_CTRL (*((PUINT8V)0x40001046)) // RWA, reset and watch-dog control, SAM +#define RB_SOFTWARE_RESET 0x01 // WA/WZ, global software reset, high action, auto clear +#define RB_WDOG_RST_EN 0x02 // RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow +#define RB_WDOG_INT_EN 0x04 // RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable +#define RB_WDOG_INT_FLAG 0x10 // RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event) +#define R8_GLOB_RESET_KEEP (*((PUINT8V)0x40001047)) // RW, value keeper during global reset + +/* System: clock configuration register */ +#define R32_CLOCK_CONFIG (*((PUINT32V)0x40001008)) // RWA, clock configuration, SAM +#define R32_CLK_SYS_CFG (*((PUINT32V)0x40001008)) // RWA, system clock configuration, SAM +#define RB_CLK_PLL_DIV 0x1F // RWA, output clock divider from PLL or CK32M +#define RB_CLK_SYS_MOD 0xC0 // RWA, system clock source mode: 00=divided from 32MHz, 01=divided from PLL-480MHz, 10=directly from 32MHz, 11=directly from 32KHz +#define RB_TX_32M_PWR_EN 0x40000 // RWA, extern 32MHz HSE power contorl +#define RB_XT_32M_PWR_EN 0x40000 // RWA, extern 32MHz HSE power contorl +#define RB_XT_FORCE_EN 0x80000 // RWA, system clock control in Halt mode +#define RB_PLL_PWR_EN 0x100000 // RWA, PLL power control + +// Fck32k = RB_CLK_OSC32K_XT ? XT_32KHz : RC_32KHz +// Fpll = XT_32MHz * 15 = 480MHz +// Fsys = RB_CLK_SYS_MOD==3 ? Fck32k : ( ( RB_CLK_SYS_MOD[0] ? Fpll : XT_32MHz ) / RB_CLK_PLL_DIV ) +// default: Fsys = XT_32MHz / RB_CLK_PLL_DIV = 32MHz / 5 = 6.4MHz +// range: 32KHz, 2MHz~10MHz, 15MHz~80MHz + +/* System: sleep control register */ +#define R32_SLEEP_CONTROL (*((PUINT32V)0x4000100C)) // RWA, sleep control, SAM +#define R8_SLP_CLK_OFF0 (*((PUINT8V)0x4000100C)) // RWA, sleep clock off control byte 0, SAM +#define RB_SLP_CLK_TMR0 0x01 // RWA, close TMR0 clock +#define RB_SLP_CLK_TMR1 0x02 // RWA, close TMR1 clock +#define RB_SLP_CLK_TMR2 0x04 // RWA, close TMR2 clock +#define RB_SLP_CLK_TMR3 0x08 // RWA, close TMR3 clock +#define RB_SLP_CLK_UART0 0x10 // RWA, close UART0 clock +#define RB_SLP_CLK_UART1 0x20 // RWA, close UART1 clock +#define RB_SLP_CLK_UART2 0x40 // RWA, close UART2 clock +#define RB_SLP_CLK_UART3 0x80 // RWA, close UART3 clock +#define R8_SLP_CLK_OFF1 (*((PUINT8V)0x4000100D)) // RWA, sleep clock off control byte 1, SAM +#define RB_SLP_CLK_SPI0 0x01 // RWA, close SPI0 clock +#define RB_SLP_CLK_PWMX 0x04 // RWA, close PWMx clock +#define RB_SLP_CLK_I2C 0x08 // RWA, close I2C clock +#define RB_SLP_CLK_USB 0x10 // RWA, close USB clock +#define RB_SLP_CLK_LCD 0x40 // RWA, close LCD clock +#define RB_SLP_CLK_BLE 0x80 // RWA, close BLE clock +#define R8_SLP_WAKE_CTRL (*((PUINT8V)0x4000100E)) // RWA, wake control, SAM +#define RB_SLP_USB_WAKE 0x01 // RWA, enable USB waking +//#define RB_SLP_BLE_WAKE 0x04 // RWA, enable BLE waking +#define RB_SLP_RTC_WAKE 0x08 // RWA, enable RTC waking +#define RB_SLP_GPIO_WAKE 0x10 // RWA, enable GPIO waking +#define RB_SLP_BAT_WAKE 0x20 // RWA, enable BAT waking +#define RB_WAKE_EV_MODE 0x40 // RWA, event wakeup mode: 0=event keep valid for long time, 1=short pulse event +#define RB_GPIO_WAKE_MODE 0x80 // RWA, +#define R8_SLP_POWER_CTRL (*((PUINT8V)0x4000100F)) // RWA, peripherals power down control, SAM +#define RB_WAKE_DLY_MOD 0x03 // RWA, wakeup delay time selection +// RB_WAKE_DLY_MOD select wakeup delay +// 00: long time, 3590 cycles+TSUHSE +// 01: short time, 520 cycles+TSUHSE +// 10: shorter time, 70 cycles+TSUHSE +// 11: no delay, 8 cycles+TSUHSE +//#define RB_SLP_USB_PWR_DN 0x01 // RWA, enable USB power down +//#define RB_SLP_BLE_PWR_DN 0x04 // RWA, enable BLE power down +#define RB_SLP_CLK_RAMX 0x10 // RWA, close main SRAM clock +#define RB_SLP_CLK_RAM2K 0x20 // RWA, close retention 2KB SRAM clock +#define RB_RAM_RET_LV 0x40 // RWA, SRAM retention voltage selection: 0=normal, 1=low voltage for low power +#define R32_SLEEP_CTRL2 (*((PUINT32V)0x40001010)) // RWA, touchkey wake up enable +#define RB_TKEY0_5_WAKE_EN 0x003F // RWA, touchkey wake up enable channel 0-5 +#define RB_TKEY8_13_WAKE_EN 0x3F00 // RWA, touchkey wake up enable channel 8-13 + +/* System: I/O pin configuration register */ +#define R32_PIN_CONFIG (*((PUINT32V)0x40001018)) // RW, I/O pin configuration +#define R16_PIN_ALTERNATE (*((PUINT16V)0x40001018)) // RW, function pin alternate configuration +#define RB_PIN_TMR0 0x01 // RW, TMR0 alternate pin enable: 0=TMR0/PWM0/CAP0 on PA[9], 1=TMR0_/PWM0_/CAP0_ on PB[23] +#define RB_PIN_TMR1 0x02 // RW, TMR1 alternate pin enable: 0=TMR1/PWM1/CAP1 on PA[10], 1=TMR1_/PWM1_/CAP1_ on PB[10] +#define RB_PIN_TMR2 0x04 // RW, TMR2 alternate pin enable: 0=TMR2/PWM2/CAP2 on PA[11], 1=TMR2_/PWM2_/CAP2_ on PB[11] +#define RB_PIN_TMR3 0x08 // RW, TMR3 alternate pin enable: 0=TMR3/PWM3/CAP3 on PA[2], 1=TMR3_/PWM3_/CAP3_ on PB[22] +#define RB_PIN_UART0 0x10 // RW, RXD0/TXD0 alternate pin enable: 0=RXD0/TXD0 on PB[4]/PB[7], 1=RXD0_/TXD0_ on PA[15]/PA[14] +#define RB_PIN_UART1 0x20 // RW, RXD1/TXD1 alternate pin enable: 0=RXD1/TXD1 on PA[8]/PA[9], 1=RXD1_/TXD1_ on PB[12]/PB[13] +#define RB_PIN_UART2 0x40 // RW, RXD2/TXD2 alternate pin enable: 0=RXD2/TXD2 on PA[6]/PA[7], 1=RXD2_/TXD2_ on PB[22]/PB[23] +#define RB_PIN_UART3 0x80 // RW, RXD3/TXD3 alternate pin enable: 0=RXD3/TXD3 on PA[4]/PA[5], 1=RXD3_/TXD3_ on PB[20]/PB[21] +#define RB_PIN_SPI0 0x100 // RW, SCS/SCK0/MOSI/MISO alternate pin enable: 0=SCS/SCK0/MOSI/MISO on PA[12]/PA[13]/PA[14]/PA[15], 1=SCS_/SCK0_/MOSI_/MISO_ on PB[12]/PB[13]/PB[14]/PB[15] +#define RB_PIN_PWMX 0x400 // RW, PWM4/PWM5/PWM7/PWM8/PWM9 alternate pin enable: 0=PWM4/5/7/8/9 on PA[12]/PA[13]/PB[4]/PB[6]/PB[7], 1=PWM4/5/7/8/9 on PA[6]/PA[7]/PB[1]/PB[2]/P[3] +#define RB_PIN_I2C 0x800 // RW, SCL/SDA alternate pin enable: 0=SCL/SDA on PB[13]/PB[12], 1=SCL_/SDA_ on PB[21]/PB[20] +#define RB_PIN_MODEM 0x1000 // RW, DSR/DTR alternate pin enable: 0=DSR/DTR on PB[1]/PB[5], 1=DSR_/DTR_ on PB[14]/PB[15] +#define RB_DEBUG_EN 0x2000 // RW, Debug interface disable control bit: 0=enable debug, 1=disable debug +#define RB_RF_ANT_SW_EN 0x8000 // RW, RF antenna switch control output enable: 0=disable output, 1=output on PB[16]/PB[17]/PB[18]/PB[19]/PB[20]/PB[21] +#define R16_PIN_ANALOG_IE (*((PUINT16V)0x4000101A)) // RW, analog pin enable and digital input disable +#define RB_PIN_USB_DP_PU 0x40 // RW, USB UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode +#define RB_PIN_USB_IE 0x80 // RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable +#define R32_PIN_CONFIG2 (*((PUINT32V)0x4000101C)) // RW, I/O pin configuration +#define RB_PIN_PA4_15_DIS 0xFFF0 // RW, PA4-PA15 digital input disable +#define RB_PIN_PB0_DIS 0x10000 // RW, PB0 digital input disable +#define RB_PIN_PB4_DIS 0x100000 // RW, PB4 digital input disable +#define RB_PIN_PB6_7_DIS 0xC00000 // RW, PB6-PB7 digital input disable +#define RB_PIN_PB22_23_DIS 0x3000000 // RW, PB22-PB23 digital input disable +#define RB_PIN_PB10_15_DIS 0xFC000000 // RW, PB10-PB15 digital input disable + +/* System: power management register */ +#define R32_POWER_MANAG (*((PUINT32V)0x40001020)) // RWA, power management register, SAM +#define R16_POWER_PLAN (*((PUINT16V)0x40001020)) // RWA, power plan before sleep instruction, SAM +#define RB_PWR_XROM 0x01 // RWA, power for flash ROM +#define RB_PWR_RAM2K 0x02 // RWA, power for retention 2KB SRAM +#define RB_PWR_CORE 0x04 // RWA, power retention for core and base peripherals +#define RB_PWR_EXTEND 0x08 // RWA, power retention for USB and BLE +#define RB_PWR_RAM24K 0x10 // RWA, power for main SRAM +#define RB_MAIN_ACT 0x40 // RWA, main power chose +#define RB_PWR_SYS_EN 0x80 // RWA, power for system +#define RB_PWR_LDO_EN 0x0100 // RWA, LDO enable +#define RB_PWR_DCDC_EN 0x0200 // RWA, DC/DC converter enable: 0=DC/DC disable and bypass, 1=DC/DC enable +#define RB_PWR_DCDC_PRE 0x0400 // RWA, DC/DC converter pre-enable +#define RB_XT_PRE_CFG 0x1800 // RWA, extern 32MHz HSE early wake up time configuration +#define RB_PWR_MUST_0 0x2000 // RWA, must write 0 +#define RB_XT_PRE_EN 0x4000 // RWA, extern 32MHz HSE early wake up enable, must be used with LSI/LSE +#define RB_PWR_PLAN_EN 0x8000 // RWA/WZ, power plan enable, auto clear after sleep executed +#define R16_AUX_POWER_ADJ (*((PUINT16V)0x40001022)) // RWA, aux power adjust control, SAM +#define RB_ULPLDO_ADJ 0x0007 // RWA, Ultra-Low-Power LDO voltage adjust +#define RB_DCDC_CHARGE 0x0080 // RWA, DC/DC aux charge enable +#define RB_IPU_TKEY_SEL 0xC000 // RWA, TouchKey wakeup + +/* System: battery detector register */ +#define R32_BATTERY_CTRL (*((PUINT32V)0x40001024)) // RWA, battery voltage detector, SAM +#define R8_BAT_DET_CTRL (*((PUINT8V)0x40001024)) // RWA, battery voltage detector control, SAM +#define RB_BAT_DET_EN 0x01 // RWA, battery voltage detector enable if RB_BAT_MON_EN=0 +#define RB_BAT_LOW_VTHX 0x01 // RWA, select monitor threshold voltage if RB_BAT_MON_EN=1 +#define RB_BAT_MON_EN 0x02 // RWA, battery voltage monitor enable under sleep mode +#define RB_BAT_LOWER_IE 0x04 // RWA, interrupt enable for battery lower voltage +#define RB_BAT_LOW_IE 0x08 // RWA, interrupt enable for battery low voltage +// request NMI interrupt if both RB_BAT_LOWER_IE and RB_BAT_LOW_IE enabled +#define R8_BAT_DET_CFG (*((PUINT8V)0x40001025)) // RWA, battery voltage detector configuration, SAM +#define RB_BAT_LOW_VTH 0x03 // RWA, select detector/monitor threshold voltage of battery voltage low +#define R8_BAT_STATUS (*((PUINT8V)0x40001026)) // RO, battery status +#define RB_BAT_STAT_LOWER 0x01 // RO, battery lower voltage status for detector, high action +#define RB_BAT_STAT_LOW 0x02 // RO, battery low voltage status for detector/monitor, high action + +/* System: 32KHz oscillator control register */ +#define R32_OSC32K_CTRL (*((PUINT32V)0x4000102C)) // RWA, 32KHz oscillator control, SAM +#define R16_INT32K_TUNE (*((PUINT16V)0x4000102C)) // RWA, internal 32KHz oscillator tune control, SAM +#define RB_INT32K_TUNE 0x1FFF // RWA, internal 32KHz oscillator frequency tune +#define R8_XT32K_TUNE (*((PUINT8V)0x4000102E)) // RWA, external 32KHz oscillator tune control, SAM +#define RB_XT32K_I_TUNE 0x03 // RWA, external 32KHz oscillator current tune: 00=75% current, 01=standard current, 10=150% current, 11=200% current for startup +#define RB_XT32K_C_LOAD 0xF0 // RWA, external 32KHz oscillator load capacitor tune: Cap = RB_XT32K_C_LOAD + 12pF +#define R8_CK32K_CONFIG (*((PUINT8V)0x4000102F)) // RWA, 32KHz oscillator configure +#define RB_CLK_XT32K_PON 0x01 // RWA, external 32KHz oscillator power on +#define RB_CLK_INT32K_PON 0x02 // RWA, internal 32KHz oscillator power on +#define RB_CLK_OSC32K_XT 0x04 // RWA, 32KHz oscillator source selection: 0=RC, 1=XT +#define RB_CLK_OSC32K_FILT 0x08 // RWA, internal 32KHz oscillator low noise mode disable: 1=enable, 0=disable +#define RB_32K_CLK_PIN 0x80 // RO, 32KHz oscillator clock pin status + +/* System: real-time clock register */ +#define R32_RTC_CTRL (*((PUINT32V)0x40001030)) // RWA, RTC control, SAM +#define R8_RTC_FLAG_CTRL (*((PUINT8V)0x40001030)) // RW, RTC flag and clear control +#define RB_RTC_TMR_CLR 0x10 // RW, set 1 to clear RTC timer action flag, auto clear +#define RB_RTC_TRIG_CLR 0x20 // RW, set 1 to clear RTC trigger action flag, auto clear +#define RB_RTC_TMR_FLAG 0x40 // RO, RTC timer action flag +#define RB_RTC_TRIG_FLAG 0x80 // RO, RTC trigger action flag +#define R8_RTC_MODE_CTRL (*((PUINT8V)0x40001031)) // RWA, RTC mode control, SAM +#define RB_RTC_TMR_MODE 0x07 // RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S +#define RB_RTC_IGNORE_B0 0x08 // RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0 +#define RB_RTC_TMR_EN 0x10 // RWA, RTC timer mode enable +#define RB_RTC_TRIG_EN 0x20 // RWA, RTC trigger mode enable +#define RB_RTC_LOAD_LO 0x40 // RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded +#define RB_RTC_LOAD_HI 0x80 // RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded +#define R32_RTC_TRIG (*((PUINT32V)0x40001034)) // RWA, RTC trigger value, SAM +#define R32_RTC_CNT_32K (*((PUINT32V)0x40001038)) // RO, RTC count based 32KHz +#define R16_RTC_CNT_32K (*((PUINT16V)0x40001038)) // RO, RTC count based 32KHz +#define R16_RTC_CNT_2S (*((PUINT16V)0x4000103A)) // RO, RTC count based 2 second +#define R32_RTC_CNT_DAY (*((PUINT32V)0x4000103C)) // RO, RTC count based one day, only low 14 bit + +/*System: Miscellaneous Control register */ +#define R32_MISC_CTRL (*((PUINT32V)0x40001048)) // RWA, miscellaneous control register +#define R8_PLL_CONFIG (*((PUINT8V)0x4000104B)) // RWA, PLL configuration control, SAM +#define RB_PLL_CFG_DAT 0x7F // RWA, PLL configuration control, SAM + +/* System: 32MHz oscillator control register */ +#define R8_XT32M_TUNE (*((PUINT8V)0x4000104E)) // RWA, external 32MHz oscillator tune control, SAM +#define RB_XT32M_I_BIAS 0x03 // RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current +#define RB_XT32M_C_LOAD 0x70 // RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF + +/* System: oscillator frequency calibration register */ +#define R32_OSC_CALIB (*((PUINT32V)0x40001050)) // RWA, oscillator frequency calibration, SAM +#define R16_OSC_CAL_CNT (*((PUINT16V)0x40001050)) // RO, system clock count value for 32KHz multi-cycles +#define RB_OSC_CAL_CNT 0x3FFF // RO, system clock count value for 32KHz multi-cycles +#define RB_OSC_CAL_OV_CLR 0x4000 // RW1, indicate R8_OSC_CAL_OV_CNT not zero, set 1 to clear R8_OSC_CAL_OV_CNT +#define RB_OSC_CAL_IF 0x8000 // RW1, interrupt flag for oscillator capture end, set 1 to clear +#define R8_OSC_CAL_OV_CNT (*((PUINT8V)0x40001052)) // RO, oscillator frequency calibration overflow times +#define R8_OSC_CAL_CTRL (*((PUINT8V)0x40001053)) // RWA, oscillator frequency calibration control, SAM +#define RB_OSC_CNT_TOTAL 0x07 // RWA, total cycles mode for oscillator capture +// RB_OSC_CNT_TOTAL: select total cycles for oscillator capture +// 000: 1 +// 001: 2 +// 010: 4 +// 011: 32 +// 100: 64 +// 101: 128 +// 110: 1024 +// 111: 2047 +#define RB_OSC_CNT_HALT 0x08 // RO, calibration counter halt status: 0=counting, 1=halt for reading count value +#define RB_OSC_CAL_IE 0x10 // RWA, interrupt enable for oscillator capture end +#define RB_OSC_CNT_EN 0x20 // RWA, calibration counter enable +#define RB_OSC_CNT_END 0x40 // RWA, select oscillator capture end mode: 0=normal, 1=append 2 cycles + +/* System: ADC and Touch-key register */ +#define R32_ADC_CTRL (*((PUINT32V)0x40001058)) // RW, ADC control +#define R8_ADC_CHANNEL (*((PUINT8V)0x40001058)) // RW, ADC input channel selection +#define RB_ADC_CH_INX 0x0F // RW, ADC input channel index +#define R8_ADC_CFG (*((PUINT8V)0x40001059)) // RW, ADC configure +#define RB_ADC_POWER_ON 0x01 // RW, ADC power control: 0=power down, 1=power on +#define RB_ADC_BUF_EN 0x02 // RW, ADC input buffer enable +#define RB_ADC_DIFF_EN 0x04 // RW, ADC input channel mode: 0=single-end, 1=differnetial +#define RB_ADC_OFS_TEST 0x08 // RW, enable ADC offset test mode: 0=normal mode, 1=short to test offset +#define RB_ADC_PGA_GAIN 0x30 // RW, set ADC input PGA gain: 00=-12dB, 01=-6dB, 10=0dB, 11=6dB +#define RB_ADC_CLK_DIV 0xC0 // RW, select ADC clock frequency: 00=3.2MHz, 01=8MHz, 10=5.33MHz, 11=4MHz +#define R8_ADC_CONVERT (*((PUINT8V)0x4000105A)) // RW, ADC convert control +#define RB_ADC_START 0x01 // RW, ADC convert start control: 0=stop ADC convert, 1=start an ADC convert, auto clear +#define RB_ADC_PGA_GAIN2 0x02 // RW, ADC gain direction, must be 0 when using TS +#define RB_ADC_EOC_X 0x80 // RO, end of ADC conversion flag +#define R8_TEM_SENSOR (*((PUINT8V)0x4000105B)) // RW, temperature sensor control +#define RB_TEM_SEN_PWR_ON 0x80 // RW, temperature sensor power control: 0=power down, 1=power on +#define R32_ADC_DATA (*((PUINT32V)0x4000105C)) // RO, ADC data and status +#define R16_ADC_DATA (*((PUINT16V)0x4000105C)) // RO, ADC data +#define RB_ADC_DATA 0x0FFF // RO, ADC conversion data +#define R8_ADC_INT_FLAG (*((PUINT8V)0x4000105E)) // RO, ADC interrupt flag register +#define RB_ADC_IF_EOC 0x80 // RO, ADC conversion interrupt flag: 0=free or converting, 1=end of conversion, interrupt action, auto ADC or write R8_ADC_CONVERT or write R8_TKEY_CONVERT to clear flag +#define R32_TKEY_CTRL (*((PUINT8V)0x40001054)) // RW, Touchkey control +#define R8_TKEY_COUNT (*((PUINT8V)0x40001054)) // RW, Touchkey charge and discharge count +#define RB_TKEY_CHARG_CNT 0x1F // RW, Touchkey charge count +#define RB_TKEY_DISCH_CNT 0xE0 // RW, Touchkey discharge count +#define R8_TKEY_CONVERT (*((PUINT8V)0x40001056)) // RW, Touchkey convert control +#define RB_TKEY_START 0x01 // RW, Touchkey convert start control: 0=stop Touchkey convert, 1=start a Touchkey convert, auto clear +#define R8_TKEY_CFG (*((PUINT8V)0x40001057)) // RW, Touchkey configure +#define RB_TKEY_PWR_ON 0x01 // RW, Touchkey power on: 0=power down, 1=power on +#define RB_TKEY_CURRENT 0x02 // RW, Touchkey charge current selection: 0=35uA, 1=70uA +#define RB_TKEY_DRV_EN 0x04 // RW, Touchkey drive shield enable +#define RB_TKEY_PGA_ADJ 0x08 // RW, ADC input PGA speed selection: 0=slow, 1=fast +#define RB_TKEY_RAND_EN 0x10 // RW, Touchkey random trigger enable +#define RB_TKEY_AUTO_EN 0x20 // RW, Touchkey auto-trigger enable +#define RB_TKEY_DMA_EN 0x40 // RW, Touchkey DMA enable +#define R32_ADC_DMA_CTRL (*((PUINT32V)0x40001060)) // RW, ADC DMA control +#define R8_ADC_CTRL_DMA (*((PUINT8V)0x40001061)) // RW, ADC DMA control +#define RB_ADC_DMA_ENABLE 0x01 // RW, ADC DMA enable +#define RB_ADC_DMA_LOOP 0x04 // RW, ADC DMA address loop enable +#define RB_ADC_IE_DMA_END 0x08 // RW, enable interrupt for ADC DMA completion +#define RB_ADC_IE_EOC 0x10 // RW, enable interrupt for end of ADC conversion +#define RB_ADC_CONT_EN 0x40 // RW, enable contineous conversion ADC +#define RB_ADC_AUTO_EN 0x80 // RW, enable auto continuing ADC for DMA +#define R8_ADC_DMA_IF (*((PUINT8V)0x40001062)) // RW1, ADC interrupt flag +#define RB_ADC_IF_DMA_END 0x08 // RW1, interrupt flag for ADC DMA completion +#define RB_ADC_IF_END_ADC 0x10 // RW1, interrupt flag for end of ADC conversion, DMA for auto ADC or write R8_ADC_CONVERT to clear flag +#define R8_ADC_AUTO_CYCLE (*((PUINT8V)0x40001063)) // RW, auto ADC cycle value, unit is 16 Fsys +#define R32_ADC_DMA_NOW (*((PUINT32V)0x40001064)) // RW, ADC DMA current address +#define R16_ADC_DMA_NOW (*((PUINT16V)0x40001064)) // RW, ADC DMA current address +#define R32_ADC_DMA_BEG (*((PUINT32V)0x40001068)) // RW, ADC DMA begin address +#define R16_ADC_DMA_BEG (*((PUINT16V)0x40001068)) // RW, ADC DMA begin address +#define R32_ADC_DMA_END (*((PUINT32V)0x4000106C)) // RW, ADC DMA end address +#define R16_ADC_DMA_END (*((PUINT16V)0x4000106C)) // RW, ADC DMA end address +#define R32_ADC_SCAN_CFG1 (*((PUINT32V)0x40001070)) // RW, ADC scan config 1 +#define R32_ADC_SCAN_CFG2 (*((PUINT32V)0x40001074)) // RW, ADC scan config 2 + +/* System: Flash ROM control register */ +#define R32_FLASH_DATA (*((PUINT32V)0x40001800)) // RO/WO, flash ROM data +#define R32_FLASH_CONTROL (*((PUINT32V)0x40001804)) // RW, flash ROM control +#define R8_FLASH_DATA (*((PUINT8V)0x40001804)) // RO/WO, flash ROM data buffer +#define R8_FLASH_CTRL (*((PUINT8V)0x40001806)) // RW, flash ROM access control +#define R8_FLASH_CFG (*((PUINT8V)0x40001807)) // RW, flash ROM access config, SAM + +/* System: GPIO interrupt control register */ +#define R32_GPIO_INT_EN (*((PUINT32V)0x40001090)) // RW, GPIO interrupt enable +#define R16_PA_INT_EN (*((PUINT16V)0x40001090)) // RW, GPIO PA interrupt enable +#define R16_PB_INT_EN (*((PUINT16V)0x40001092)) // RW, GPIO PB interrupt enable +#define R32_GPIO_INT_MODE (*((PUINT32V)0x40001094)) // RW, GPIO interrupt mode: 0=level action, 1=edge action +#define R16_PA_INT_MODE (*((PUINT16V)0x40001094)) // RW, GPIO PA interrupt mode: 0=level action, 1=edge action +#define R16_PB_INT_MODE (*((PUINT16V)0x40001096)) // RW, GPIO PB interrupt mode: 0=level action, 1=edge action +#define R32_GPIO_INT_IF (*((PUINT32V)0x4000109C)) // RW1, GPIO interrupt flag +#define R16_PA_INT_IF (*((PUINT16V)0x4000109C)) // RW1, GPIO PA interrupt flag +#define R16_PB_INT_IF (*((PUINT16V)0x4000109E)) // RW1, GPIO PB interrupt flag + +/* GPIO PA register */ +#define R32_PA_DIR (*((PUINT32V)0x400010A0)) // RW, GPIO PA I/O direction: 0=in, 1=out +#define R8_PA_DIR_0 (*((PUINT8V)0x400010A0)) // RW, GPIO PA I/O direction byte 0 +#define R8_PA_DIR_1 (*((PUINT8V)0x400010A1)) // RW, GPIO PA I/O direction byte 1 +#define R32_PA_PIN (*((PUINT32V)0x400010A4)) // RO, GPIO PA input +#define R8_PA_PIN_0 (*((PUINT8V)0x400010A4)) // RO, GPIO PA input byte 0 +#define R8_PA_PIN_1 (*((PUINT8V)0x400010A5)) // RO, GPIO PA input byte 1 +#define R32_PA_OUT (*((PUINT32V)0x400010A8)) // RW, GPIO PA output +#define R8_PA_OUT_0 (*((PUINT8V)0x400010A8)) // RW, GPIO PA output byte 0 +#define R8_PA_OUT_1 (*((PUINT8V)0x400010A9)) // RW, GPIO PA output byte 1 +#define R32_PA_CLR (*((PUINT32V)0x400010AC)) // WZ, GPIO PA clear output: 0=keep, 1=clear +#define R8_PA_CLR_0 (*((PUINT8V)0x400010AC)) // WZ, GPIO PA clear output byte 0 +#define R8_PA_CLR_1 (*((PUINT8V)0x400010AD)) // WZ, GPIO PA clear output byte 1 +#define R32_PA_PU (*((PUINT32V)0x400010B0)) // RW, GPIO PA pullup resistance enable +#define R8_PA_PU_0 (*((PUINT8V)0x400010B0)) // RW, GPIO PA pullup resistance enable byte 0 +#define R8_PA_PU_1 (*((PUINT8V)0x400010B1)) // RW, GPIO PA pullup resistance enable byte 1 +#define R32_PA_PD_DRV (*((PUINT32V)0x400010B4)) // RW, PA pulldown for input or PA driving capability for output +#define R8_PA_PD_DRV_0 (*((PUINT8V)0x400010B4)) // RW, PA pulldown for input or PA driving capability for output byte 0 +#define R8_PA_PD_DRV_1 (*((PUINT8V)0x400010B5)) // RW, PA pulldown for input or PA driving capability for output byte 1 + +/* GPIO PB register */ +#define R32_PB_DIR (*((PUINT32V)0x400010C0)) // RW, GPIO PB I/O direction: 0=in, 1=out +#define R8_PB_DIR_0 (*((PUINT8V)0x400010C0)) // RW, GPIO PB I/O direction byte 0 +#define R8_PB_DIR_1 (*((PUINT8V)0x400010C1)) // RW, GPIO PB I/O direction byte 1 +#define R8_PB_DIR_2 (*((PUINT8V)0x400010C2)) // RW, GPIO PB I/O direction byte 2 +#define R32_PB_PIN (*((PUINT32V)0x400010C4)) // RO, GPIO PB input +#define R8_PB_PIN_0 (*((PUINT8V)0x400010C4)) // RO, GPIO PB input byte 0 +#define R8_PB_PIN_1 (*((PUINT8V)0x400010C5)) // RO, GPIO PB input byte 1 +#define R8_PB_PIN_2 (*((PUINT8V)0x400010C6)) // RO, GPIO PB input byte 2 +#define R32_PB_OUT (*((PUINT32V)0x400010C8)) // RW, GPIO PB output +#define R8_PB_OUT_0 (*((PUINT8V)0x400010C8)) // RW, GPIO PB output byte 0 +#define R8_PB_OUT_1 (*((PUINT8V)0x400010C9)) // RW, GPIO PB output byte 1 +#define R8_PB_OUT_2 (*((PUINT8V)0x400010CA)) // RW, GPIO PB output byte 2 +#define R32_PB_CLR (*((PUINT32V)0x400010CC)) // WZ, GPIO PB clear output: 0=keep, 1=clear +#define R8_PB_CLR_0 (*((PUINT8V)0x400010CC)) // WZ, GPIO PB clear output byte 0 +#define R8_PB_CLR_1 (*((PUINT8V)0x400010CD)) // WZ, GPIO PB clear output byte 1 +#define R8_PB_CLR_2 (*((PUINT8V)0x400010CE)) // WZ, GPIO PB clear output byte 2 +#define R32_PB_PU (*((PUINT32V)0x400010D0)) // RW, GPIO PB pullup resistance enable +#define R8_PB_PU_0 (*((PUINT8V)0x400010D0)) // RW, GPIO PB pullup resistance enable byte 0 +#define R8_PB_PU_1 (*((PUINT8V)0x400010D1)) // RW, GPIO PB pullup resistance enable byte 1 +#define R8_PB_PU_2 (*((PUINT8V)0x400010D2)) // RW, GPIO PB pullup resistance enable byte 2 +#define R32_PB_PD_DRV (*((PUINT32V)0x400010D4)) // RW, PB pulldown for input or PB driving capability for output +#define R8_PB_PD_DRV_0 (*((PUINT8V)0x400010D4)) // RW, PB pulldown for input or PB driving capability for output byte 0 +#define R8_PB_PD_DRV_1 (*((PUINT8V)0x400010D5)) // RW, PB pulldown for input or PB driving capability for output byte 1 +#define R8_PB_PD_DRV_2 (*((PUINT8V)0x400010D6)) // RW, PB pulldown for input or PB driving capability for output byte 2 + +/* GPIO register address offset and bit define */ +#define BA_PA ((PUINT8V)0x400010A0) // point GPIO PA base address +#define BA_PB ((PUINT8V)0x400010C0) // point GPIO PB base address +#define GPIO_DIR 0x00 +#define GPIO_DIR_0 0x00 +#define GPIO_DIR_1 0x01 +#define GPIO_DIR_2 0x02 +#define GPIO_PIN 0x04 +#define GPIO_PIN_0 0x04 +#define GPIO_PIN_1 0x05 +#define GPIO_PIN_2 0x06 +#define GPIO_OUT 0x08 +#define GPIO_OUT_0 0x08 +#define GPIO_OUT_1 0x09 +#define GPIO_OUT_2 0x0A +#define GPIO_CLR 0x0C +#define GPIO_CLR_0 0x0C +#define GPIO_CLR_1 0x0D +#define GPIO_CLR_2 0x0E +#define GPIO_PU 0x10 +#define GPIO_PU_0 0x10 +#define GPIO_PU_1 0x11 +#define GPIO_PU_2 0x12 +#define GPIO_PD_DRV 0x14 +#define GPIO_PD_DRV_0 0x14 +#define GPIO_PD_DRV_1 0x15 +#define GPIO_PD_DRV_2 0x16 + +/* GPIO alias name */ +#define bAIN9 (1<<0) // PA0 +#define bSCK1 (1<<0) // PA0 +#define bAIN8 (1<<1) // PA1 +#define bSDO (1<<1) // PA1 +#define bMOSI1 bSDO +#define bAIN7 (1<<2) // PA2 +#define bSDI (1<<2) // PA2 +#define bMISO1 bSDI +#define bAIN6 (1<<3) // PA3 +#define bAIN0 (1<<4) // PA4 +#define bRXD3 (1<<4) // PA4 +#define bRXD3_ (1<<4) // PA4 +#define bAIN1 (1<<5) // PA5 +#define bTXD3 (1<<5) // PA5 +#define bTXD3_ (1<<5) // PA5 +#define bAIN10 (1<<6) // PA6 +#define bRXD2_ (1<<6) // PA6 +#define bPWM4_ (1<<6) // PA6 +#define bAIN11 (1<<7) // PA7 +#define bTXD2_ (1<<7) // PA7 +#define bPWM5_ (1<<7) // PA7 +#define bAIN12 (1<<8) // PA8 +#define bRXD1 (1<<8) // PA8 +#define bAIN13 (1<<9) // PA9 +#define bTMR0 (1<<9) // PA9 +#define bCAP0 bTMR0 +#define bPWM0 bTMR0 +#define bTXD1 (1<<9) // PA9 +#define bX32KI (1<<10) // PA10 +#define bTMR1 (1<<10) // PA10 +#define bCAP1 bTMR1 +#define bPWM1 bTMR1 +#define bX32KO (1<<11) // PA11 +#define bTMR2 (1<<11) // PA11 +#define bCAP2 bTMR2 +#define bPWM2 bTMR2 +#define bAIN2 (1<<12) // PA12 +#define bPWM4 (1<<12) // PA12 +#define bSCS (1<<12) // PA12 +#define bAIN3 (1<<13) // PA13 +#define bSCK0 (1<<13) // PA13 +#define bPWM5 (1<<13) // PA13 +#define bAIN4 (1<<14) // PA14 +#define bMOSI (1<<14) // PA14 +#define bTXD0_ (1<<14) // PA14 +#define bAIN5 (1<<15) // PA15 +#define bMISO (1<<15) // PA15 +#define bRXD0_ (1<<15) // PA15 +#define bPWM6 (1<<0) // PB0 +#define bCTS (1<<0) // PB0 +#define bDSR (1<<1) // PB1 +#define bPWM7_ (1<<1) // PB1 +#define bRI (1<<2) // PB2 +#define bPWM8_ (1<<2) // PB2 +#define bDCD (1<<3) // PB3 +#define bPWM9_ (1<<3) // PB3 +#define bPWM7 (1<<4) // PB4 +#define bRXD0 (1<<4) // PB4 +#define bDTR (1<<5) // PB5 +#define bRTS (1<<6) // PB6 +#define bPWM8 (1<<6) // PB6 +#define bTXD0 (1<<7) // PB7 +#define bPWM9 (1<<7) // PB7 +#define bUDM (1<<10) // PB10 +#define bTMR1_ (1<<10) // PB10 +#define bCAP1_ bTMR1_ +#define bPWM1_ bTMR1_ +#define bUDP (1<<11) // PB11 +#define bTMR2_ (1<<11) // PB11 +#define bCAP2_ bTMR2_ +#define bPWM2_ bTMR2_ +#define bU2DM (1<<12) // PB12 +#define bSCS_ (1<<12) // PB12 +#define bRXD1_ (1<<12) // PB12 +#define bU2DP (1<<13) // PB13 +#define bSCK0_ (1<<13) // PB13 +#define bTXD1_ (1<<13) // PB13 +#define bTIO (1<<14) // PB14 +#define bDSR_ (1<<14) // PB14 +#define bMOSI_ (1<<14) // PB14 +#define bSDA (1<<14) // PB14 +#define bPWM10 (1<<14) // PB14 +#define bTCK (1<<15) // PB15 +#define bMISO_ (1<<15) // PB15 +#define bSCL (1<<15) // PB15 +#define bDTR_ (1<<15) // PB15 +#define bRXD2 (1<<22) // PB22 +#define bTMR3 (1<<22) // PB22 +#define bCAP3 bTMR3 +#define bPWM3 bTMR3 +#define bTMR3_ (1<<22) // PB22 +#define bCAP3_ bTMR3_ +#define bPWM3_ bTMR3_ +#define bRST (1<<23) // PB23 +#define bTMR0_ (1<<23) // PB23 +#define bCAP0_ bTMR0_ +#define bPWM0_ bTMR0_ +#define bTXD2 (1<<23) // PB23 +#define bPWM11 (1<<23) // PB23 + +/* Timer0 register */ +#define R32_TMR0_CONTROL (*((PUINT32V)0x40002000)) // RW, TMR0 control +#define R8_TMR0_CTRL_MOD (*((PUINT8V)0x40002000)) // RW, TMR0 mode control +#define R8_TMR0_INTER_EN (*((PUINT8V)0x40002002)) // RW, TMR0 interrupt enable +// #define R32_TMR0_STATUS (*((PUINT32V)0x40002004)) // RW, TMR0 status +#define R8_TMR0_INT_FLAG (*((PUINT8V)0x40002006)) // RW1, TMR0 interrupt flag +#define R8_TMR0_FIFO_COUNT (*((PUINT8V)0x40002007)) // RO, TMR0 FIFO count status +#define R32_TMR0_COUNT (*((PUINT32V)0x40002008)) // RO, TMR0 current count +#define R16_TMR0_COUNT (*((PUINT16V)0x40002008)) // RO, TMR0 current count +#define R8_TMR0_COUNT (*((PUINT8V)0x40002008)) // RO, TMR0 current count +#define R32_TMR0_CNT_END (*((PUINT32V)0x4000200C)) // RW, TMR0 end count value, only low 26 bit +#define R32_TMR0_FIFO (*((PUINT32V)0x40002010)) // RO/WO, TMR0 FIFO register, only low 26 bit +#define R16_TMR0_FIFO (*((PUINT16V)0x40002010)) // RO/WO, TMR0 FIFO register +#define R8_TMR0_FIFO (*((PUINT8V)0x40002010)) // RO/WO, TMR0 FIFO register + +/* Timer1 register */ +#define R32_TMR1_CONTROL (*((PUINT32V)0x40002400)) // RW, TMR1 control +#define R8_TMR1_CTRL_MOD (*((PUINT8V)0x40002400)) // RW, TMR1 mode control +#define R8_TMR1_CTRL_DMA (*((PUINT8V)0x40002401)) // RW, TMR1 DMA control +#define R8_TMR1_INTER_EN (*((PUINT8V)0x40002402)) // RW, TMR1 interrupt enable +// #define R32_TMR1_STATUS (*((PUINT32V)0x40002404)) // RW, TMR1 status +#define R8_TMR1_INT_FLAG (*((PUINT8V)0x40002406)) // RW1, TMR1 interrupt flag +#define R8_TMR1_FIFO_COUNT (*((PUINT8V)0x40002407)) // RO, TMR1 FIFO count status +#define R32_TMR1_COUNT (*((PUINT32V)0x40002408)) // RO, TMR1 current count +#define R16_TMR1_COUNT (*((PUINT16V)0x40002408)) // RO, TMR1 current count +#define R8_TMR1_COUNT (*((PUINT8V)0x40002408)) // RO, TMR1 current count +#define R32_TMR1_CNT_END (*((PUINT32V)0x4000240C)) // RW, TMR1 end count value, only low 26 bit +#define R32_TMR1_FIFO (*((PUINT32V)0x40002410)) // RO/WO, TMR1 FIFO register, only low 26 bit +#define R16_TMR1_FIFO (*((PUINT16V)0x40002410)) // RO/WO, TMR1 FIFO register +#define R8_TMR1_FIFO (*((PUINT8V)0x40002410)) // RO/WO, TMR1 FIFO register +#define R32_TMR1_DMA_NOW (*((PUINT32V)0x40002414)) // RW, TMR1 DMA current address +#define R16_TMR1_DMA_NOW (*((PUINT16V)0x40002414)) // RW, TMR1 DMA current address +#define R32_TMR1_DMA_BEG (*((PUINT32V)0x40002418)) // RW, TMR1 DMA begin address +#define R16_TMR1_DMA_BEG (*((PUINT16V)0x40002418)) // RW, TMR1 DMA begin address +#define R32_TMR1_DMA_END (*((PUINT32V)0x4000241C)) // RW, TMR1 DMA end address +#define R16_TMR1_DMA_END (*((PUINT16V)0x4000241C)) // RW, TMR1 DMA end address + +/* Timer2 register */ +#define R32_TMR2_CONTROL (*((PUINT32V)0x40002800)) // RW, TMR2 control +#define R8_TMR2_CTRL_MOD (*((PUINT8V)0x40002800)) // RW, TMR2 mode control +#define R8_TMR2_CTRL_DMA (*((PUINT8V)0x40002801)) // RW, TMR2 DMA control +#define R8_TMR2_INTER_EN (*((PUINT8V)0x40002802)) // RW, TMR2 interrupt enable +// #define R32_TMR2_STATUS (*((PUINT32V)0x40002804)) // RW, TMR2 status +#define R8_TMR2_INT_FLAG (*((PUINT8V)0x40002806)) // RW1, TMR2 interrupt flag +#define R8_TMR2_FIFO_COUNT (*((PUINT8V)0x40002807)) // RO, TMR2 FIFO count status +#define R32_TMR2_COUNT (*((PUINT32V)0x40002808)) // RO, TMR2 current count +#define R16_TMR2_COUNT (*((PUINT16V)0x40002808)) // RO, TMR2 current count +#define R8_TMR2_COUNT (*((PUINT8V)0x40002808)) // RO, TMR2 current count +#define R32_TMR2_CNT_END (*((PUINT32V)0x4000280C)) // RW, TMR2 end count value, only low 26 bit +#define R32_TMR2_FIFO (*((PUINT32V)0x40002810)) // RO/WO, TMR2 FIFO register, only low 26 bit +#define R16_TMR2_FIFO (*((PUINT16V)0x40002810)) // RO/WO, TMR2 FIFO register +#define R8_TMR2_FIFO (*((PUINT8V)0x40002810)) // RO/WO, TMR2 FIFO register +#define R32_TMR2_DMA_NOW (*((PUINT32V)0x40002814)) // RW, TMR2 DMA current address +#define R16_TMR2_DMA_NOW (*((PUINT16V)0x40002814)) // RW, TMR2 DMA current address +#define R32_TMR2_DMA_BEG (*((PUINT32V)0x40002818)) // RW, TMR2 DMA begin address +#define R16_TMR2_DMA_BEG (*((PUINT16V)0x40002818)) // RW, TMR2 DMA begin address +#define R32_TMR2_DMA_END (*((PUINT32V)0x4000281C)) // RW, TMR2 DMA end address +#define R16_TMR2_DMA_END (*((PUINT16V)0x4000281C)) // RW, TMR2 DMA end address + +/* Timer3 register */ +#define R32_TMR3_CONTROL (*((PUINT32V)0x40002C00)) // RW, TMR3 control +#define R8_TMR3_CTRL_MOD (*((PUINT8V)0x40002C00)) // RW, TMR3 mode control +#define R8_TMR3_INTER_EN (*((PUINT8V)0x40002C02)) // RW, TMR3 interrupt enable +// #define R32_TMR3_STATUS (*((PUINT32V)0x40002C04)) // RW, TMR3 status +#define R8_TMR3_INT_FLAG (*((PUINT8V)0x40002C06)) // RW1, TMR3 interrupt flag +#define R8_TMR3_FIFO_COUNT (*((PUINT8V)0x40002C07)) // RO, TMR3 FIFO count status +#define R32_TMR3_COUNT (*((PUINT32V)0x40002C08)) // RO, TMR3 current count +#define R16_TMR3_COUNT (*((PUINT16V)0x40002C08)) // RO, TMR3 current count +#define R8_TMR3_COUNT (*((PUINT8V)0x40002C08)) // RO, TMR3 current count +#define R32_TMR3_CNT_END (*((PUINT32V)0x40002C0C)) // RW, TMR3 end count value, only low 26 bit +#define R32_TMR3_FIFO (*((PUINT32V)0x40002C10)) // RO/WO, TMR3 FIFO register, only low 26 bit +#define R16_TMR3_FIFO (*((PUINT16V)0x40002C10)) // RO/WO, TMR3 FIFO register +#define R8_TMR3_FIFO (*((PUINT8V)0x40002C10)) // RO/WO, TMR3 FIFO register + +/* Timer register address offset and bit define */ +#define TMR_FIFO_SIZE 8 // timer FIFO size (depth) +#define BA_TMR0 ((PUINT8V)0x40002000) // point TMR0 base address +#define BA_TMR1 ((PUINT8V)0x40002400) // point TMR1 base address +#define BA_TMR2 ((PUINT8V)0x40002800) // point TMR2 base address +#define BA_TMR3 ((PUINT8V)0x40002C00) // point TMR3 base address +#define TMR_CTRL_MOD 0 +#define RB_TMR_MODE_IN 0x01 // RW, timer in mode: 0=timer/PWM, 1=capture/count +#define RB_TMR_ALL_CLEAR 0x02 // RW, force clear timer FIFO and count +#define RB_TMR_COUNT_EN 0x04 // RW, timer count enable +#define RB_TMR_OUT_EN 0x08 // RW, timer output enable +#define RB_TMR_OUT_POLAR 0x10 // RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action +#define RB_TMR_CAP_COUNT 0x10 // RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count +#define RB_TMR_PWM_REPEAT 0xC0 // RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 +#define RB_TMR_CAP_EDGE 0xC0 // RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise +#define TMR_CTRL_DMA 1 +#define RB_TMR_DMA_ENABLE 0x01 // RW, timer1/2 DMA enable +#define RB_TMR_DMA_LOOP 0x04 // RW, timer1/2 DMA address loop enable +#define TMR_INTER_EN 2 +#define RB_TMR_IE_CYC_END 0x01 // RW, enable interrupt for timer capture count timeout or PWM cycle end +#define RB_TMR_IE_DATA_ACT 0x02 // RW, enable interrupt for timer capture input action or PWM trigger +#define RB_TMR_IE_FIFO_HF 0x04 // RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo <=3) +#define RB_TMR_IE_DMA_END 0x08 // RW, enable interrupt for timer1/2 DMA completion +#define RB_TMR_IE_FIFO_OV 0x10 // RW, enable interrupt for timer FIFO overflow +#define TMR_INT_FLAG 6 +#define RB_TMR_IF_CYC_END 0x01 // RW1, interrupt flag for timer capture count timeout or PWM cycle end +#define RB_TMR_IF_DATA_ACT 0x02 // RW1, interrupt flag for timer capture input action or PWM trigger +#define RB_TMR_IF_FIFO_HF 0x04 // RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo <=3) +#define RB_TMR_IF_DMA_END 0x08 // RW1, interrupt flag for timer1/2 DMA completion +#define RB_TMR_IF_FIFO_OV 0x10 // RW1, interrupt flag for timer FIFO overflow +#define TMR_FIFO_COUNT 7 +#define TMR_COUNT 0x08 +#define TMR_CNT_END 0x0C +#define TMR_FIFO 0x10 +#define TMR_DMA_NOW 0x14 +#define TMR_DMA_BEG 0x18 +#define TMR_DMA_END 0x1C + +/* UART0 register */ +#define R32_UART0_CTRL (*((PUINT32V)0x40003000)) // RW, UART0 control +#define R8_UART0_MCR (*((PUINT8V)0x40003000)) // RW, UART0 modem control +#define R8_UART0_IER (*((PUINT8V)0x40003001)) // RW, UART0 interrupt enable +#define R8_UART0_FCR (*((PUINT8V)0x40003002)) // RW, UART0 FIFO control +#define R8_UART0_LCR (*((PUINT8V)0x40003003)) // RW, UART0 line control +#define R32_UART0_STAT (*((PUINT32V)0x40003004)) // RO, UART0 status +#define R8_UART0_IIR (*((PUINT8V)0x40003004)) // RO, UART0 interrupt identification +#define R8_UART0_LSR (*((PUINT8V)0x40003005)) // RO, UART0 line status +#define R8_UART0_MSR (*((PUINT8V)0x40003006)) // RO, UART0 modem status +#define R32_UART0_FIFO (*((PUINT32V)0x40003008)) // RW, UART0 data or FIFO port +#define R8_UART0_RBR (*((PUINT8V)0x40003008)) // RO, UART0 receiver buffer, receiving byte +#define R8_UART0_THR (*((PUINT8V)0x40003008)) // WO, UART0 transmitter holding, transmittal byte +#define R8_UART0_RFC (*((PUINT8V)0x4000300A)) // RO, UART0 receiver FIFO count +#define R8_UART0_TFC (*((PUINT8V)0x4000300B)) // RO, UART0 transmitter FIFO count +#define R32_UART0_SETUP (*((PUINT32V)0x4000300C)) // RW, UART0 setup +#define R16_UART0_DL (*((PUINT16V)0x4000300C)) // RW, UART0 divisor latch +#define R8_UART0_DLL (*((PUINT8V)0x4000300C)) // RW, UART0 divisor latch LSB byte +// #define R8_UART0_DLM (*((PUINT8V)0x4000300D)) // RW, UART0 divisor latch MSB byte +#define R8_UART0_DIV (*((PUINT8V)0x4000300E)) // RW, UART0 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 +#define R8_UART0_ADR (*((PUINT8V)0x4000300F)) // RW, UART0 slave address: 0xFF=disable, other=enable + +/* UART1 register */ +#define R32_UART1_CTRL (*((PUINT32V)0x40003400)) // RW, UART1 control +#define R8_UART1_MCR (*((PUINT8V)0x40003400)) // RW, UART1 modem control +#define R8_UART1_IER (*((PUINT8V)0x40003401)) // RW, UART1 interrupt enable +#define R8_UART1_FCR (*((PUINT8V)0x40003402)) // RW, UART1 FIFO control +#define R8_UART1_LCR (*((PUINT8V)0x40003403)) // RW, UART1 line control +#define R32_UART1_STAT (*((PUINT32V)0x40003404)) // RO, UART1 status +#define R8_UART1_IIR (*((PUINT8V)0x40003404)) // RO, UART1 interrupt identification +#define R8_UART1_LSR (*((PUINT8V)0x40003405)) // RO, UART1 line status +#define R32_UART1_FIFO (*((PUINT32V)0x40003408)) // RW, UART1 data or FIFO port +#define R8_UART1_RBR (*((PUINT8V)0x40003408)) // RO, UART1 receiver buffer, receiving byte +#define R8_UART1_THR (*((PUINT8V)0x40003408)) // WO, UART1 transmitter holding, transmittal byte +#define R8_UART1_RFC (*((PUINT8V)0x4000340A)) // RO, UART1 receiver FIFO count +#define R8_UART1_TFC (*((PUINT8V)0x4000340B)) // RO, UART1 transmitter FIFO count +#define R32_UART1_SETUP (*((PUINT32V)0x4000340C)) // RW, UART1 setup +#define R16_UART1_DL (*((PUINT16V)0x4000340C)) // RW, UART1 divisor latch +#define R8_UART1_DLL (*((PUINT8V)0x4000340C)) // RW, UART1 divisor latch LSB byte +// #define R8_UART1_DLM (*((PUINT8V)0x4000340D)) // RW, UART1 divisor latch MSB byte +#define R8_UART1_DIV (*((PUINT8V)0x4000340E)) // RW, UART1 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART2 register */ +#define R32_UART2_CTRL (*((PUINT32V)0x40003800)) // RW, UART2 control +#define R8_UART2_MCR (*((PUINT8V)0x40003800)) // RW, UART2 modem control +#define R8_UART2_IER (*((PUINT8V)0x40003801)) // RW, UART2 interrupt enable +#define R8_UART2_FCR (*((PUINT8V)0x40003802)) // RW, UART2 FIFO control +#define R8_UART2_LCR (*((PUINT8V)0x40003803)) // RW, UART2 line control +#define R32_UART2_STAT (*((PUINT32V)0x40003804)) // RO, UART2 status +#define R8_UART2_IIR (*((PUINT8V)0x40003804)) // RO, UART2 interrupt identification +#define R8_UART2_LSR (*((PUINT8V)0x40003805)) // RO, UART2 line status +#define R32_UART2_FIFO (*((PUINT32V)0x40003808)) // RW, UART2 data or FIFO port +#define R8_UART2_RBR (*((PUINT8V)0x40003808)) // RO, UART2 receiver buffer, receiving byte +#define R8_UART2_THR (*((PUINT8V)0x40003808)) // WO, UART2 transmitter holding, transmittal byte +#define R8_UART2_RFC (*((PUINT8V)0x4000380A)) // RO, UART2 receiver FIFO count +#define R8_UART2_TFC (*((PUINT8V)0x4000380B)) // RO, UART2 transmitter FIFO count +#define R32_UART2_SETUP (*((PUINT32V)0x4000380C)) // RW, UART2 setup +#define R16_UART2_DL (*((PUINT16V)0x4000380C)) // RW, UART2 divisor latch +#define R8_UART2_DLL (*((PUINT8V)0x4000380C)) // RW, UART2 divisor latch LSB byte +// #define R8_UART2_DLM (*((PUINT8V)0x4000380D)) // RW, UART2 divisor latch MSB byte +#define R8_UART2_DIV (*((PUINT8V)0x4000380E)) // RW, UART2 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART3 register */ +#define R32_UART3_CTRL (*((PUINT32V)0x40003C00)) // RW, UART3 control +#define R8_UART3_MCR (*((PUINT8V)0x40003C00)) // RW, UART3 modem control +#define R8_UART3_IER (*((PUINT8V)0x40003C01)) // RW, UART3 interrupt enable +#define R8_UART3_FCR (*((PUINT8V)0x40003C02)) // RW, UART3 FIFO control +#define R8_UART3_LCR (*((PUINT8V)0x40003C03)) // RW, UART3 line control +#define R32_UART3_STAT (*((PUINT32V)0x40003C04)) // RO, UART3 status +#define R8_UART3_IIR (*((PUINT8V)0x40003C04)) // RO, UART3 interrupt identification +#define R8_UART3_LSR (*((PUINT8V)0x40003C05)) // RO, UART3 line status +#define R32_UART3_FIFO (*((PUINT32V)0x40003C08)) // RW, UART3 data or FIFO port +#define R8_UART3_RBR (*((PUINT8V)0x40003C08)) // RO, UART3 receiver buffer, receiving byte +#define R8_UART3_THR (*((PUINT8V)0x40003C08)) // WO, UART3 transmitter holding, transmittal byte +#define R8_UART3_RFC (*((PUINT8V)0x40003C0A)) // RO, UART3 receiver FIFO count +#define R8_UART3_TFC (*((PUINT8V)0x40003C0B)) // RO, UART3 transmitter FIFO count +#define R32_UART3_SETUP (*((PUINT32V)0x40003C0C)) // RW, UART3 setup +#define R16_UART3_DL (*((PUINT16V)0x40003C0C)) // RW, UART3 divisor latch +#define R8_UART3_DLL (*((PUINT8V)0x40003C0C)) // RW, UART3 divisor latch LSB byte +// #define R8_UART3_DLM (*((PUINT8V)0x40003C0D)) // RW, UART3 divisor latch MSB byte +#define R8_UART3_DIV (*((PUINT8V)0x40003C0E)) // RW, UART3 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART register address offset and bit define */ +#define UART_FIFO_SIZE 8 // UART FIFO size (depth) +#define UART_RECV_RDY_SZ 7 // the max FIFO trigger level for UART receiver data available +#define BA_UART0 ((PUINT8V)0x40003000) // point UART0 base address +#define BA_UART1 ((PUINT8V)0x40003400) // point UART1 base address +#define BA_UART2 ((PUINT8V)0x40003800) // point UART2 base address +#define BA_UART3 ((PUINT8V)0x40003C00) // point UART3 base address +#define UART_MCR 0 +#define RB_MCR_DTR 0x01 // RW, UART0 control DTR +#define RB_MCR_RTS 0x02 // RW, UART0 control RTS +#define RB_MCR_OUT1 0x04 // RW, UART0 control OUT1 +#define RB_MCR_OUT2 0x08 // RW, UART control OUT2 +#define RB_MCR_INT_OE 0x08 // RW, UART interrupt output enable +#define RB_MCR_LOOP 0x10 // RW, UART0 enable local loop back +#define RB_MCR_AU_FLOW_EN 0x20 // RW, UART0 enable autoflow control +#define RB_MCR_TNOW 0x40 // RW, UART0 enable TNOW output on DTR pin +#define RB_MCR_HALF 0x80 // RW, UART0 enable half-duplex +#define UART_IER 1 +#define RB_IER_RECV_RDY 0x01 // RW, UART interrupt enable for receiver data ready +#define RB_IER_THR_EMPTY 0x02 // RW, UART interrupt enable for THR empty +#define RB_IER_LINE_STAT 0x04 // RW, UART interrupt enable for receiver line status +#define RB_IER_MODEM_CHG 0x08 // RW, UART0 interrupt enable for modem status change +#define RB_IER_DTR_EN 0x10 // RW, UART0 DTR/TNOW output pin enable +#define RB_IER_RTS_EN 0x20 // RW, UART0 RTS output pin enable +#define RB_IER_TXD_EN 0x40 // RW, UART TXD pin enable +#define RB_IER_RESET 0x80 // WZ, UART software reset control, high action, auto clear +#define UART_FCR 2 +#define RB_FCR_FIFO_EN 0x01 // RW, UART FIFO enable +#define RB_FCR_RX_FIFO_CLR 0x02 // WZ, clear UART receiver FIFO, high action, auto clear +#define RB_FCR_TX_FIFO_CLR 0x04 // WZ, clear UART transmitter FIFO, high action, auto clear +#define RB_FCR_FIFO_TRIG 0xC0 // RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes +#define UART_LCR 3 +#define RB_LCR_WORD_SZ 0x03 // RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit +#define RB_LCR_STOP_BIT 0x04 // RW, UART stop bit length: 0-1bit, 1-2bit +#define RB_LCR_PAR_EN 0x08 // RW, UART parity enable +#define RB_LCR_PAR_MOD 0x30 // RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space +#define RB_LCR_BREAK_EN 0x40 // RW, UART break control enable +#define RB_LCR_DLAB 0x80 // RW, UART reserved bit +#define RB_LCR_GP_BIT 0x80 // RW, UART general purpose bit +#define UART_IIR 4 +#define RB_IIR_NO_INT 0x01 // RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt +#define RB_IIR_INT_MASK 0x0F // RO, UART interrupt flag bit mask +#define RB_IIR_FIFO_ID 0xC0 // RO, UART FIFO enabled flag +#define UART_LSR 5 +#define RB_LSR_DATA_RDY 0x01 // RO, UART receiver fifo data ready status +#define RB_LSR_OVER_ERR 0x02 // RZ, UART receiver overrun error +#define RB_LSR_PAR_ERR 0x04 // RZ, UART receiver parity error +#define RB_LSR_FRAME_ERR 0x08 // RZ, UART receiver frame error +#define RB_LSR_BREAK_ERR 0x10 // RZ, UART receiver break error +#define RB_LSR_TX_FIFO_EMP 0x20 // RO, UART transmitter fifo empty status +#define RB_LSR_TX_ALL_EMP 0x40 // RO, UART transmitter all empty status +#define RB_LSR_ERR_RX_FIFO 0x80 // RO, indicate error in UART receiver fifo +#define UART_MSR 6 +#define RB_MSR_CTS_CHG 0x01 // RZ, UART0 CTS changed status, high action +#define RB_MSR_DSR_CHG 0x02 // RZ, UART0 DSR changed status, high action +//#define RB_MSR_RI_CHG 0x04 // RZ, UART0 RI changed status, high action +//#define RB_MSR_DCD_CHG 0x08 // RZ, UART0 DCD changed status, high action +#define RB_MSR_CTS 0x10 // RO, UART0 CTS action status +#define RB_MSR_DSR 0x20 // RO, UART0 DSR action status +//#define RB_MSR_RI 0x40 // RO, UART0 RI action status +//#define RB_MSR_DCD 0x80 // RO, UART0 DCD action status +#define UART_RBR 8 +#define UART_THR 8 +#define UART_RFC 0x0A +#define UART_TFC 0x0B +#define UART_DLL 0x0C +// #define UART_DLM 0x0D +#define UART_DIV 0x0E +#define UART_ADR 0x0F + +/* UART interrupt identification values for IIR bits 3:0 */ +#define UART_II_SLV_ADDR 0x0E // RO, UART0 slave address match +#define UART_II_LINE_STAT 0x06 // RO, UART interrupt by receiver line status +#define UART_II_RECV_RDY 0x04 // RO, UART interrupt by receiver data available +#define UART_II_RECV_TOUT 0x0C // RO, UART interrupt by receiver fifo timeout +#define UART_II_THR_EMPTY 0x02 // RO, UART interrupt by THR empty +#define UART_II_MODEM_CHG 0x00 // RO, UART0 interrupt by modem status change +#define UART_II_NO_INTER 0x01 // RO, no UART interrupt is pending + +/* SPI0 register */ +#define R32_SPI0_CONTROL (*((PUINT32V)0x40004000)) // RW, SPI0 control +#define R8_SPI0_CTRL_MOD (*((PUINT8V)0x40004000)) // RW, SPI0 mode control +#define R8_SPI0_CTRL_CFG (*((PUINT8V)0x40004001)) // RW, SPI0 configuration control +#define R8_SPI0_INTER_EN (*((PUINT8V)0x40004002)) // RW, SPI0 interrupt enable +#define R8_SPI0_CLOCK_DIV (*((PUINT8V)0x40004003)) // RW, SPI0 master clock divisor +#define R8_SPI0_SLAVE_PRE (*((PUINT8V)0x40004003)) // RW, SPI0 slave preset value +#define R32_SPI0_STATUS (*((PUINT32V)0x40004004)) // RW, SPI0 status +#define R8_SPI0_BUFFER (*((PUINT8V)0x40004004)) // RO, SPI0 data buffer +#define R8_SPI0_RUN_FLAG (*((PUINT8V)0x40004005)) // RO, SPI0 work flag +#define R8_SPI0_INT_FLAG (*((PUINT8V)0x40004006)) // RW1, SPI0 interrupt flag +#define R8_SPI0_FIFO_COUNT (*((PUINT8V)0x40004007)) // RO, SPI0 FIFO count status +#define R32_SPI0_TOTAL_CNT (*((PUINT32V)0x4000400C)) // RW, SPI0 total byte count, only low 12 bit +#define R16_SPI0_TOTAL_CNT (*((PUINT16V)0x4000400C)) // RW, SPI0 total byte count, only low 12 bit +#define R32_SPI0_FIFO (*((PUINT32V)0x40004010)) // RW, SPI0 FIFO register +#define R8_SPI0_FIFO (*((PUINT8V)0x40004010)) // RO/WO, SPI0 FIFO register +#define R8_SPI0_FIFO_COUNT1 (*((PUINT8V)0x40004013)) // RO, SPI0 FIFO count status +#define R32_SPI0_DMA_NOW (*((PUINT32V)0x40004014)) // RW, SPI0 DMA current address +#define R16_SPI0_DMA_NOW (*((PUINT16V)0x40004014)) // RW, SPI0 DMA current address +#define R32_SPI0_DMA_BEG (*((PUINT32V)0x40004018)) // RW, SPI0 DMA begin address +#define R16_SPI0_DMA_BEG (*((PUINT16V)0x40004018)) // RW, SPI0 DMA begin address +#define R32_SPI0_DMA_END (*((PUINT32V)0x4000401C)) // RW, SPI0 DMA end address +#define R16_SPI0_DMA_END (*((PUINT16V)0x4000401C)) // RW, SPI0 DMA end address + +/* SPI register address offset and bit define */ +#define SPI_FIFO_SIZE 8 // SPI FIFO size (depth) +#define BA_SPI0 ((PUINT8V)0x40004000) // point SPI0 base address +#define SPI_CTRL_MOD 0 +#define RB_SPI_MODE_SLAVE 0x01 // RW, SPI0 slave mode: 0=master/host, 1=slave/device +#define RB_SPI_ALL_CLEAR 0x02 // RW, force clear SPI FIFO and count +#define RB_SPI_2WIRE_MOD 0x04 // RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX) +#define RB_SPI_MST_SCK_MOD 0x08 // RW, SPI master clock mode: 0=mode 0, 1=mode 3 +#define RB_SPI_SLV_CMD_MOD 0x08 // RW, SPI0 slave command mode: 0=byte stream, 1=first byte command +#define RB_SPI_FIFO_DIR 0x10 // RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode) +#define RB_SPI_SCK_OE 0x20 // RW, SPI SCK output enable +#define RB_SPI_MOSI_OE 0x40 // RW, SPI MOSI output enable +#define RB_SPI_MISO_OE 0x80 // RW, SPI MISO output enable +#define SPI_CTRL_CFG 1 +#define RB_SPI_DMA_ENABLE 0x01 // RW, SPI0 DMA enable +#define RB_SPI_DMA_LOOP 0x04 // RW, SPI0 DMA address loop enable +#define RB_SPI_AUTO_IF 0x10 // RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag +#define RB_SPI_BIT_ORDER 0x20 // RW, SPI bit data order: 0=MSB first, 1=LSB first +#define RB_SPI_MST_DLY_EN 0x40 // RW, SPI master input delay enable +#define SPI_INTER_EN 2 +#define RB_SPI_IE_CNT_END 0x01 // RW, enable interrupt for SPI total byte count end +#define RB_SPI_IE_BYTE_END 0x02 // RW, enable interrupt for SPI byte exchanged +#define RB_SPI_IE_FIFO_HF 0x04 // RW, enable interrupt for SPI FIFO half +#define RB_SPI_IE_DMA_END 0x08 // RW, enable interrupt for SPI0 DMA completion +#define RB_SPI_IE_FIFO_OV 0x10 // RW, enable interrupt for SPI0 FIFO overflow +#define RB_SPI_IE_FST_BYTE 0x80 // RW, enable interrupt for SPI0 slave mode first byte received +#define SPI_CLOCK_DIV 3 +#define SPI_SLAVE_PRESET 3 +#define SPI_BUFFER 4 +#define SPI_RUN_FLAG 5 +#define RB_SPI_SLV_CMD_ACT 0x10 // RO, SPI0 slave first byte / command flag +#define RB_SPI_FIFO_READY 0x20 // RO, SPI FIFO ready status +#define RB_SPI_SLV_CS_LOAD 0x40 // RO, SPI0 slave chip-select loading status +#define RB_SPI_SLV_SELECT 0x80 // RO, SPI0 slave selection status +#define SPI_INT_FLAG 6 +#define RB_SPI_IF_CNT_END 0x01 // RW1, interrupt flag for SPI total byte count end +#define RB_SPI_IF_BYTE_END 0x02 // RW1, interrupt flag for SPI byte exchanged +#define RB_SPI_IF_FIFO_HF 0x04 // RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : <4bytes) +#define RB_SPI_IF_DMA_END 0x08 // RW1, interrupt flag for SPI0 DMA completion +#define RB_SPI_IF_FIFO_OV 0x10 // RW1, interrupt flag for SPI0 FIFO overflow +#define RB_SPI_FREE 0x40 // RO, current SPI free status +#define RB_SPI_IF_FST_BYTE 0x80 // RW1, interrupt flag for SPI0 slave mode first byte received +#define SPI_FIFO_COUNT 7 +#define SPI_TOTAL_CNT 0x0C +#define SPI_FIFO 0x10 +#define SPI_DMA_NOW 0x14 +#define SPI_DMA_BEG 0x18 +#define SPI_DMA_END 0x1C + +/* I2C register */ +#define R16_I2C_CTRL1 (*((PUINT16V)0x40004800)) // RW, I2C control 1 +#define R16_I2C_CTRL2 (*((PUINT16V)0x40004804)) // RW, I2C control 2 +#define R16_I2C_OADDR1 (*((PUINT16V)0x40004808)) // RW, I2C own address register 1 +#define R16_I2C_OADDR2 (*((PUINT16V)0x4000480C)) // RW, I2C own address register 2 +#define R16_I2C_DATAR (*((PUINT16V)0x40004810)) // RW, I2C data register +#define R16_I2C_STAR1 (*((PUINT16V)0x40004814)) // R0, I2C stauts register 1 +#define R16_I2C_STAR2 (*((PUINT16V)0x40004818)) // R0, I2C status register 2 +// #define R8_I2C_PEC (*((PUINT8V) 0x40004819)) // R0, I2C Packet error checking register +#define R16_I2C_CKCFGR (*((PUINT16V)0x4000481C)) // RW, I2C clock control register +#define R16_I2C_RTR (*((PUINT16V)0x40004820)) // RW, I2C trise register + +/* I2C register address offset and bit define */ +#define BA_I2C ((PUINT8V)0x40004800) // point I2C base address +#define I2C_CTRL1 0 +#define RB_I2C_PE 0x0001 // RW, Peripheral enable +#define RB_I2C_SMBUS 0x0002 // RW, SMBUS mode: 0=I2C mode, 1=SMBUS mode +#define RB_I2C_SMBTYPE 0x0008 // RW, SMBus type: 0=Device, 1=Host +#define RB_I2C_EBARP 0x0010 // RW, ARP enable +#define RB_I2C_ENPEC 0x0020 // RW, PEC ebable +#define RB_I2C_ENGC 0x0040 // RW, General call enable +#define RB_I2C_NOSTRETCH 0x0080 // RW, Clock stretching disable (Slave mode) +#define RB_I2C_START 0x0100 // RW, Start generation: master mode: 0=no start, 1=repeated start; slave mode: 0=no start, 1=start at bus free +#define RB_I2C_STOP 0x0200 // RW, Stop generation: master mode: 0=no stop, 1=stop after the current byte transfer or after the current Start condition is sent; slave mode: 0=no stop, 1=Release the SCL and SDA lines after the current byte transfer +#define RB_I2C_ACK 0x0400 // RW, Acknowledge enable +#define RB_I2C_POS 0x0800 // RW, Acknowledge/PEC Position (for data reception) +#define RB_I2C_PEC 0x1000 // RW, Packet error checking: 0=No PEC transfer, 1=PEC transfer (in Tx or Rx mode) +#define RB_I2C_ALERT 0x2000 // RW, SMBus alert: 0=Releases SMBA pin high, 1=Drives SMBA pin low. +#define RB_I2C_SWRST 0x8000 // RW, Software reset +#define I2C_CTRL2 4 +#define RB_I2C_FREQ 0x003F // RW, Peripheral clock frequency, The minimum allowed frequency is 2 MHz,the maximum frequency is 36 MHz +#define RB_I2C_ITERREN 0x0100 // RW, Error interrupt enable +#define RB_I2C_ITEVTEN 0x0200 // RW, Event interrupt enable +#define RB_I2C_ITBUFEN 0x0400 // RW, Buffer interrupt enable +#define I2C_OADDR1 8 +#define RB_I2C_ADD0 0x0001 // RW, bit0 of address in 10-bit addressing mode +#define RB_I2C_ADD7_1 0x00FE // RW, bit[7:1] of address +#define RB_I2C_ADD9_8 0x0300 // RW, bit[9:8] of address in 10-bit addressing mode +#define RB_I2C_ADDMODE 0x8000 // RW, Addressing mode (slave mode): 0=7-bit slave address, 1=10-bit slave address +#define I2C_OADDR2 12 +#define RB_I2C_ENDUAL 0x0001 // RW, Dual addressing mode enable +#define RB_I2C_ADD2 0x00FE // RW, bit[7:1] of address2 +#define I2C_DATAR 16 +#define I2C_STAR1 20 +#define RB_I2C_SB 0x0001 // RW0, Start bit flag (Master mode) +#define RB_I2C_ADDR 0x0002 // RW0, Address sent (master mode)/matched (slave mode) flag +#define RB_I2C_BTF 0x0004 // RO, Byte transfer finished flag +#define RB_I2C_ADD10 0x0008 // RO, 10-bit header sent flag (Master mode) +#define RB_I2C_STOPF 0x0010 // RO, Stop detection flag (slave mode) +#define RB_I2C_RxNE 0x0040 // RO, Data register not empty flag (receivers) +#define RB_I2C_TxE 0x0080 // RO, Data register empty flag (transmitters) +#define RB_I2C_BERR 0x0100 // RW0, Bus error flag +#define RB_I2C_ARLO 0x0200 // RW0, Arbitration lost flag (master mode) +#define RB_I2C_AF 0x0400 // RW0, Acknowledge failure flag +#define RB_I2C_OVR 0x0800 // RW0, Overrun/Underrun flag +#define RB_I2C_PECERR 0x1000 // RW0, PEC Error flag in reception +#define RB_I2C_TIMEOUT 0x4000 // RW0, Timeout or Tlow error flag +#define RB_I2C_SMBALERT 0x8000 // RW0, SMBus alert flag +#define I2C_STAR2 24 +#define RB_I2C_MSL 0x0001 // RO, Mode statu: 0=Slave mode, 1=Master mode +#define RB_I2C_BUSY 0x0002 // RO, Bus busy flag +#define RB_I2C_TRA 0x0004 // RO, Trans flag: 0=data bytes received, 1=data bytes transmitted +#define RB_I2C_GENCALL 0x0010 // RO, General call address (Slave mode) received flag +#define RB_I2C_SMBDEFAULT 0x0020 // RO, SMBus device default address (Slave mode) received flag +#define RB_I2C_SMBHOST 0x0040 // RO, SMBus host header (Slave mode) received flag +#define RB_I2C_DUALF 0x0080 // RO, Dual flag (Slave mode): 0=Received address matched with OAR1, 1=Received address matched with OAR2 +#define RB_I2C_PECX 0xFF00 // RO, Packet error checking register +#define I2C_CKCFGR 28 +#define RB_I2C_CCR 0x0FFF // RW, Controls the SCL clock in Fm/Sm mode (Master mode) +#define RB_I2C_DUTY 0x4000 // RW, Fm mode duty cycle: 0=L/H=2, 1=L/H=16/9 +#define RB_I2C_F_S 0x8000 // RW, I2C master mode selection: 0=standard mode, 1=fast mode +#define I2C_RTR 32 +#define RB_I2C_TRISE 0x003F // RW, Maximum rise time in Fm/Sm mode (Master mode) + +/* PWM4/5/6/7/8/9/10/11 register */ +#define R32_PWM_CONTROL (*((PUINT32V)0x40005000)) // RW, PWM control +#define R8_PWM_OUT_EN (*((PUINT8V)0x40005000)) // RW, PWM output enable control +#define R8_PWM_POLAR (*((PUINT8V)0x40005001)) // RW, PWM output polarity control +#define R8_PWM_CONFIG (*((PUINT8V)0x40005002)) // RW, PWM configuration +#define R8_PWM_CLOCK_DIV (*((PUINT8V)0x40005003)) // RW, PWM clock divisor +#define R32_PWM4_7_DATA (*((PUINT32V)0x40005004)) // RW, PWM4-7 data holding +#define R16_PWM4_DATA (*((PUINT16V)0x40005004)) // RW, PWM4 16bit data holding +#define R16_PWM5_DATA (*((PUINT16V)0x40005006)) // RW, PWM5 16bit data holding +#define R8_PWM4_DATA (*((PUINT8V)0x40005004)) // RW, PWM4 data holding +#define R8_PWM5_DATA (*((PUINT8V)0x40005005)) // RW, PWM5 data holding +#define R8_PWM6_DATA (*((PUINT8V)0x40005006)) // RW, PWM6 data holding +#define R8_PWM7_DATA (*((PUINT8V)0x40005007)) // RW, PWM7 data holding +#define R32_PWM8_11_DATA (*((PUINT32V)0x40005008)) // RW, PWM8-11 data holding +#define R16_PWM6_DATA (*((PUINT16V)0x40005008)) // RW, PWM6 16bit data holding +#define R16_PWM7_DATA (*((PUINT16V)0x4000500A)) // RW, PWM7 16bit data holding +#define R8_PWM8_DATA (*((PUINT8V)0x40005008)) // RW, PWM8 data holding +#define R8_PWM9_DATA (*((PUINT8V)0x40005009)) // RW, PWM9 data holding +#define R8_PWM10_DATA (*((PUINT8V)0x4000500A)) // RW, PWM10 data holding +#define R8_PWM11_DATA (*((PUINT8V)0x4000500B)) // RW, PWM11 data holding +#define R8_PWM_INT_CTRL (*((PUINT32V)0x4000500C)) // RW, PWM interrupt control +#define RB_PWM_IE_CYC 0x01 // RW, enable interrupt for PWM cycle end +#define RB_PWM_CYC_PRE 0x02 // RW, select PWM cycle interrupt point: 0=after count 0xFE (0x7E for 7 bits mode...), 1=after count 0xF0 (0x70 for 7 bits mode...) +#define RB_PWM_IF_CYC 0x80 // RW1, interrupt flag for PWM cycle end +#define R32_PWM_REG_DATA8 (*((PUINT32V)0x40005010)) // RW, PWM8-9 data register +#define R16_PWM8_DATA (*((PUINT16V)0x40005010)) // RW, PWM8 16bit data holding +#define R16_PWM9_DATA (*((PUINT16V)0x40005012)) // RW, PWM9 16bit data holding +#define R32_PWM_REG_CYCLE (*((PUINT32V)0x40005014)) // RW, PWM cycle value + +/* PWM4/5/6/7/8/9/10/11 register address offset and bit define */ +#define BA_PWMX ((PUINT8V)0x40005000) // point PWM4/5/6/7/8/9/10/11 base address +#define PWM_OUT_EN 0 +#define RB_PWM4_OUT_EN 0x01 // RW, PWM4 output enable +#define RB_PWM5_OUT_EN 0x02 // RW, PWM5 output enable +#define RB_PWM6_OUT_EN 0x04 // RW, PWM6 output enable +#define RB_PWM7_OUT_EN 0x08 // RW, PWM7 output enable +#define RB_PWM8_OUT_EN 0x10 // RW, PWM8 output enable +#define RB_PWM9_OUT_EN 0x20 // RW, PWM9 output enable +#define RB_PWM10_OUT_EN 0x40 // RW, PWM10 output enable +#define RB_PWM11_OUT_EN 0x80 // RW, PWM11 output enable +#define PWM_POLAR 1 +#define RB_PWM4_POLAR 0x01 // RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM5_POLAR 0x02 // RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM6_POLAR 0x04 // RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM7_POLAR 0x08 // RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM8_POLAR 0x10 // RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM9_POLAR 0x20 // RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM10_POLAR 0x40 // RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM11_POLAR 0x80 // RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action +#define PWM_CONFIG 2 +#define RB_PWM_CYCLE_SEL 0x01 // RW, PWM cycle selection: 0=256/128/64/32 clocks, 1=255/127/63/31 clocks +#define RB_PWM_STAG_ST 0x02 // RO, PWM stagger cycle status +#define RB_PWM_CYC_MOD 0x0C // RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=16 bits data +#define RB_PWM4_5_STAG_EN 0x10 // RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output +#define RB_PWM6_7_STAG_EN 0x20 // RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output +#define RB_PWM8_9_STAG_EN 0x40 // RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output +#define RB_PWM10_11_STAG_EN 0x80 // RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output +#define PWM_CLOCK_DIV 3 +#define PWM4_DATA_HOLD 4 +#define PWM5_DATA_HOLD 5 +#define PWM6_DATA_HOLD 6 +#define PWM7_DATA_HOLD 7 +#define PWM8_DATA_HOLD 8 +#define PWM9_DATA_HOLD 9 +#define PWM10_DATA_HOLD 10 +#define PWM11_DATA_HOLD 11 + +/* LCD register */ +#define R32_LCD_CMD (*((PUINT32V)(0x40006000))) +#define RB_LCD_SYS_EN 0x01 // RW, LCD digital system enable +#define RB_LCD_ON 0x02 // RW, LCD analog system enable +#define RB_LCD_BIAS 0x04 // RW, LCD bias select: 0=1/2 bias, 1=1/3 bias +#define RB_LCD_DUTY 0x18 // RW, LCD duty select: 00=1/2 duty, 01=1/3 duty, 10=1/4 duty +#define RB_LCD_SCAN_CLK 0x60 // RW, LCD scan clock select: 00=256Hz, 01=512Hz, 10=1KHz, 11=128Hz +#define RB_LCD_VLCD_SEL 0x80 // RW, LCD drive voltage：0=VIO33*100%(3.3V),1=VIO33*76%(2.5V) +#define RB_LCD_SEG0_7_EN 0xFF00 // RW, SEG0-SEG7 enable +#define RB_LCD_SEG8_15_EN 0xFF0000 // RW, SEG8-SEG15 enable +#define RB_LCD_SEG16_19_EN 0xF000000 // RW, SEG16-SEG19 enable + +#define R32_LCD_RAM0 (*((PUINT32V)(0x40006004))) // RW, LCD driver data0, address 0-3 +#define R32_LCD_RAM1 (*((PUINT32V)(0x40006008))) // RW, LCD driver data1, address 4-7 +#define R32_LCD_RAM2 (*((PUINT32V)(0x4000600C))) // RW, LCD driver data2, address 8-12 + +/* Address space define */ +#define BA_CODE ((PUINT32)0x00000000) // point code base address +#define SZ_CODE 0x00080000 // code size +#define BA_SFR ((PUINT32)0x40000000) // point SFR base address +#define SZ_SFR 0x00010000 // SFR size +#define BA_RAM ((PUINT32)0x20000000) // point RAM base address +#define SZ_RAM 0x00006800 // RAM size + +/* Special Program Space */ +#define DATA_FLASH_ADDR 0x70000 // start address of Data-Flash +#define DATA_FLASH_SIZE 0x8000 // size of Data-Flash +#define BOOT_LOAD_ADDR 0x78000 // start address of boot loader program +#define BOOT_LOAD_SIZE 0x6000 // size of boot loader program +#define BOOT_LOAD_CFG 0x7E000 // start address of configuration information for boot loader program +#define ROM_CFG_ADDR 0x7F000 // chip configuration information address + +/*----- Reference Information --------------------------------------------*/ +#define ID_CH592 0x92 // chip ID +#define ID_CH591 0x91 // chip ID + +/* Interrupt routine address and interrupt number */ +#define INT_ID_TMR0 16 // interrupt number for Timer0 +#define INT_ID_GPIO_A 17 // interrupt number for GPIO port A +#define INT_ID_GPIO_B 18 // interrupt number for GPIO port B +#define INT_ID_SPI0 19 // interrupt number for SPI0 +#define INT_ID_BLEB 20 // interrupt number for BLEBB +#define INT_ID_BLEL 21 // interrupt number for BLELLE +#define INT_ID_USB 22 // interrupt number for USB +#define INT_ID_TMR1 24 // interrupt number for Timer1 +#define INT_ID_TMR2 25 // interrupt number for Timer2 +#define INT_ID_UART0 26 // interrupt number for UART0 +#define INT_ID_UART1 27 // interrupt number for UART1 +#define INT_ID_RTC 28 // interrupt number for RTC +#define INT_ID_ADC 29 // interrupt number for ADC and TouchKey +#define INT_ID_I2C 30 // interrupt number for I2C +#define INT_ID_PWMX 31 // interrupt number for PWM4~11 +#define INT_ID_TMR3 32 // interrupt number for Timer3 +#define INT_ID_UART2 33 // interrupt number for UART2 +#define INT_ID_UART3 34 // interrupt number for UART3 +#define INT_ID_WDOG_BAT 35 // interrupt number for Watch-Dog timer and Battery low voltage +#define INT_VEC_ENTRY_SZ 4 // size of each interrupt vector entry +#define INT_ADDR_TMR0 (INT_ID_TMR0*INT_VEC_ENTRY_SZ) // interrupt vector address for Timer0 +#define INT_ADDR_GPIO_A (INT_ID_GPIO_A*INT_VEC_ENTRY_SZ) // interrupt vector address for GPIO port A +#define INT_ADDR_GPIO_B (INT_ID_GPIO_B*INT_VEC_ENTRY_SZ) // interrupt vector address for GPIO port B +#define INT_ADDR_SPI0 (INT_ID_SPI0*INT_VEC_ENTRY_SZ) // interrupt vector address for SPI0 +#define INT_ADDR_BLEB (INT_ID_BLEB*INT_VEC_ENTRY_SZ) // interrupt vector address for BLEBB +#define INT_ADDR_BLEL (INT_ID_BLEL*INT_VEC_ENTRY_SZ) // interrupt vector address for BLELLE +#define INT_ADDR_USB (INT_ID_USB*INT_VEC_ENTRY_SZ) // interrupt vector address for USB +#define INT_ADDR_TMR1 (INT_ID_TMR1*INT_VEC_ENTRY_SZ) // interrupt vector address for Timer1 +#define INT_ADDR_TMR2 (INT_ID_TMR2*INT_VEC_ENTRY_SZ) // interrupt vector address for Timer2 +#define INT_ADDR_UART0 (INT_ID_UART0*INT_VEC_ENTRY_SZ) // interrupt vector address for UART0 +#define INT_ADDR_UART1 (INT_ID_UART1*INT_VEC_ENTRY_SZ) // interrupt vector address for UART1 +#define INT_ADDR_RTC (INT_ID_RTC*INT_VEC_ENTRY_SZ) // interrupt vector address for RTC +#define INT_ADDR_ADC (INT_ID_ADC*INT_VEC_ENTRY_SZ) // interrupt vector address for ADC and TouchKey +#define INT_ADDR_I2C (INT_ID_I2C*INT_VEC_ENTRY_SZ) // interrupt vector address for I2C +#define INT_ADDR_PWMX (INT_ID_PWMX*INT_VEC_ENTRY_SZ) // interrupt vector address for PWM4~11 +#define INT_ADDR_TMR3 (INT_ID_TMR3*INT_VEC_ENTRY_SZ) // interrupt vector address for Timer3 +#define INT_ADDR_UART2 (INT_ID_UART2*INT_VEC_ENTRY_SZ) // interrupt vector address for UART2 +#define INT_ADDR_UART3 (INT_ID_UART3*INT_VEC_ENTRY_SZ) // interrupt vector address for UART3 +#define INT_ADDR_WDOG_BAT (INT_ID_WDOG_BAT*INT_VEC_ENTRY_SZ) // interrupt vector address for Watch-Dog timer and Battery low voltage + +#ifndef TABLE_IRQN +#define __PFIC_PRIO_BITS 2 /*!< uses 8 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +typedef enum IRQn +{ + Reset_IRQn = 1, + NMI_IRQn = 2, /*!< Non Maskable Interrupt */ + EXC_IRQn = 3, /*!< Exceptions Interrupt */ + SysTick_IRQn = 12, /*!< System timer Interrupt */ + SWI_IRQn = 14, /*!< software Interrupt */ + TMR0_IRQn = 16, + GPIO_A_IRQn = 17, + GPIO_B_IRQn = 18, + SPI0_IRQn = 19, + BLEB_IRQn = 20, + BLEL_IRQn = 21, + USB_IRQn = 22, + TMR1_IRQn = 24, + TMR2_IRQn = 25, + UART0_IRQn = 26, + UART1_IRQn = 27, + RTC_IRQn = 28, + ADC_IRQn = 29, + I2C_IRQn = 30, + PWMX_IRQn = 31, + TMR3_IRQn = 32, + UART2_IRQn = 33, + UART3_IRQn = 34, + WDOG_BAT_IRQn = 35 +} IRQn_Type; +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // __CH592SFR_H__ + + +#ifndef __CH592USBSFR_H__ +#define __CH592USBSFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* usb addresses +// USB: +8000H - 83FFH */ +#define USB_BASE_ADDR (0x40008000) +#define BA_USB ((PUINT8V)0x40008000) // point USB base address + +/* USB */ +#define R32_USB_CONTROL (*((PUINT32V)0x40008000)) // USB control & interrupt enable & device address +#define R8_USB_CTRL (*((PUINT8V)0x40008000)) // USB base control +#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit +#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit +#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control +// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need RB_PIN_USB_DP_PU=1 or need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +#define R8_UDEV_CTRL (*((PUINT8V)0x40008001)) // USB device physical prot control +#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define RB_UD_GP_BIT 0x02 // general purpose bit +#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +#define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control +#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define R8_USB_INT_EN (*((PUINT8V)0x40008002)) // USB interrupt enable +#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define RB_MOD_1_WIRE 0x20 // enable single wire mode +#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode + +#define R8_USB_DEV_AD (*((PUINT8V)0x40008003)) // USB device address +#define RB_UDA_GP_BIT 0x80 // general purpose bit +#define MASK_USB_ADDR 0x7F // bit mask for USB device address + +#define R32_USB_STATUS (*((PUINT32V)0x40008004)) // USB miscellaneous status & interrupt flag & interrupt status +#define R8_USB_MIS_ST (*((PUINT8V)0x40008005)) // USB miscellaneous status +#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +#define R8_USB_INT_FG (*((PUINT8V)0x40008006)) // USB interrupt flag +#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +#define R8_USB_INT_ST (*((PUINT8V)0x40008007)) // USB interrupt status +#define RB_UIS_SETUP_ACT 0x80 // RO, indicate SETUP token & 8 bytes setup request received for USB device mode +#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode, keep last status during SETUP token, clear RB_UIF_TRANSFER ( RB_UIF_TRANSFER from 1 to 0 ) to set free +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: free +#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +#define R8_USB_RX_LEN (*((PUINT8V)0x40008008)) // USB receiving length +#define R32_USB_BUF_MODE (*((PUINT32V)0x4000800C)) // USB endpoint buffer mode +#define R8_UEP4_1_MOD (*((PUINT8V)0x4000800C)) // endpoint 4/1 mode +#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +#define R8_UEP2_3_MOD (*((PUINT8V)0x4000800D)) // endpoint 2/3 mode +#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +#define R8_UEP567_MOD (*((PUINT8V)0x4000800E)) // endpoint 5/6/7 mode +#define RB_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT) +#define RB_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN) +#define RB_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT) +#define RB_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN) +#define RB_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT) +#define RB_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN) +// bUEPn_RX_EN & bUEPn_TX_EN: USB endpoint 5/6/7 buffer mode, buffer start address is UEPn_DMA +// 0 0: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (OUT endpoint) +// 0 1: 64 bytes buffer for transmittal (IN endpoint) +// 1 1: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes + +#define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode +#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +#define R16_UEP0_DMA (*((PUINT16V)0x40008010)) // endpoint 0 DMA buffer address +#define R16_UEP1_DMA (*((PUINT16V)0x40008014)) // endpoint 1 DMA buffer address +#define R16_UEP2_DMA (*((PUINT16V)0x40008018)) // endpoint 2 DMA buffer address +#define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer address +#define R16_UEP3_DMA (*((PUINT16V)0x4000801C)) // endpoint 3 DMA buffer address +#define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer address +#define R16_UEP5_DMA (*((PUINT16V)0x40008054)) // endpoint 5 DMA buffer address +#define R16_UEP6_DMA (*((PUINT16V)0x40008058)) // endpoint 6 DMA buffer address +#define R16_UEP7_DMA (*((PUINT16V)0x4000805C)) // endpoint 7 DMA buffer address +#define R32_USB_EP0_CTRL (*((PUINT32V)0x40008020)) // endpoint 0 control & transmittal length +#define R8_UEP0_T_LEN (*((PUINT8V)0x40008020)) // endpoint 0 transmittal length +#define R8_UEP0_CTRL (*((PUINT8V)0x40008022)) // endpoint 0 control +#define R32_USB_EP1_CTRL (*((PUINT32V)0x40008024)) // endpoint 1 control & transmittal length +#define R8_UEP1_T_LEN (*((PUINT8V)0x40008024)) // endpoint 1 transmittal length +#define R8_UEP1_CTRL (*((PUINT8V)0x40008026)) // endpoint 1 control +#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) +#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) +#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK 0x00 +#define UEP_R_RES_TOUT 0x04 +#define UEP_R_RES_NAK 0x08 +#define UEP_R_RES_STALL 0x0C +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_TOUT 0x01 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +#define R8_UH_SETUP R8_UEP1_CTRL // host aux setup +#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable + +#define R32_USB_EP2_CTRL (*((PUINT32V)0x40008028)) // endpoint 2 control & transmittal length +#define R8_UEP2_T_LEN (*((PUINT8V)0x40008028)) // endpoint 2 transmittal length +#define R8_UEP2_CTRL (*((PUINT8V)0x4000802A)) // endpoint 2 control + +#define R8_UH_EP_PID R8_UEP2_T_LEN // host endpoint and PID +#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer +#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer + +#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control +#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define R32_USB_EP3_CTRL (*((PUINT32V)0x4000802c)) // endpoint 3 control & transmittal length +#define R8_UEP3_T_LEN (*((PUINT8V)0x4000802c)) // endpoint 3 transmittal length +#define R8_UEP3_CTRL (*((PUINT8V)0x4000802e)) // endpoint 3 control +#define R8_UH_TX_LEN R8_UEP3_T_LEN // host transmittal endpoint transmittal length + +#define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control +#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#define R32_USB_EP4_CTRL (*((PUINT32V)0x40008030)) // endpoint 4 control & transmittal length +#define R8_UEP4_T_LEN (*((PUINT8V)0x40008030)) // endpoint 4 transmittal length +#define R8_UEP4_CTRL (*((PUINT8V)0x40008032)) // endpoint 4 control + +#define R32_USB_EP5_CTRL (*((PUINT32V)0x40008064)) // endpoint 5 control & transmittal length +#define R8_UEP5_T_LEN (*((PUINT8V)0x40008064)) // endpoint 5 transmittal length +#define R8_UEP5_CTRL (*((PUINT8V)0x40008066)) // endpoint 5 control + +#define R32_USB_EP6_CTRL (*((PUINT32V)0x40008068)) // endpoint 6 control & transmittal length +#define R8_UEP6_T_LEN (*((PUINT8V)0x40008068)) // endpoint 6 transmittal length +#define R8_UEP6_CTRL (*((PUINT8V)0x4000806A)) // endpoint 6 control + +#define R32_USB_EP7_CTRL (*((PUINT32V)0x4000806C)) // endpoint 7 control & transmittal length +#define R8_UEP7_T_LEN (*((PUINT8V)0x4000806C)) // endpoint 7 transmittal length +#define R8_UEP7_CTRL (*((PUINT8V)0x4000806E)) // endpoint 7 control + +#ifdef __cplusplus +} +#endif + +#endif //__CH592USBSFR_H__ + + +#ifndef __USB_TYPE__ +#define __USB_TYPE__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*----- USB constant and structure define --------------------------------*/ + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 /* reserved PID */ +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit define for USB request type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ +#define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ +#define USB_REQ_TYP_READ 0x80 /* control read, device to host */ +#define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ +#define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#endif + +/* USB request type for hub class request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub class feature selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB descriptor type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB device class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB endpoint type and attributes */ +#ifndef USB_ENDP_TYPE_MASK +#define USB_ENDP_DIR_MASK 0x80 +#define USB_ENDP_ADDR_MASK 0x0F +#define USB_ENDP_TYPE_MASK 0x03 +#define USB_ENDP_TYPE_CTRL 0x00 +#define USB_ENDP_TYPE_ISOCH 0x01 +#define USB_ENDP_TYPE_BULK 0x02 +#define USB_ENDP_TYPE_INTER 0x03 +#endif + +#ifndef USB_DEVICE_ADDR +#define USB_DEVICE_ADDR 0x02 /* 默认的USB设备地址 */ +#endif +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ +#endif +#ifndef MAX_PACKET_SIZE +#define MAX_PACKET_SIZE 64 /* maximum packet size */ +#endif +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F /* 命令块CBW的总长度 */ +#define USB_BO_CSW_SIZE 0x0D /* 命令状态块CSW的总长度 */ +#endif +#ifndef USB_BO_CBW_SIG +#define USB_BO_CBW_SIG 0x43425355 /* 命令块CBW识别标志'USBC' */ +#define USB_BO_CSW_SIG 0x53425355 /* 命令状态块CSW识别标志'USBS' */ +#endif + +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif + +typedef struct __PACKED _USB_SETUP_REQ { + UINT8 bRequestType; + UINT8 bRequest; + UINT16 wValue; + UINT16 wIndex; + UINT16 wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +typedef struct __PACKED _USB_DEVICE_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 bcdUSB; + UINT8 bDeviceClass; + UINT8 bDeviceSubClass; + UINT8 bDeviceProtocol; + UINT8 bMaxPacketSize0; + UINT16 idVendor; + UINT16 idProduct; + UINT16 bcdDevice; + UINT8 iManufacturer; + UINT8 iProduct; + UINT8 iSerialNumber; + UINT8 bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +typedef struct __PACKED _USB_CONFIG_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 wTotalLength; + UINT8 bNumInterfaces; + UINT8 bConfigurationValue; + UINT8 iConfiguration; + UINT8 bmAttributes; + UINT8 MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +typedef struct __PACKED _USB_INTERF_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bInterfaceNumber; + UINT8 bAlternateSetting; + UINT8 bNumEndpoints; + UINT8 bInterfaceClass; + UINT8 bInterfaceSubClass; + UINT8 bInterfaceProtocol; + UINT8 iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +typedef struct __PACKED _USB_ENDPOINT_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bEndpointAddress; + UINT8 bmAttributes; + UINT16 wMaxPacketSize; + UINT8 bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +typedef struct __PACKED _USB_CONFIG_DESCR_LONG { + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[1]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +typedef USB_CFG_DESCR_LONG *PXUSB_CFG_DESCR_LONG; + +typedef struct __PACKED _USB_HUB_DESCR { + UINT8 bDescLength; + UINT8 bDescriptorType; + UINT8 bNbrPorts; + UINT8 wHubCharacteristicsL; + UINT8 wHubCharacteristicsH; + UINT8 bPwrOn2PwrGood; + UINT8 bHubContrCurrent; + UINT8 DeviceRemovable; + UINT8 PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +typedef USB_HUB_DESCR *PXUSB_HUB_DESCR; + +typedef struct __PACKED _USB_HID_DESCR { + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 bcdHID; + UINT8 bCountryCode; + UINT8 bNumDescriptors; + UINT8 bDescriptorTypeX; + UINT8 wDescriptorLengthL; + UINT8 wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +typedef USB_HID_DESCR *PXUSB_HID_DESCR; + +typedef struct __PACKED _UDISK_BOC_CBW { /* command of BulkOnly USB-FlashDisk */ + UINT32 mCBW_Sig; + UINT32 mCBW_Tag; + UINT32 mCBW_DataLen; /* uppest byte of data length, always is 0 */ + UINT8 mCBW_Flag; /* transfer direction and etc. */ + UINT8 mCBW_LUN; + UINT8 mCBW_CB_Len; /* length of command block */ + UINT8 mCBW_CB_Buf[16]; /* command block buffer */ +} UDISK_BOC_CBW, *PUDISK_BOC_CBW; + +typedef UDISK_BOC_CBW *PXUDISK_BOC_CBW; + +typedef struct __PACKED _UDISK_BOC_CSW { /* status of BulkOnly USB-FlashDisk */ + UINT32 mCSW_Sig; + UINT32 mCSW_Tag; + UINT32 mCSW_Residue; /* return: remainder bytes */ + UINT8 mCSW_Status; /* return: result status */ +} UDISK_BOC_CSW, *PUDISK_BOC_CSW; + +typedef UDISK_BOC_CSW *PXUDISK_BOC_CSW; + +#ifdef __cplusplus +} +#endif + +#endif // __USB_TYPE__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_adc.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_adc.h new file mode 100644 index 0000000..4e5ef64 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_adc.h @@ -0,0 +1,283 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_adc.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_ADC_H__ +#define __CH59x_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ROM_CFG_TMP_25C 0x7F014 + +/** + * @brief adc single channel define + */ +typedef enum +{ + CH_EXTIN_0 = 0, // ADC 外部模拟通道 0 + CH_EXTIN_1, // ADC 外部模拟通道 1 + CH_EXTIN_2, // ADC 外部模拟通道 2 + CH_EXTIN_3, // ADC 外部模拟通道 3 + CH_EXTIN_4, // ADC 外部模拟通道 4 + CH_EXTIN_5, // ADC 外部模拟通道 5 + CH_EXTIN_6, // ADC 外部模拟通道 6 + CH_EXTIN_7, // ADC 外部模拟通道 7 + CH_EXTIN_8, // ADC 外部模拟通道 8 + CH_EXTIN_9, // ADC 外部模拟通道 9 + CH_EXTIN_10, // ADC 外部模拟通道 10 + CH_EXTIN_11, // ADC 外部模拟通道 11 + CH_EXTIN_12, // ADC 外部模拟通道 12 + CH_EXTIN_13, // ADC 外部模拟通道 13 + + CH_INTE_VBAT = 14, // ADC 内部电池检测通道 + CH_INTE_VTEMP = 15, // ADC 内部温度传感器检测通道 + +} ADC_SingleChannelTypeDef; + +/** + * @brief adc differential channel define + */ +typedef enum +{ + CH_DIFF_0_2 = 0, // ADC 差分通道 #0-#2 + CH_DIFF_1_3, // ADC 差分通道 #1-#3 + +} ADC_DiffChannelTypeDef; + +/** + * @brief adc sampling clock + */ +typedef enum +{ + SampleFreq_3_2 = 0, // 3.2M 采样频率 + SampleFreq_8, // 8M 采样频率 + SampleFreq_5_33, // 5.33M 采样频率 + SampleFreq_4, // 4M 采样频率 +} ADC_SampClkTypeDef; + +/** + * @brief adc signal PGA + */ +typedef enum +{ + ADC_PGA_1_4 = 0, // -12dB, 1/4倍 + ADC_PGA_1_2, // -6dB, 1/2倍 + ADC_PGA_0, // 0dB, 1倍，无增益 + ADC_PGA_2, // 6dB, 2倍 + ADC_PGA_2_ = 0x10, // 6dB, 2倍 + ADC_PGA_4, // 12dB, 4倍 + ADC_PGA_8, // 18dB, 8倍 + ADC_PGA_16, // 24dB, 16倍 +} ADC_SignalPGATypeDef; + +/** + * @brief Configuration DMA mode + */ +typedef enum +{ + ADC_Mode_Single = 0, // 单次模式 + ADC_Mode_LOOP, // 循环模式 +} ADC_DMAModeTypeDef; + + +/** + * @brief 设置 ADC 采样通道 + * + * @param d - refer to ADC_SingleChannelTypeDef + */ +#define ADC_ChannelCfg(d) (R8_ADC_CHANNEL = d) + +/** + * @brief 设置 ADC 采样时钟 + * + * @param d - refer to ADC_SampClkTypeDef + */ +#define ADC_SampClkCfg(d) (R8_ADC_CFG = R8_ADC_CFG & (~RB_ADC_CLK_DIV) | (d << 6)) + +/** + * @brief 设置 ADC 信号增益 + * + * @param d - refer to ADC_SignalPGATypeDef + */ +#define ADC_PGACfg(d) (R8_ADC_CFG = R8_ADC_CFG & (~RB_ADC_PGA_GAIN) | (d << 4)) + +/** + * @brief 设置内部温度传感器校准值 + * + * @param d - 校准值 + */ +#define ADC_TempCalibCfg(d) (R8_TEM_SENSOR = R8_TEM_SENSOR & (~RB_TEM_SEN_CALIB) | d) + +/** + * @brief 外部信号单通道采样初始化 + * + * @param sp - refer to ADC_SampClkTypeDef + * @param ga - refer to ADC_SignalPGATypeDef + */ +void ADC_ExtSingleChSampInit(ADC_SampClkTypeDef sp, ADC_SignalPGATypeDef ga); + +/** + * @brief 外部信号差分通道采样初始化 + * + * @param sp - refer to ADC_SampClkTypeDef + * @param ga - refer to ADC_SignalPGATypeDef + */ +void ADC_ExtDiffChSampInit(ADC_SampClkTypeDef sp, ADC_SignalPGATypeDef ga); + +/** + * @brief 触摸按键通道采样初始化 + */ +void TouchKey_ChSampInit(void); + +/** + * @brief 关闭TouchKey电源 + */ +#define TouchKey_DisableTSPower() (R8_TKEY_CFG &= ~RB_TKEY_PWR_ON) + +/** + * @brief 内置温度传感器采样初始化 + */ +void ADC_InterTSSampInit(void); + +/** + * @brief 关闭温度传感器电源 + */ +#define ADC_DisableTSPower() (R8_TEM_SENSOR = 0) + +/** + * @brief 内置电池电压采样初始化 + */ +void ADC_InterBATSampInit(void); + +/** + * @brief ADC执行单次转换 + * + * @return ADC转换后的数据 + */ +uint16_t ADC_ExcutSingleConver(void); + +/** + * @brief 采样数据粗调,获取偏差值,必须先配置ADC后调用此函数获取校准值 + * + * @return 偏差 + */ +signed short ADC_DataCalib_Rough(void); + +/** + * @brief TouchKey转换后数据 + * + * @param charg - Touchkey充电时间,5bits有效, t=charg*Tadc + * @param disch - Touchkey放电时间,3bits有效, t=disch*Tadc + * + * @return 当前TouchKey等效数据 + */ +uint16_t TouchKey_ExcutSingleConver(uint8_t charg, uint8_t disch); + +/** + * @brief 设置连续 ADC的周期 + * + * @param cycle - 单位为 16个系统时钟 + */ +void ADC_AutoConverCycle(uint8_t cycle); + +/** + * @brief 配置DMA功能 + * + * @param s - 是否打开DMA功能 + * @param startAddr - DMA 起始地址 + * @param endAddr - DMA 结束地址 + * @param m - 配置DMA模式 + */ +void ADC_DMACfg(uint8_t s, uint32_t startAddr, uint32_t endAddr, ADC_DMAModeTypeDef m); + +/** + * @brief Convert ADC value to temperature(Celsius) + * + * @param adc_val - adc value + * + * @return temperature (Celsius) + */ +int adc_to_temperature_celsius(uint16_t adc_val); + +/** + * @brief 获取ADC转换值 + * + * @return ADC转换值 + */ +#define ADC_ReadConverValue() (R16_ADC_DATA) + +/** + * @brief ADC执行单次转换 + */ +#define ADC_StartUp() (R8_ADC_CONVERT = RB_ADC_START) + +/** + * @brief 获取ADC中断状态 + */ +#define ADC_GetITStatus() (R8_ADC_INT_FLAG & RB_ADC_IF_EOC) + +/** + * @brief 清除ADC中断标志 + */ +#define ADC_ClearITFlag() (R8_ADC_CONVERT = 0) + +/** + * @brief 获取ADC DMA完成状态 + */ +#define ADC_GetDMAStatus() (R8_ADC_DMA_IF & RB_ADC_IF_DMA_END) + +/** + * @brief 清除ADC DMA完成标志 + */ +#define ADC_ClearDMAFlag() (R8_ADC_DMA_IF |= RB_ADC_IF_DMA_END) + +/** + * @brief 开启定时间隔自动连续 ADC + */ +#define ADC_StartAutoDMA() (R8_ADC_CTRL_DMA |= RB_ADC_AUTO_EN) + +/** + * @brief 停止定时间隔自动连续 ADC + */ +#define ADC_StopAutoDMA() (R8_ADC_CTRL_DMA &= ~RB_ADC_AUTO_EN) + +/** + * @brief 开启连续转换 ADC + */ +#define ADC_StartContDMA() (R8_ADC_CTRL_DMA |= RB_ADC_CONT_EN) + +/** + * @brief 停止连续转换 ADC + */ +#define ADC_StopContDMA() (R8_ADC_CTRL_DMA &= ~RB_ADC_CONT_EN) + +/** + * @brief 获取TouchKey中断状态 + */ +#define TouchKey_GetITStatus() (R8_ADC_INT_FLAG & RB_ADC_IF_EOC) + +/** + * @brief 清除TouchKey中断标志 + */ +#define TouchKey_ClearITFlag() (R8_TKEY_CTRL |= RB_TKEY_PWR_ON) + +/** + * @brief 关闭ADC电源 + */ +#define ADC_DisablePower() (R8_ADC_CFG &= ~RB_ADC_POWER_ON) + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_ADC_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_clk.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_clk.h new file mode 100644 index 0000000..d70593f --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_clk.h @@ -0,0 +1,291 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_clk.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_CLK_H__ +#define __CH59x_CLK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief 系统主频定义 + */ +typedef enum +{ + CLK_SOURCE_LSI = 0x00, + CLK_SOURCE_LSE, + + CLK_SOURCE_HSE_16MHz = 0x22, + CLK_SOURCE_HSE_8MHz = 0x24, + CLK_SOURCE_HSE_6_4MHz = 0x25, + CLK_SOURCE_HSE_4MHz = 0x28, + + CLK_SOURCE_PLL_80MHz = 0x46, // untested, max allowed per datasheet; possibly req'd for BLE + CLK_SOURCE_PLL_60MHz = 0x48, + CLK_SOURCE_PLL_48MHz = (0x40 | 10), + CLK_SOURCE_PLL_32MHz = (0x40 | 15), + CLK_SOURCE_PLL_24MHz = (0x40 | 20), +} SYS_CLKTypeDef; + +/** + * @brief 32K时钟选择 + */ +typedef enum +{ + Clk32K_LSI = 0, + Clk32K_LSE, + +} LClk32KTypeDef; + +/** + * @brief 32M晶振电流挡位 + */ +typedef enum +{ + HSE_RCur_75 = 0, + HSE_RCur_100, + HSE_RCur_125, + HSE_RCur_150 + +} HSECurrentTypeDef; + +/** + * @brief 32M晶振内部电容挡位 + */ +typedef enum +{ + HSECap_10p = 0, + HSECap_12p, + HSECap_14p, + HSECap_16p, + HSECap_18p, + HSECap_20p, + HSECap_22p, + HSECap_24p + +} HSECapTypeDef; + +/** + * @brief 32K晶振电流挡位 + */ +typedef enum +{ + LSE_RCur_70 = 0, + LSE_RCur_100, + LSE_RCur_140, + LSE_RCur_200 + +} LSECurrentTypeDef; + +/** + * @brief 32K晶振内部电容挡位 + */ +typedef enum +{ + LSECap_2p = 0, + LSECap_13p, + LSECap_14p, + LSECap_15p, + LSECap_16p, + LSECap_17p, + LSECap_18p, + LSECap_19p, + LSECap_20p, + LSECap_21p, + LSECap_22p, + LSECap_23p, + LSECap_24p, + LSECap_25p, + LSECap_26p, + LSECap_27p + +} LSECapTypeDef; + +#define RTC_MAX_COUNT 0xA8C00000 + +#define MAX_DAY 0x00004000 +#define MAX_2_SEC 0x0000A8C0 +//#define MAX_SEC 0x545FFFFF + +#define BEGYEAR 2020 +#define IsLeapYear(yr) (!((yr) % 400) || (((yr) % 100) && !((yr) % 4))) +#define YearLength(yr) (IsLeapYear(yr) ? 366 : 365) +#define monthLength(lpyr, mon) (((mon) == 1) ? (28 + (lpyr)) : (((mon) > 6) ? (((mon) & 1) ? 31 : 30) : (((mon) & 1) ? 30 : 31))) + +/** + * @brief rtc timer mode period define + */ +typedef enum +{ + Period_0_125_S = 0, // 0.125s 周期 + Period_0_25_S, // 0.25s 周期 + Period_0_5_S, // 0.5s 周期 + Period_1_S, // 1s 周期 + Period_2_S, // 2s 周期 + Period_4_S, // 4s 周期 + Period_8_S, // 8s 周期 + Period_16_S, // 16s 周期 +} RTC_TMRCycTypeDef; + +/** + * @brief rtc interrupt event define + */ +typedef enum +{ + RTC_TRIG_EVENT = 0, // RTC 触发事件 + RTC_TMR_EVENT, // RTC 周期定时事件 + +} RTC_EVENTTypeDef; + +/** + * @brief rtc interrupt event define + */ +typedef enum +{ + RTC_TRIG_MODE = 0, // RTC 触发模式 + RTC_TMR_MODE, // RTC 周期定时模式 + +} RTC_MODETypeDef; + +typedef enum +{ + /* 校准精度越高，耗时越长 */ + Level_32 = 3, // 用时 1.2ms 1000ppm (32M 主频) 1100ppm (60M 主频) + Level_64, // 用时 2.2ms 800ppm (32M 主频) 1000ppm (60M 主频) + Level_128, // 用时 4.2ms 600ppm (32M 主频) 800ppm (60M 主频) + +} Cali_LevelTypeDef; + +/** + * @brief 32K 低频时钟来源 + * + * @param hc - 选择32K使用内部还是外部 + */ +void LClk32K_Select(LClk32KTypeDef hc); + +/** + * @brief HSE晶体 偏置电流配置 + * + * @param c - 75%,100%,125%,150% + */ +void HSECFG_Current(HSECurrentTypeDef c); + +/** + * @brief HSE晶体 负载电容配置 + * + * @param c - refer to HSECapTypeDef + */ +void HSECFG_Capacitance(HSECapTypeDef c); + +/** + * @brief LSE晶体 偏置电流配置 + * + * @param c - 70%,100%,140%,200% + */ +void LSECFG_Current(LSECurrentTypeDef c); + +/** + * @brief LSE晶体 负载电容配置 + * + * @param c - refer to LSECapTypeDef + */ +void LSECFG_Capacitance(LSECapTypeDef c); + +void Calibration_LSI(Cali_LevelTypeDef cali_Lv); /* 用主频校准内部32K时钟 */ + +/** + * @brief RTC时钟初始化当前时间 + * + * @param y - 配置年，MAX_Y = BEGYEAR + 44 + * @param mon - 配置月，MAX_MON = 12 + * @param d - 配置日，MAX_D = 31 + * @param h - 配置小时，MAX_H = 23 + * @param m - 配置分钟，MAX_M = 59 + * @param s - 配置秒，MAX_S = 59 + */ +void RTC_InitTime(uint16_t y, uint16_t mon, uint16_t d, uint16_t h, uint16_t m, uint16_t s); + +/** + * @brief 获取当前时间 + * + * @param py - 获取到的年，MAX_Y = BEGYEAR + 44 + * @param pmon - 获取到的月，MAX_MON = 12 + * @param pd - 获取到的日，MAX_D = 31 + * @param ph - 获取到的小时，MAX_H = 23 + * @param pm - 获取到的分钟，MAX_M = 59 + * @param ps - 获取到的秒，MAX_S = 59 + */ +void RTC_GetTime(uint16_t *py, uint16_t *pmon, uint16_t *pd, uint16_t *ph, uint16_t *pm, uint16_t *ps); + +/** + * @brief 基于LSE/LSI时钟，配置当前RTC 周期数 + * + * @param cyc - 配置周期计数初值，MAX_CYC = 0xA8BFFFFF = 2831155199 + */ +void RTC_SetCycle32k(uint32_t cyc); + +/** + * @brief 基于LSE/LSI时钟，获取当前RTC 周期数 + * + * @return 当前周期数，MAX_CYC = 0xA8BFFFFF = 2831155199 + */ +uint32_t RTC_GetCycle32k(void); + +/** + * @brief RTC定时模式配置（注意定时基准固定为32768Hz） + * + * @param t - refer to RTC_TMRCycTypeDef + */ +void RTC_TRIGFunCfg(uint32_t cyc); + +/** + * @brief RTC定时模式配置（注意定时基准固定为32768Hz） + * + * @param t - refer to RTC_TMRCycTypeDef + */ +void RTC_TMRFunCfg(RTC_TMRCycTypeDef t); + +/** + * @brief RTC 模式功能关闭 + * + * @param m - 需要关闭的当前模式 + */ +void RTC_ModeFunDisable(RTC_MODETypeDef m); + +/** + * @brief 获取RTC中断标志 + * + * @param f - refer to RTC_EVENTTypeDef + * + * @return 中断标志状态 + */ +uint8_t RTC_GetITFlag(RTC_EVENTTypeDef f); + +/** + * @brief 清除RTC中断标志 + * + * @param f - refer to RTC_EVENTTypeDef + */ +void RTC_ClearITFlag(RTC_EVENTTypeDef f); + +/** + * @brief 32K 低频时钟电源配置 + */ +void LClk32K_Cfg(LClk32KTypeDef hc, FunctionalState s); + + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_CLK_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_common.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_common.h new file mode 100644 index 0000000..7cc2a53 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_common.h @@ -0,0 +1,102 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_common.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + + +#ifndef __CH59x_COMM_H__ +#define __CH59x_COMM_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifndef NULL +#define NULL 0 +#endif +#define ALL 0xFFFF + +#ifndef __HIGH_CODE +#define __HIGH_CODE __attribute__((section(".highcode"))) +#endif + +#ifndef __INTERRUPT +#ifdef INT_SOFT +#define __INTERRUPT __attribute__((interrupt())) +#else +#define __INTERRUPT __attribute__((interrupt("WCH-Interrupt-fast"))) +#endif +#endif + +#define Debug_UART0 0 +#define Debug_UART1 1 +#define Debug_UART2 2 +#define Debug_UART3 3 + +#ifdef DEBUG +#include +#endif + +/** + * @brief 系统主频时钟（Hz） + */ +#ifndef FREQ_SYS +#define FREQ_SYS 60000000 +#endif + +#ifndef SAFEOPERATE +#define SAFEOPERATE __nop();__nop() +#endif + +/** + * @brief 32K时钟（Hz） + */ +#ifdef CLK_OSC32K +#if ( CLK_OSC32K == 1 ) +#define CAB_LSIFQ 32000 +#else +#define CAB_LSIFQ 32768 +#endif +#else +#define CAB_LSIFQ 32000 +#endif + +#include +#include +#include "CH592SFR.h" +#include "core_riscv.h" +#include "CH59x_clk.h" +#include "CH59x_uart.h" +#include "CH59x_gpio.h" +#include "CH59x_i2c.h" +#include "CH59x_flash.h" +#include "CH59x_pwr.h" +#include "CH59x_pwm.h" +#include "CH59x_adc.h" +#include "CH59x_sys.h" +#include "CH59x_timer.h" +#include "CH59x_spi.h" +#include "CH59x_usbdev.h" +#include "CH59x_usbhost.h" +#include "ISP592.h" + + +#define DelayMs(x) mDelaymS(x) +#define DelayUs(x) mDelayuS(x) + +#define ROM_CFG_VERISON 0x7F010 + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_COMM_H__ + diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_flash.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_flash.h new file mode 100644 index 0000000..8cff417 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_flash.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_flash.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_FLASH_H__ +#define __CH59x_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief 读取Flash-ROM + * + * @param StartAddr - read address + * @param Buffer - read buffer + * @param len - read len + */ +void FLASH_ROM_READ(uint32_t StartAddr, void *Buffer, uint32_t len); + +UINT8 UserOptionByteConfig(FunctionalState RESET_EN, FunctionalState BOOT_PIN, FunctionalState UART_NO_KEY_EN, + uint32_t FLASHProt_Size); + +UINT8 UserOptionByteClose_SWD(void); + +void UserOptionByte_Active(void); + +void GET_UNIQUE_ID(uint8_t *Buffer); +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_FLASH_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_gpio.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_gpio.h new file mode 100644 index 0000000..22fd97a --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_gpio.h @@ -0,0 +1,274 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_gpio.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_GPIO_H__ +#define __CH59x_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO_pins_define + */ +#define GPIO_Pin_0 (0x00000001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 (0x00000002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 (0x00000004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 (0x00000008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 (0x00000010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 (0x00000020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 (0x00000040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 (0x00000080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 (0x00000100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 (0x00000200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 (0x00000400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 (0x00000800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 (0x00001000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 (0x00002000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 (0x00004000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 (0x00008000) /*!< Pin 15 selected */ +#define GPIO_Pin_16 (0x00010000) /*!< Pin 16 selected */ +#define GPIO_Pin_17 (0x00020000) /*!< Pin 17 selected */ +#define GPIO_Pin_18 (0x00040000) /*!< Pin 18 selected */ +#define GPIO_Pin_19 (0x00080000) /*!< Pin 19 selected */ +#define GPIO_Pin_20 (0x00100000) /*!< Pin 20 selected */ +#define GPIO_Pin_21 (0x00200000) /*!< Pin 21 selected */ +#define GPIO_Pin_22 (0x00400000) /*!< Pin 22 selected */ +#define GPIO_Pin_23 (0x00800000) /*!< Pin 23 selected */ +#define GPIO_Pin_All (0xFFFFFFFF) /*!< All pins selected */ + +/** + * @brief Configuration GPIO Mode + */ +typedef enum +{ + GPIO_ModeIN_Floating, //浮空输入 + GPIO_ModeIN_PU, //上拉输入 + GPIO_ModeIN_PD, //下拉输入 + GPIO_ModeOut_PP_5mA, //推挽输出最大5mA + GPIO_ModeOut_PP_20mA, //推挽输出最大20mA + +} GPIOModeTypeDef; + +/** + * @brief Configuration GPIO IT Mode + */ +typedef enum +{ + GPIO_ITMode_LowLevel, //低电平触发 + GPIO_ITMode_HighLevel, //高电平触发 + GPIO_ITMode_FallEdge, //下降沿触发 + GPIO_ITMode_RiseEdge, //上升沿触发 + +} GPIOITModeTpDef; + +/** + * @brief GPIOA端口引脚模式配置 + * + * @param pin - PA0-PA15 + * @param mode - 输入输出类型 + */ +void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); + +/** + * @brief GPIOB端口引脚模式配置 + * + * @param pin - PB0-PB23 + * @param mode - 输入输出类型 + */ +void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); + +/** + * @brief GPIOA端口引脚输出置低 + * + * @param pin - PA0-PA15 + */ +#define GPIOA_ResetBits(pin) (R32_PA_CLR |= pin) + +/** + * @brief GPIOA端口引脚输出置高 + * + * @param pin - PA0-PA15 + */ +#define GPIOA_SetBits(pin) (R32_PA_OUT |= pin) + +/** + * @brief GPIOB端口引脚输出置低 + * + * @param pin - PB0-PB23 + */ +#define GPIOB_ResetBits(pin) (R32_PB_CLR |= pin) + +/** + * @brief GPIOB端口引脚输出置高 + * + * @param pin - PB0-PB23 + */ +#define GPIOB_SetBits(pin) (R32_PB_OUT |= pin) + +/** + * @brief GPIOA端口引脚输出电平翻转 + * + * @param pin - PA0-PA15 + */ +#define GPIOA_InverseBits(pin) (R32_PA_OUT ^= pin) + +/** + * @brief GPIOB端口引脚输出电平翻转 + * + * @param pin - PB0-PB23 + */ +#define GPIOB_InverseBits(pin) (R32_PB_OUT ^= pin) + +/** + * @brief GPIOA端口32位数据返回，低16位有效 + * + * @return GPIOA端口32位数据 + */ +#define GPIOA_ReadPort() (R32_PA_PIN) + +/** + * @brief GPIOB端口32位数据返回，低24位有效 + * + * @return GPIOB端口32位数据 + */ +#define GPIOB_ReadPort() (R32_PB_PIN) + +/** + * @brief GPIOA端口引脚状态，0-引脚低电平，(!0)-引脚高电平 + * + * @param pin - PA0-PA15 + * + * @return GPIOA端口引脚状态 + */ +#define GPIOA_ReadPortPin(pin) (R32_PA_PIN & (pin)) + +/** + * @brief GPIOB端口引脚状态，0-引脚低电平，(!0)-引脚高电平 + * + * @param pin - PB0-PB23 + * + * @return GPIOB端口引脚状态 + */ +#define GPIOB_ReadPortPin(pin) (R32_PB_PIN & (pin)) + +/** + * @brief GPIOA引脚中断模式配置 + * + * @param pin - PA0-PA15 + * @param mode - 触发类型 + */ +void GPIOA_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); + +/** + * @brief GPIOB引脚中断模式配置 + * + * @param pin - PB0-PB23 + * @param mode - 触发类型 + */ +void GPIOB_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); + +/** + * @brief 读取GPIOA端口中断标志状态 + * + * @return GPIOA端口中断标志状态 + */ +#define GPIOA_ReadITFlagPort() (R16_PA_INT_IF) + +/** + * @brief 读取GPIOB端口中断标志状态 + * + * @return GPIOB端口中断标志状态 + */ +#define GPIOB_ReadITFlagPort() ((R16_PB_INT_IF & (~((GPIO_Pin_22 | GPIO_Pin_23) >> 14))) | ((R16_PB_INT_IF << 14) & (GPIO_Pin_22 | GPIO_Pin_23))) + +/** + * @brief 读取GPIOA端口引脚中断标志状态 + * + * @param pin - PA0-PA15 + * + * @return GPIOA端口引脚中断标志状态 + */ +#define GPIOA_ReadITFlagBit(pin) (R16_PA_INT_IF & (pin)) + +/** + * @brief 读取GPIOB端口引脚中断标志状态 + * + * @param pin - PB0-PB23 + * + * @return GPIOB端口引脚中断标志状态 + */ +#define GPIOB_ReadITFlagBit(pin) (R16_PB_INT_IF & ((pin) | (((pin) & (GPIO_Pin_22 | GPIO_Pin_23)) >> 14))) + +/** + * @brief 清除GPIOA端口引脚中断标志状态 + * + * @param pin - PA0-PA15 + */ +#define GPIOA_ClearITFlagBit(pin) (R16_PA_INT_IF = pin) + +/** + * @brief 清除GPIOB端口引脚中断标志状态 + * + * @param pin - PB0-PB23 + */ +#define GPIOB_ClearITFlagBit(pin) (R16_PB_INT_IF = ((pin) | (((pin) & (GPIO_Pin_22 | GPIO_Pin_23)) >> 14))) + +/** + * @brief 外设功能引脚映射 + * + * @param s - 是否使能映射 + * @param perph - RB_RF_ANT_SW_EN - RF antenna switch control output on PB16/PB17/PB18/PB19/PB20/PB21 + * RB_PIN_U0_INV - RXD0/RXD0_/TXD0/TXD0_ invert input/output + * RB_PIN_INTX - INTX: INT24/INT25 PB8/PB9 -> INT24_/INT25_ PB22/PB23 + * RB_PIN_MODEM - MODEM: PB1/PB5 -> PB14/PB15 + * RB_PIN_I2C - I2C: PB13/PB12 -> PB21/PB20 + * RB_PIN_PWMX - PWMX: PA12/PA13/PB4/PB6/PB7 -> PA6/PA7/PB1/PB2/PB3 + * RB_PIN_SPI0 - SPI0: PA12/PA13/PA14/PA15 -> PB12/PB13/PB14/PB15 + * RB_PIN_UART3 - UART3: PA4/PA5 -> PB20/PB21 + * RB_PIN_UART2 - UART2: PA6/PA7 -> PB22/PB23 + * RB_PIN_UART1 - UART1: PA8/PA9 -> PB12/PB13 + * RB_PIN_UART0 - UART0: PB4/PB7 -> PA15/PA14 + * RB_PIN_TMR3 - TMR2: PA9 -> PB23 + * RB_PIN_TMR2 - TMR2: PA11 -> PB11 + * RB_PIN_TMR1 - TMR1: PA10 -> PB10 + * RB_PIN_TMR0 - TMR0: PA9 -> PB23 + */ +void GPIOPinRemap(FunctionalState s, uint16_t perph); + +/** + * @brief 模拟外设GPIO引脚功能控制 + * + * @param s - 是否启用模拟外设功能 + * @param perph - RB_PIN_ADC8_9_IE - ADC/TKEY 9/8通道 + * RB_PIN_ADC6_7_IE - ADC/TKEY 7/6通道 + * RB_PIN_ADC10_IE - ADC/TKEY 10通道 + * RB_PIN_ADC11_IE - ADC/TKEY 11 通道 + * RB_PIN_USB2_DP_PU - USB2 U2D+引脚内部上拉电阻 + * RB_PIN_USB2_IE - USB2引脚 + * RB_PIN_USB_DP_PU - USB UD+引脚内部上拉电阻 + * RB_PIN_USB_IE - USB 引脚 + * RB_PIN_ADC0_IE - ADC/TKEY 0 通道 + * RB_PIN_ADC1_IE - ADC/TKEY 1 通道 + * RB_PIN_ADC12_IE - ADC/TKEY 12 通道 + * RB_PIN_ADC13_IE - ADC/TKEY 13 通道 + * RB_PIN_XT32K_IE - 32KHz晶振LSE引脚 + * RB_PIN_ADC2_3_IE - ADC/TKEY 2/3 通道 + * RB_PIN_ADC4_5_IE - ADC/TKEY 4/5 通道 + */ +void GPIOAGPPCfg(FunctionalState s, uint16_t perph); + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_GPIO_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_i2c.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_i2c.h new file mode 100644 index 0000000..dea5eb8 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_i2c.h @@ -0,0 +1,180 @@ + + +#ifndef __CH59x_I2C_H__ +#define __CH59x_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)RB_I2C_POS) +#define I2C_NACKPosition_Current ((uint16_t)~RB_I2C_POS) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)RB_I2C_POS) +#define I2C_PECPosition_Current ((uint16_t)~RB_I2C_POS) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)RB_I2C_ALERT) +#define I2C_SMBusAlert_High ((uint16_t)~RB_I2C_ALERT) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/* I2C_mode */ +typedef enum +{ + I2C_Mode_I2C = 0x0000, + I2C_Mode_SMBusDevice = 0x0002, + I2C_Mode_SMBusHost = 0x000A, +} I2C_ModeTypeDef; + +/* I2C_duty_cycle_in_fast_mode */ +typedef enum +{ + I2C_DutyCycle_16_9 = RB_I2C_DUTY, /* I2C fast mode Tlow/Thigh = 16/9 */ + I2C_DutyCycle_2 = 0x0000, /* I2C fast mode Tlow/Thigh = 2 */ +} I2C_DutyTypeDef; + +/* I2C_acknowledgement - Enables or disables the acknowledgement.*/ +typedef enum +{ + I2C_Ack_Enable = RB_I2C_ACK, + I2C_Ack_Disable = 0x0000, +} I2C_AckTypeDef; + +/* I2C_acknowledged_address - Specifies if 7-bit or 10-bit address is acknowledged. */ +typedef enum +{ + I2C_AckAddr_7bit = 0x4000, + I2C_AckAddr_10bit = 0xC000, +} I2C_AckAddrTypeDef; + +/* I2C_interrupts_definition */ +typedef enum +{ + I2C_IT_BUF = 0x0400, /* Buffer interrupt mask. */ + I2C_IT_EVT = 0x0200, /* Event interrupt mask. */ + I2C_IT_ERR = 0x0100, /* Error interrupt mask. */ +} I2C_ITTypeDef; + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +void I2C_Init(I2C_ModeTypeDef I2C_Mode, UINT32 I2C_ClockSpeed, I2C_DutyTypeDef I2C_DutyCycle, + I2C_AckTypeDef I2C_Ack, I2C_AckAddrTypeDef I2C_AckAddr, UINT16 I2C_OwnAddress1); +void I2C_Cmd(FunctionalState NewState); +void I2C_GenerateSTART(FunctionalState NewState); +void I2C_GenerateSTOP(FunctionalState NewState); +void I2C_AcknowledgeConfig(FunctionalState NewState); +void I2C_OwnAddress2Config(uint8_t Address); +void I2C_DualAddressCmd(FunctionalState NewState); +void I2C_GeneralCallCmd(FunctionalState NewState); +void I2C_ITConfig(I2C_ITTypeDef I2C_IT, FunctionalState NewState); +void I2C_SendData(uint8_t Data); + +uint8_t I2C_ReceiveData(void); + +void I2C_Send7bitAddress(uint8_t Address, uint8_t I2C_Direction); +void I2C_SoftwareResetCmd(FunctionalState NewState); +void I2C_NACKPositionConfig(uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(FunctionalState NewState); +void I2C_PECPositionConfig(uint16_t I2C_PECPosition); +void I2C_CalculatePEC(FunctionalState NewState); + +uint8_t I2C_GetPEC(void); + +void I2C_ARPCmd(FunctionalState NewState); +void I2C_StretchClockCmd(FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(uint16_t I2C_DutyCycle); + +/**************************************************************************************** + * I2C State Monitoring Functions + ****************************************************************************************/ +uint8_t I2C_CheckEvent(uint32_t I2C_EVENT); +uint32_t I2C_GetLastEvent(void); +FlagStatus I2C_GetFlagStatus(uint32_t I2C_FLAG); + +void I2C_ClearFlag(uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(uint32_t I2C_IT); +void I2C_ClearITPendingBit(uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_I2C_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_lcd.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_lcd.h new file mode 100644 index 0000000..500ad55 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_lcd.h @@ -0,0 +1,98 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_lcd.h + * Author : WCH + * Version : V1.0 + * Date : 2022/12/05 + * Description : + ******************************************************************************** + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + + +#ifndef __CH59x_LCD_H__ +#define __CH59x_LCD_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "CH592SFR.h" + +/** + * @brief Configuration LCD driver power + */ +typedef enum +{ + LCD_PS_3V3 = 0, // 3.3V 驱动 + LCD_PS_2V5, // 2.5V 驱动 +}LCDDrvPowerTypeDef; + +/** + * @brief Configuration LCD bias + */ +typedef enum +{ + LCD_1_2_Bias = 0, // 2级分压 + LCD_1_3_Bias, // 3级分压 +}LCDBiasTypeDef; + +/** + * @brief Configuration LCD duty + */ +typedef enum +{ + LCD_1_2_Duty = 0, // COM0-COM1 + LCD_1_3_Duty, // COM0-COM2 + LCD_1_4_Duty, // COM0-COM3 +}LCDDutyTypeDef; + +/** + * @brief Configuration LCD scan clk + */ +typedef enum +{ + LCD_CLK_256 = 0, // 256Hz + LCD_CLK_512, // 512Hz + LCD_CLK_1000, // 1KHz + LCD_CLK_128 // 128Hz +}LCDSCANCLKTypeDef; + +/* LCD段式屏驱动初始化配置 */ +void LCD_Init(LCDDutyTypeDef duty, LCDBiasTypeDef bias); + +#define LCD_PowerDown() (R32_LCD_CMD &= ~(RB_LCD_ON | RB_LCD_SYS_EN)) /* LCD功能模块关闭 */ +#define LCD_PowerOn() (R32_LCD_CMD |= (RB_LCD_ON | RB_LCD_SYS_EN)) /* LCD功能模块开启 */ + +// 输入值参考 LCDDrvPowerTypeDef +#define LCD_PowerCfg( d ) (R32_LCD_CMD = (R32_LCD_CMD & ~RB_LCD_VLCD_SEL) | (d<<7)) /* 配置LCD的 供电电压选择 */ +// 输入值参考 LCDSCANCLKTypeDef +#define LCD_ScanCLKCfg( d ) (R32_LCD_CMD = (R32_LCD_CMD & ~RB_LCD_SCAN_CLK) | (d<<5)) /* 配置LCD的 扫描时钟选择 */ +// 输入值参考 LCDDutyTypeDef +#define LCD_DutyCfg( d ) (R32_LCD_CMD = (R32_LCD_CMD & ~RB_LCD_DUTY) | (d<<3)) /* 配置LCD的 duty选择 */ +// 输入值参考 LCDBiasTypeDef +#define LCD_BiasCfg( d ) (R32_LCD_CMD = (R32_LCD_CMD & ~RB_LCD_BIAS) | (d<<2)) /* 配置LCD的 bias选择 */ + +#define LCD_WriteData0( d ) (R32_LCD_RAM0 = (R32_LCD_RAM0 & 0xffffff00) | ((UINT32)d)) /* 填充SEG0驱动数值 */ +#define LCD_WriteData1( d ) (R32_LCD_RAM0 = (R32_LCD_RAM0 & 0xffff00ff) | ((UINT32)d<<8)) /* 填充SEG1驱动数值 */ +#define LCD_WriteData2( d ) (R32_LCD_RAM0 = (R32_LCD_RAM0 & 0xff00ffff) | ((UINT32)d<<16)) /* 填充SEG2驱动数值 */ +#define LCD_WriteData3( d ) (R32_LCD_RAM0 = (R32_LCD_RAM0 & 0x00ffffff) | ((UINT32)d<<24)) /* 填充SEG3驱动数值 */ + +#define LCD_WriteData4( d ) (R32_LCD_RAM1 = (R32_LCD_RAM1 & 0xffffff00) | ((UINT32)d)) /* 填充SEG4驱动数值 */ +#define LCD_WriteData5( d ) (R32_LCD_RAM1 = (R32_LCD_RAM1 & 0xffff00ff) | ((UINT32)d<<8)) /* 填充SEG5驱动数值 */ +#define LCD_WriteData6( d ) (R32_LCD_RAM1 = (R32_LCD_RAM1 & 0xff00ffff) | ((UINT32)d<<16)) /* 填充SEG6驱动数值 */ +#define LCD_WriteData7( d ) (R32_LCD_RAM1 = (R32_LCD_RAM1 & 0x00ffffff) | ((UINT32)d<<24)) /* 填充SEG7驱动数值 */ + +#define LCD_WriteData8( d ) (R32_LCD_RAM2 = (R32_LCD_RAM2 & 0xffffff00) | ((UINT32)d)) /* 填充SEG8驱动数值 */ +#define LCD_WriteData9( d ) (R32_LCD_RAM2 = (R32_LCD_RAM2 & 0xffff00ff) | ((UINT32)d<<8)) /* 填充SEG9驱动数值 */ +#define LCD_WriteData10( d ) (R32_LCD_RAM2 = (R32_LCD_RAM2 & 0xff00ffff) | ((UINT32)d<<16)) /* 填充SEG10驱动数值 */ + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_LCD_H__ + diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_pwm.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_pwm.h new file mode 100644 index 0000000..4bf8997 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_pwm.h @@ -0,0 +1,167 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_pwm.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_PWM_H__ +#define __CH59x_PWM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief channel of PWM define + */ +#define CH_PWM4 0x01 // PWM4 通道 +#define CH_PWM5 0x02 // PWM5 通道 +#define CH_PWM6 0x04 // PWM6 通道 +#define CH_PWM7 0x08 // PWM7 通道 +#define CH_PWM8 0x10 // PWM8 通道 +#define CH_PWM9 0x20 // PWM9 通道 +#define CH_PWM10 0x40 // PWM10 通道 +#define CH_PWM11 0x80 // PWM11 通道 + +/** + * @brief channel of PWM define + */ +typedef enum +{ + High_Level = 0, // 默认低电平，高电平有效 + Low_Level, // 默认高电平，低电平有效 +} PWMX_PolarTypeDef; + +/** + * @brief Configuration PWM4_11 Cycle size + */ +typedef enum +{ + PWMX_Cycle_256 = 0, // 256 个PWMX周期 + PWMX_Cycle_255, // 255 个PWMX周期 + PWMX_Cycle_128, // 128 个PWMX周期 + PWMX_Cycle_127, // 127 个PWMX周期 + PWMX_Cycle_64, // 64 个PWMX周期 + PWMX_Cycle_63, // 63 个PWMX周期 +} PWMX_CycleTypeDef; + +/** + * @brief PWM4-PWM11 通道基准时钟配置 + * + * @param d - 通道基准时钟 = d*Tsys + */ +#define PWMX_CLKCfg(d) (R8_PWM_CLOCK_DIV = d) + +/** + * @brief PWM4-PWM11周期配置 + * + * @param cyc - refer to PWMX_CycleTypeDef + */ +void PWMX_CycleCfg(PWMX_CycleTypeDef cyc); + +/** + * @brief PWM4-PWM9 16位周期配置 + * + * @param cyc - 16位周期 + */ +void PWMX_16bit_CycleCfg(uint16_t cyc); + +/** + * @brief 设置 PWM4 有效数据脉宽 + * + * @param d - 有效数据脉宽 + */ +#define PWM4_ActDataWidth(d) (R8_PWM4_DATA = d) + +/** + * @brief 设置 PWM5 有效数据脉宽 + * + * @param d - 有效数据脉宽 + */ +#define PWM5_ActDataWidth(d) (R8_PWM5_DATA = d) + +/** + * @brief 设置 PWM6 有效数据脉宽 + * + * @param d - 有效数据脉宽 + */ +#define PWM6_ActDataWidth(d) (R8_PWM6_DATA = d) + +/** + * @brief 设置 PWM7 有效数据脉宽 + * + * @param d - 有效数据脉宽 + */ +#define PWM7_ActDataWidth(d) (R8_PWM7_DATA = d) + +/** + * @brief 设置 PWM8 有效数据脉宽 + * + * @param d - 有效数据脉宽 + */ +#define PWM8_ActDataWidth(d) (R8_PWM8_DATA = d) + +/** + * @brief 设置 PWM9 有效数据脉宽 + * + * @param d - 有效数据脉宽 + */ +#define PWM9_ActDataWidth(d) (R8_PWM9_DATA = d) + +/** + * @brief 设置 PWM10 有效数据脉宽 + * + * @param d - 有效数据脉宽 + */ +#define PWM10_ActDataWidth(d) (R8_PWM10_DATA = d) + +/** + * @brief 设置 PWM11 有效数据脉宽 + * + * @param d - 有效数据脉宽 + */ +#define PWM11_ActDataWidth(d) (R8_PWM11_DATA = d) + +/** + * @brief PWM4-PWM11通道输出波形配置 + * + * @param ch - select channel of pwm, refer to channel of PWM define + * @param da - effective pulse width + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param s - control pwmx function, ENABLE or DISABLE + */ +void PWMX_ACTOUT(uint8_t ch, uint8_t da, PWMX_PolarTypeDef pr, FunctionalState s); + +/** + * @brief PWM4-PWM9 通道16位输出波形配置 + * + * @param ch - select channel of pwm, refer to channel of PWM define + * @param da - effective pulse width + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param s - control pwmx function, ENABLE or DISABLE + */ +void PWMX_16bit_ACTOUT(uint8_t ch, uint16_t da, PWMX_PolarTypeDef pr, FunctionalState s); + +/** + * @brief PWM 交替输出模式配置 + * + * @param ch - select group of PWM alternate output + * RB_PWM4_5_STAG_EN - PWM4 和 PWM5 通道交替输出 + * RB_PWM6_7_STAG_EN - PWM6 和 PWM7 通道交替输出 + * RB_PWM8_9_STAG_EN - PWM8 和 PWM9 通道交替输出 + * RB_PWM10_11_STAG_EN - PWM10 和 PWM11 通道交替输出 + * @param s - control pwmx function, ENABLE or DISABLE + */ +void PWMX_AlterOutCfg(uint8_t ch, FunctionalState s); + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_PWM_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_pwr.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_pwr.h new file mode 100644 index 0000000..ce40668 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_pwr.h @@ -0,0 +1,169 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_pwr.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_PWR_H__ +#define __CH59x_PWR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ROM_CFG_ADR_HW 0x7F00C // config address for hardware config for LDO&OSC and etc + +/** + * @brief Peripher CLK control bit define + */ +#define BIT_SLP_CLK_TMR0 (0x00000001) /*!< TMR0 peripher clk bit */ +#define BIT_SLP_CLK_TMR1 (0x00000002) /*!< TMR1 peripher clk bit */ +#define BIT_SLP_CLK_TMR2 (0x00000004) /*!< TMR2 peripher clk bit */ +#define BIT_SLP_CLK_TMR3 (0x00000008) /*!< TMR3 peripher clk bit */ +#define BIT_SLP_CLK_UART0 (0x00000010) /*!< UART0 peripher clk bit */ +#define BIT_SLP_CLK_UART1 (0x00000020) /*!< UART1 peripher clk bit */ +#define BIT_SLP_CLK_UART2 (0x00000040) /*!< UART2 peripher clk bit */ +#define BIT_SLP_CLK_UART3 (0x00000080) /*!< UART3 peripher clk bit */ +#define BIT_SLP_CLK_SPI0 (0x00000100) /*!< SPI0 peripher clk bit */ +//#define BIT_SLP_CLK_SPI1 (0x00000200) /*!< SPI1 peripher clk bit */ +#define BIT_SLP_CLK_PWMX (0x00000400) /*!< PWMX peripher clk bit */ +//#define BIT_SLP_CLK_LCD (0x00000800) /*!< LCD peripher clk bit */ +#define BIT_SLP_CLK_USB (0x00001000) /*!< USB peripher clk bit */ +//#define BIT_SLP_CLK_ETH (0x00002000) /*!< ETH peripher clk bit */ +//#define BIT_SLP_CLK_LED (0x00004000) /*!< LED peripher clk bit */ +#define BIT_SLP_CLK_BLE (0x00008000) /*!< BLE peripher clk bit */ + +#define BIT_SLP_CLK_RAMX (0x10000000) /*!< main SRAM RAM16K peripher clk bit */ +#define BIT_SLP_CLK_RAM2K (0x20000000) /*!< RAM2K peripher clk bit */ +#define BIT_SLP_CLK_ALL (0x3000FFFF) /*!< All peripher clk bit */ + +/** + * @brief unit of controllable power supply + */ +#define UNIT_SYS_LSE RB_CLK_XT32K_PON // 外部32K 时钟振荡 +#define UNIT_SYS_LSI RB_CLK_INT32K_PON // 内部32K 时钟振荡 +#define UNIT_SYS_HSE RB_CLK_XT32M_PON // 外部32M 时钟振荡 +#define UNIT_SYS_PLL RB_CLK_PLL_PON // PLL 时钟振荡 + +/** + * @brief wakeup mode define + */ +typedef enum +{ + Short_Delay = 0, + Long_Delay, + +} WakeUP_ModeypeDef; + +/** + * @brief wakeup mode define + */ +typedef enum +{ + /* 下面等级将使用高精度监控，210uA消耗 */ + HALevel_1V9 = 0, // 1.7-1.9 + HALevel_2V1, // 1.9-2.1 + HALevel_2V3, // 2.1-2.3 + HALevel_2V5, // 2.3-2.5 + + /* 下面等级将使用低功耗监控，1uA消耗 */ + LPLevel_1V8 = 0x80, + LPLevel_1V9, + LPLevel_2V0, + LPLevel_2V1, + LPLevel_2V2, + LPLevel_2V3, + LPLevel_2V4, + LPLevel_2V5, + +} VolM_LevelypeDef; + +/** + * @brief 启用内部DC/DC电源，用于节约系统功耗 + * + * @param s - 是否打开DCDC电源 + */ +void PWR_DCDCCfg(FunctionalState s); + +/** + * @brief 可控单元模块的电源控制 + * + * @param s - 是否打开电源 + * @param unit - please refer to unit of controllable power supply + */ +void PWR_UnitModCfg(FunctionalState s, uint8_t unit); + +/** + * @brief 外设时钟控制位 + * + * @param s - 是否打开对应外设时钟 + * @param perph - please refer to Peripher CLK control bit define + */ +void PWR_PeriphClkCfg(FunctionalState s, uint16_t perph); + +/** + * @brief 睡眠唤醒源配置 + * + * @param s - 是否打开此外设睡眠唤醒功能 + * @param perph - 需要设置的唤醒源 + * RB_SLP_USB_WAKE - USB 为唤醒源 + * RB_SLP_RTC_WAKE - RTC 为唤醒源 + * RB_SLP_GPIO_WAKE - GPIO 为唤醒源 + * RB_SLP_BAT_WAKE - BAT 为唤醒源 + * @param mode - refer to WakeUP_ModeypeDef + */ +void PWR_PeriphWakeUpCfg(FunctionalState s, uint8_t perph, WakeUP_ModeypeDef mode); + +/** + * @brief 电源监控 + * + * @param s - 是否打开此功能 + * @param vl - refer to VolM_LevelypeDef + */ +void PowerMonitor(FunctionalState s, VolM_LevelypeDef vl); + +/** + * @brief 低功耗-Idle模式 + */ +void LowPower_Idle(void); + +/** + * @brief 低功耗-Halt模式，此低功耗切到HSI/5时钟运行，唤醒后需要用户自己重新选择系统时钟源 + */ +void LowPower_Halt(void); + +/** + * @brief 低功耗-Sleep模式，此低功耗切到HSI/5时钟运行，唤醒后需要用户自己重新选择系统时钟源 + * @note 注意调用此函数，DCDC功能强制关闭，唤醒后可以手动再次打开 + * + * @param rm - 供电模块选择 + * RB_PWR_RAM2K - 2K retention SRAM 供电 + * RB_PWR_RAM16K - 16K main SRAM 供电 + * RB_PWR_EXTEND - USB 和 BLE 单元保留区域供电 + * RB_PWR_XROM - FlashROM 供电 + * NULL - 以上单元都断电 + */ +void LowPower_Sleep(uint16_t rm); + +/** + * @brief 低功耗-Shutdown模式，此低功耗切到HSI/5时钟运行，唤醒后需要用户自己重新选择系统时钟源 + * @note 注意调用此函数，DCDC功能强制关闭，唤醒后可以手动再次打开 + * + * @param rm - 供电模块选择 + * RB_PWR_RAM2K - 2K retention SRAM 供电 + * RB_PWR_RAM16K - 16K main SRAM 供电 + * NULL - 以上单元都断电 + */ +void LowPower_Shutdown(uint16_t rm); + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_PWR_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_spi.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_spi.h new file mode 100644 index 0000000..a3ede16 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_spi.h @@ -0,0 +1,214 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_SPI.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_SPI_H__ +#define __CH59x_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief SPI0 interrupt bit define + */ +#define SPI0_IT_FST_BYTE RB_SPI_IE_FST_BYTE // 从机模式的首字节命令模式下，接收到首字节中断 +#define SPI0_IT_FIFO_OV RB_SPI_IE_FIFO_OV // FIFO 溢出 +#define SPI0_IT_DMA_END RB_SPI_IE_DMA_END // DMA 传输结束 +#define SPI0_IT_FIFO_HF RB_SPI_IE_FIFO_HF // FIFO 使用过半 +#define SPI0_IT_BYTE_END RB_SPI_IE_BYTE_END // 单字节传输完成 +#define SPI0_IT_CNT_END RB_SPI_IE_CNT_END // 全部字节传输完成 + +/** + * @brief Configuration data mode + */ +typedef enum +{ + Mode0_LowBitINFront = 0, // 模式0，低位在前 + Mode0_HighBitINFront, // 模式0，高位在前 + Mode3_LowBitINFront, // 模式3，低位在前 + Mode3_HighBitINFront, // 模式3，高位在前 +} ModeBitOrderTypeDef; + +/** + * @brief Configuration SPI0 slave mode + */ +typedef enum +{ + Mode_DataStream = 0, // 数据流模式 + Mose_FirstCmd, // 首字节命令模式 +} Slave_ModeTypeDef; + +/** + * @brief 主机模式默认初始化：模式0+3线全双工+8MHz + */ +void SPI0_MasterDefInit(void); + +/** + * @brief SPI0 基准时钟配置，= d*Tsys + * + * @param c - 时钟分频系数 + */ +void SPI0_CLKCfg(uint8_t c); + +/** + * @brief 设置数据流模式 + * + * @param m - 数据流模式 refer to ModeBitOrderTypeDef + */ +void SPI0_DataMode(ModeBitOrderTypeDef m); + +/** + * @brief 发送单字节 (buffer) + * + * @param d - 发送字节 + */ +void SPI0_MasterSendByte(uint8_t d); + +/** + * @brief 接收单字节 (buffer) + * + * @param none + */ +uint8_t SPI0_MasterRecvByte(void); + +/** + * @brief 使用FIFO连续发送多字节 + * + * @param pbuf - 待发送的数据内容首地址 + * @param len - 请求发送的数据长度，最大4095 + */ +void SPI0_MasterTrans(uint8_t *pbuf, uint16_t len); + +/** + * @brief 使用FIFO连续接收多字节 + * + * @param pbuf - 待接收的数据首地址 + * @param len - 待接收的数据长度，最大4095 + */ +void SPI0_MasterRecv(uint8_t *pbuf, uint16_t len); + +/** + * @brief DMA方式连续发送数据 + * + * @param pbuf - 待发送数据起始地址,需要四字节对其 + * @param len - 待发送数据长度 + */ +void SPI0_MasterDMATrans(uint8_t *pbuf, uint16_t len); + +/** + * @brief DMA方式连续接收数据 + * + * @param pbuf - 待接收数据存放起始地址,需要四字节对其 + * @param len - 待接收数据长度 + */ +void SPI0_MasterDMARecv(uint8_t *pbuf, uint16_t len); + +void SPI1_MasterDefInit(void); /* 主机模式默认初始化：模式0+3线全双工+8MHz */ +void SPI1_CLKCfg(UINT8 c); /* SPI1 基准时钟配置，= d*Tsys */ +void SPI1_DataMode(ModeBitOrderTypeDef m); /* 设置数据流模式 */ + +void SPI1_MasterSendByte(UINT8 d); /* 发送单字节 (buffer) */ +UINT8 SPI1_MasterRecvByte(void); /* 接收单字节 (buffer) */ + +void SPI1_MasterTrans(UINT8 *pbuf, UINT16 len); /* 使用FIFO连续发送多字节 */ +void SPI1_MasterRecv(UINT8 *pbuf, UINT16 len); /* 使用FIFO连续接收多字节 */ + +/** + * @brief 设备模式默认初始化，建议设置MISO的GPIO对应为输入模式 + */ +void SPI0_SlaveInit(void); + +/** + * @brief 加载首字节数据内容 + * + * @param d - 首字节数据内容 + */ +#define SetFirstData(d) (R8_SPI0_SLAVE_PRE = d) + +/** + * @brief 从机模式，发送一字节数据 + * + * @param d - 待发送数据 + */ +void SPI0_SlaveSendByte(uint8_t d); + +/** + * @brief 从机模式，接收一字节数据 + * + * @return 接收到数据 + */ +uint8_t SPI0_SlaveRecvByte(void); + +/** + * @brief 从机模式，发送多字节数据 + * + * @param pbuf - 待发送的数据内容首地址 + * @param len - 请求发送的数据长度，最大4095 + */ +void SPI0_SlaveTrans(uint8_t *pbuf, uint16_t len); + +/** + * @brief 从机模式，接收多字节数据 + * + * @param pbuf - 接收收数据存放起始地址 + * @param len - 请求接收数据长度 + */ +void SPI0_SlaveRecv(uint8_t *pbuf, uint16_t len); + +/** + * @brief DMA方式连续发送数据 + * + * @param pbuf - 待发送数据起始地址,需要四字节对其 + * @param len - 待发送数据长度 + */ +void SPI0_SlaveDMATrans(uint8_t *pbuf, uint16_t len); + +/** + * @brief DMA方式连续接收数据 + * + * @param pbuf - 待接收数据存放起始地址,需要四字节对其 + * @param len - 待接收数据长度 + */ +void SPI0_SlaveDMARecv(uint8_t *pbuf, uint16_t len); + +/** + * @brief 配置SPI0中断 + * + * @param s - 使能/关闭 + * @param f - refer to SPI0 interrupt bit define + */ +#define SPI0_ITCfg(s, f) ((s) ? (R8_SPI0_INTER_EN |= f) : (R8_SPI0_INTER_EN &= ~f)) + +/** + * @brief 获取中断标志状态，0-未置位，(!0)-触发 + * + * @param f - refer to SPI0 interrupt bit define + */ +#define SPI0_GetITFlag(f) (R8_SPI0_INT_FLAG & f) + +/** + * @brief 清除当前中断标志 + * + * @param f - refer to SPI0 interrupt bit define + */ +#define SPI0_ClearITFlag(f) (R8_SPI0_INT_FLAG = f) + +/** + * @brief 关闭SPI0 + */ +#define SPI0_Disable() (R8_SPI0_CTRL_MOD &= ~(RB_SPI_MOSI_OE | RB_SPI_SCK_OE | RB_SPI_MISO_OE)) + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_SPI_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_sys.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_sys.h new file mode 100644 index 0000000..c3c0e7c --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_sys.h @@ -0,0 +1,189 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_SYS.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_SYS_H__ +#define __CH59x_SYS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief rtc interrupt event define + */ +typedef enum +{ + RST_STATUS_SW = 0, // 软件复位 + RST_STATUS_RPOR, // 上电复位 + RST_STATUS_WTR, // 看门狗超时复位 + RST_STATUS_MR, // 外部手动复位 + RST_STATUS_LRM0, // 唤醒复位-软复位引起 + RST_STATUS_GPWSM, // 下电模式唤醒复位 + RST_STATUS_LRM1, // 唤醒复位-看门狗引起 + RST_STATUS_LRM2, // 唤醒复位-手动复位引起 + +} SYS_ResetStaTypeDef; + +/** + * @brief rtc interrupt event define + */ +typedef enum +{ + INFO_ROM_READ = 0, // FlashROM 代码和数据区 是否可读 + INFO_RESET_EN = 2, // RST#外部手动复位输入功能是否开启 + INFO_BOOT_EN, // 系统引导程序 BootLoader 是否开启 + INFO_DEBUG_EN, // 系统仿真调试接口是否开启 + INFO_LOADER, // 当前系统是否处于Bootloader 区 + STA_SAFEACC_ACT, // 当前系统是否处于安全访问状态，否则RWA属性区域不可访问 + +} SYS_InfoStaTypeDef; + +/** + * @brief 获取芯片ID类，一般为固定值 + */ +#define SYS_GetChipID() R8_CHIP_ID + +/** + * @brief 获取安全访问ID，一般为固定值 + */ +#define SYS_GetAccessID() R8_SAFE_ACCESS_ID + +/** + * @brief 配置系统运行时钟 + * + * @param sc - 系统时钟源选择 refer to SYS_CLKTypeDef + */ +void SetSysClock(SYS_CLKTypeDef sc); + +/** + * @brief 获取当前系统时钟 + * + * @return Hz + */ +uint32_t GetSysClock(void); + +/** + * @brief 获取当前系统信息状态 + * + * @param i - refer to SYS_InfoStaTypeDef + * + * @return 是否开启 + */ +uint8_t SYS_GetInfoSta(SYS_InfoStaTypeDef i); + +/** + * @brief 获取系统上次复位状态 + * + * @return refer to SYS_ResetStaTypeDef + */ +#define SYS_GetLastResetSta() (R8_RESET_STATUS & RB_RESET_FLAG) + +/** + * @brief 执行系统软件复位 + */ +void SYS_ResetExecute(void); + +/** + * @brief 设置复位保存寄存器的值，不受手动复位、 软件复位、 看门狗复位或者普通唤醒复位的影响 + * + * @param i - refer to SYS_InfoStaTypeDef + */ +#define SYS_ResetKeepBuf(d) (R8_GLOB_RESET_KEEP = d) + +/** + * @brief 关闭所有中断，并保留当前中断值 + * + * @param pirqv - 当前保留中断值 + */ +void SYS_DisableAllIrq(uint32_t *pirqv); + +/** + * @brief 恢复之前关闭的中断值 + * + * @param irq_status - 当前保留中断值 + */ +void SYS_RecoverIrq(uint32_t irq_status); + +/** + * @brief 获取当前系统(SYSTICK)计数值 + * + * @return 当前计数值 + */ +uint32_t SYS_GetSysTickCnt(void); + +/** + * @brief 加载看门狗计数初值，递增型 + * + * @param c - 看门狗计数初值 + */ +#define WWDG_SetCounter(c) (R8_WDOG_COUNT = c) + +/** + * @brief 看门狗定时器溢出中断使能 + * + * @param s - 溢出是否中断 + */ +void WWDG_ITCfg(FunctionalState s); + +/** + * @brief 看门狗定时器复位功能 + * + * @param s - 溢出是否复位 + */ +void WWDG_ResetCfg(FunctionalState s); + +/** + * @brief 获取当前看门狗定时器溢出标志 + * + * @return 看门狗定时器溢出标志 + */ +#define WWDG_GetFlowFlag() (R8_RST_WDOG_CTRL & RB_WDOG_INT_FLAG) + +/** + * @brief 清除看门狗中断标志，重新加载计数值也可清除 + */ +void WWDG_ClearFlag(void); + +/** + * @brief uS 延时 + * + * @param t - 时间参数 + */ +void mDelayuS(uint16_t t); + +/** + * @brief mS 延时 + * + * @param t - 时间参数 + */ +void mDelaymS(uint16_t t); + +/** + * @brief Enter safe access mode. + * + * @NOTE: After enter safe access mode, about 16 system frequency cycles + * are in safe mode, and one or more secure registers can be rewritten + * within the valid period. The safe mode will be automatically + * terminated after the above validity period is exceeded. + * if sys_safe_access_enable() is called, + * you must call sys_safe_access_disable() before call sys_safe_access_enable() again. + */ +#define sys_safe_access_enable() do{volatile uint32_t mpie_mie;mpie_mie=__risc_v_disable_irq();SAFEOPERATE;\ + R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG1;R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG2;SAFEOPERATE; + +#define sys_safe_access_disable() R8_SAFE_ACCESS_SIG = 0;__risc_v_enable_irq(mpie_mie);SAFEOPERATE;}while(0) + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_SYS_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_timer.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_timer.h new file mode 100644 index 0000000..4f0bf90 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_timer.h @@ -0,0 +1,595 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_timer.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_TIMER_H__ +#define __CH59x_TIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DataBit_25 (1 << 25) + +/** + * @brief TMR0 interrupt bit define + */ + +#define TMR0_3_IT_CYC_END 0x01 // 周期结束标志：捕捉-超时，定时-周期结束，PWM-周期结束 +#define TMR0_3_IT_DATA_ACT 0x02 // 数据有效标志：捕捉-新数据，PWM-有效电平结束 +#define TMR0_3_IT_FIFO_HF 0x04 // FIFO 使用过半：捕捉- FIFO>=4， PWM- FIFO<4 +#define TMR1_2_IT_DMA_END 0x08 // DMA 结束，支持TMR1和TMR2 +#define TMR0_3_IT_FIFO_OV 0x10 // FIFO 溢出：捕捉- FIFO满， PWM- FIFO空 + +/** + * @brief Configuration PWM effective level repeat times + */ +typedef enum +{ + PWM_Times_1 = 0, // PWM 有效输出重复1次数 + PWM_Times_4, // PWM 有效输出重复4次数 + PWM_Times_8, // PWM 有效输出重复8次数 + PWM_Times_16, // PWM 有效输出重复16次数 +} PWM_RepeatTsTypeDef; + +/** + * @brief Configuration Cap mode + */ +typedef enum +{ + CAP_NULL = 0, // 不捕捉 & 不计数 + Edge_To_Edge, // 任意边沿之间 & 计数任意边沿 + FallEdge_To_FallEdge, // 下降沿到下降沿 & 计数下降沿 + RiseEdge_To_RiseEdge, // 上升沿到上升沿 & 计数上升沿 +} CapModeTypeDef; + +/** + * @brief Configuration DMA mode + */ +typedef enum +{ + Mode_Single = 0, // 单次模式 + Mode_LOOP, // 循环模式 +} DMAModeTypeDef; + +/** + * @brief 定时功能初始化 + * + * @param t - 定时时间，基于当前系统时钟Tsys, 最长定时周期 67108864 + */ +void TMR0_TimerInit(uint32_t t); + +/** + * @brief 获取当前定时器值，最大67108864 + * + * @return 当前定时器值 + */ +#define TMR0_GetCurrentTimer() R32_TMR0_COUNT + +/** + * @brief 边沿计数功能初始化 + * + * @param cap - 采集计数类型 + */ +void TMR0_EXTSingleCounterInit(CapModeTypeDef cap); + +/** + * @brief 设置计数统计溢出大小，最大67108862 + * + * @param cyc - 计数统计溢出大小 + */ +#define TMR0_CountOverflowCfg(cyc) (R32_TMR0_CNT_END = (cyc + 2)) + +/** + * @brief 获取当前计数值，最大67108862 + * + * @return 当前计数值 + */ +#define TMR0_GetCurrentCount() R32_TMR0_COUNT + +/** + * @brief PWM0 通道输出波形周期配置, 最大67108864 + * + * @param cyc - 输出波形周期 + */ +#define TMR0_PWMCycleCfg(cyc) (R32_TMR0_CNT_END = cyc) + +/** + * @brief PWM 输出初始化 + * + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param ts - set pwm repeat times, refer to PWM_RepeatTsTypeDef + */ +void TMR0_PWMInit(PWMX_PolarTypeDef pr, PWM_RepeatTsTypeDef ts); + +/** + * @brief PWM0 有效数据脉宽, 最大67108864 + * + * @param d - 有效数据脉宽 + */ +#define TMR0_PWMActDataWidth(d) (R32_TMR0_FIFO = d) + +/** + * @brief CAP0 捕捉电平超时配置, 最大33554432 + * + * @param cyc - 捕捉电平超时 + */ +#define TMR0_CAPTimeoutCfg(cyc) (R32_TMR0_CNT_END = cyc) + +/** + * @brief 外部信号捕捉功能初始化 + * + * @param cap - select capture mode, refer to CapModeTypeDef + */ +void TMR0_CapInit(CapModeTypeDef cap); + +/** + * @brief 获取脉冲数据 + * + * @return 脉冲数据 + */ +#define TMR0_CAPGetData() R32_TMR0_FIFO + +/** + * @brief 获取当前已捕获数据个数 + * + * @return 当前已捕获数据个数 + */ +#define TMR0_CAPDataCounter() R8_TMR0_FIFO_COUNT + +/** + * @brief 关闭 TMR0 PWM输出 + */ +#define TMR0_PWMDisable() (R8_TMR0_CTRL_MOD &= ~RB_TMR_OUT_EN) + +/** + * @brief 开启 TMR0 PWM输出 + */ +#define TMR0_PWMEnable() (R8_TMR0_CTRL_MOD |= RB_TMR_OUT_EN) + +/** + * @brief 关闭 TMR0 + */ +#define TMR0_Disable() (R8_TMR0_CTRL_MOD &= ~RB_TMR_COUNT_EN) + +/** + * @brief 开启 TMR0 + */ +#define TMR0_Enable() (R8_TMR0_CTRL_MOD |= RB_TMR_COUNT_EN) + +/** + * @brief 中断配置 + * + * @param s - 使能/关闭 + * @param f - refer to TMR interrupt bit define + */ +#define TMR0_ITCfg(s, f) ((s) ? (R8_TMR0_INTER_EN |= f) : (R8_TMR0_INTER_EN &= ~f)) + +/** + * @brief 清除中断标志 + * + * @param f - refer to TMR interrupt bit define + */ +#define TMR0_ClearITFlag(f) (R8_TMR0_INT_FLAG = f) + +/** + * @brief 查询中断标志状态 + * + * @param f - refer to TMR interrupt bit define + */ +#define TMR0_GetITFlag(f) (R8_TMR0_INT_FLAG & f) + +/** + * @brief 定时功能初始化 + * + * @param t - 定时时间，基于当前系统时钟Tsys, 最长定时周期 67108864 + */ +void TMR1_TimerInit(uint32_t t); + +/** + * @brief 获取当前定时器值，最大67108864 + * + * @return 当前定时器值 + */ +#define TMR1_GetCurrentTimer() R32_TMR1_COUNT + +/** + * @brief 边沿计数功能初始化 + * + * @param cap - 采集计数类型 + */ +void TMR1_EXTSingleCounterInit(CapModeTypeDef cap); + +/** + * @brief 设置计数统计溢出大小，最大67108862 + * + * @param cyc - 计数统计溢出大小 + */ +#define TMR1_CountOverflowCfg(cyc) (R32_TMR1_CNT_END = (cyc + 2)) + +/** + * @brief 获取当前计数值，最大67108862 + * + * @return 当前计数值 + */ +#define TMR1_GetCurrentCount() R32_TMR1_COUNT + +/** + * @brief PWM1 通道输出波形周期配置, 最大67108864 + * + * @param cyc - 输出波形周期 + */ +#define TMR1_PWMCycleCfg(cyc) (R32_TMR1_CNT_END = cyc) + +/** + * @brief PWM 输出初始化 + * + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param ts - set pwm repeat times, refer to PWM_RepeatTsTypeDef + */ +void TMR1_PWMInit(PWMX_PolarTypeDef pr, PWM_RepeatTsTypeDef ts); + +/** + * @brief PWM1 有效数据脉宽, 最大67108864 + * + * @param d - 有效数据脉宽 + */ +#define TMR1_PWMActDataWidth(d) (R32_TMR1_FIFO = d) + +/** + * @brief CAP1 捕捉电平超时配置, 最大33554432 + * + * @param cyc - 捕捉电平超时 + */ +#define TMR1_CAPTimeoutCfg(cyc) (R32_TMR1_CNT_END = cyc) + +/** + * @brief 外部信号捕捉功能初始化 + * + * @param cap - select capture mode, refer to CapModeTypeDef + */ +void TMR1_CapInit(CapModeTypeDef cap); + +/** + * @brief 获取脉冲数据 + * + * @return 脉冲数据 + */ +#define TMR1_CAPGetData() R32_TMR1_FIFO + +/** + * @brief 获取当前已捕获数据个数 + * + * @return 当前已捕获数据个数 + */ +#define TMR1_CAPDataCounter() R8_TMR1_FIFO_COUNT + +/** + * @brief 配置DMA功能 + * + * @param s - 是否打开DMA功能 + * @param startAddr - DMA 起始地址 + * @param endAddr - DMA 结束地址 + * @param m - 配置DMA模式 + */ +void TMR1_DMACfg(uint8_t s, uint16_t startAddr, uint16_t endAddr, DMAModeTypeDef m); + +/** + * @brief 关闭 TMR1 PWM输出 + */ +#define TMR1_PWMDisable() (R8_TMR1_CTRL_MOD &= ~RB_TMR_OUT_EN) + +/** + * @brief 开启 TMR1 PWM输出 + */ +#define TMR1_PWMEnable() (R8_TMR1_CTRL_MOD |= RB_TMR_OUT_EN) + +/** + * @brief 关闭 TMR1 + */ +#define TMR1_Disable() (R8_TMR1_CTRL_MOD &= ~RB_TMR_COUNT_EN) + +/** + * @brief 开启 TMR1 + */ +#define TMR1_Enable() (R8_TMR1_CTRL_MOD |= RB_TMR_COUNT_EN) + +/** + * @brief 中断配置 + * + * @param s - 使能/关闭 + * @param f - refer to TMR interrupt bit define + */ +#define TMR1_ITCfg(s, f) ((s) ? (R8_TMR1_INTER_EN |= f) : (R8_TMR1_INTER_EN &= ~f)) + +/** + * @brief 清除中断标志 + * + * @param f - refer to TMR interrupt bit define + */ +#define TMR1_ClearITFlag(f) (R8_TMR1_INT_FLAG = f) + +/** + * @brief 查询中断标志状态 + * + * @param f - refer to TMR interrupt bit define + */ +#define TMR1_GetITFlag(f) (R8_TMR1_INT_FLAG & f) + +/** + * @brief 定时功能初始化 + * + * @param t - 定时时间，基于当前系统时钟Tsys, 最长定时周期 67108864 + */ +void TMR2_TimerInit(uint32_t t); + +/** + * @brief 获取当前定时器值，最大67108864 + * + * @return 当前定时器值 + */ +#define TMR2_GetCurrentTimer() R32_TMR2_COUNT + +/** + * @brief 边沿计数功能初始化 + * + * @param cap - 采集计数类型 + */ +void TMR2_EXTSingleCounterInit(CapModeTypeDef cap); + +/** + * @brief 设置计数统计溢出大小，最大67108862 + * + * @param cyc - 计数统计溢出大小 + */ +#define TMR2_CountOverflowCfg(cyc) (R32_TMR2_CNT_END = (cyc + 2)) + +/** + * @brief 获取当前计数值，最大67108862 + * + * @return 当前计数值 + */ +#define TMR2_GetCurrentCount() R32_TMR2_COUNT + +/** + * @brief PWM2 通道输出波形周期配置, 最大67108864 + * + * @param cyc - 输出波形周期 + */ +#define TMR2_PWMCycleCfg(cyc) (R32_TMR2_CNT_END = cyc) + +/** + * @brief PWM 输出初始化 + * + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param ts - set pwm repeat times, refer to PWM_RepeatTsTypeDef + */ +void TMR2_PWMInit(PWMX_PolarTypeDef pr, PWM_RepeatTsTypeDef ts); + +/** + * @brief PWM2 有效数据脉宽, 最大67108864 + * + * @param d - 有效数据脉宽 + */ +#define TMR2_PWMActDataWidth(d) (R32_TMR2_FIFO = d) + +/** + * @brief CAP2 捕捉电平超时配置, 最大33554432 + * + * @param cyc - 捕捉电平超时 + */ +#define TMR2_CAPTimeoutCfg(cyc) (R32_TMR2_CNT_END = cyc) + +/** + * @brief 外部信号捕捉功能初始化 + * + * @param cap - select capture mode, refer to CapModeTypeDef + */ +void TMR2_CapInit(CapModeTypeDef cap); + +/** + * @brief 获取脉冲数据 + * + * @return 脉冲数据 + */ +#define TMR2_CAPGetData() R32_TMR2_FIFO + +/** + * @brief 获取当前已捕获数据个数 + * + * @return 当前已捕获数据个数 + */ +#define TMR2_CAPDataCounter() R8_TMR2_FIFO_COUNT + +/** + * @brief 配置DMA功能 + * + * @param s - 是否打开DMA功能 + * @param startAddr - DMA 起始地址 + * @param endAddr - DMA 结束地址 + * @param m - 配置DMA模式 + */ +void TMR2_DMACfg(uint8_t s, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef m); + +/** + * @brief 关闭 TMR2 PWM输出 + */ +#define TMR2_PWMDisable() (R8_TMR2_CTRL_MOD &= ~RB_TMR_OUT_EN) + +/** + * @brief 开启 TMR2 PWM输出 + */ +#define TMR2_PWMEnable() (R8_TMR2_CTRL_MOD |= RB_TMR_OUT_EN) + +/** + * @brief 关闭 TMR2 + */ +#define TMR2_Disable() (R8_TMR2_CTRL_MOD &= ~RB_TMR_COUNT_EN) + +/** + * @brief 开启 TMR2 + */ +#define TMR2_Enable() (R8_TMR2_CTRL_MOD |= RB_TMR_COUNT_EN) + +/** + * @brief 中断配置 + * + * @param s - 使能/关闭 + * @param f - refer to TMR interrupt bit define + */ +#define TMR2_ITCfg(s, f) ((s) ? (R8_TMR2_INTER_EN |= f) : (R8_TMR2_INTER_EN &= ~f)) + +/** + * @brief 清除中断标志 + * + * @param f - refer to TMR interrupt bit define + */ +#define TMR2_ClearITFlag(f) (R8_TMR2_INT_FLAG = f) + +/** + * @brief 查询中断标志状态 + * + * @param f - refer to TMR interrupt bit define + */ +#define TMR2_GetITFlag(f) (R8_TMR2_INT_FLAG & f) + +/** + * @brief 定时功能初始化 + * + * @param t - 定时时间，基于当前系统时钟Tsys, 最长定时周期 67108864 + */ +void TMR3_TimerInit(uint32_t t); + +/** + * @brief 获取当前定时器值，最大67108864 + * + * @return 当前定时器值 + */ +#define TMR3_GetCurrentTimer() R32_TMR3_COUNT + +/** + * @brief 边沿计数功能初始化 + * + * @param cap - 采集计数类型 + */ +void TMR3_EXTSingleCounterInit(CapModeTypeDef cap); + +/** + * @brief 设置计数统计溢出大小，最大67108862 + * + * @param cyc - 计数统计溢出大小 + */ +#define TMR3_CountOverflowCfg(cyc) (R32_TMR3_CNT_END = (cyc + 2)) + +/** + * @brief 获取当前计数值，最大67108862 + * + * @return 当前计数值 + */ +#define TMR3_GetCurrentCount() R32_TMR3_COUNT + +/** + * @brief PWM3 通道输出波形周期配置, 最大67108864 + * + * @param cyc - 输出波形周期 + */ +#define TMR3_PWMCycleCfg(cyc) (R32_TMR3_CNT_END = cyc) + +/** + * @brief PWM 输出初始化 + * + * @param pr - select wave polar, refer to PWMX_PolarTypeDef + * @param ts - set pwm repeat times, refer to PWM_RepeatTsTypeDef + */ +void TMR3_PWMInit(PWMX_PolarTypeDef pr, PWM_RepeatTsTypeDef ts); + +/** + * @brief PWM3 有效数据脉宽, 最大67108864 + * + * @param d - 有效数据脉宽 + */ +#define TMR3_PWMActDataWidth(d) (R32_TMR3_FIFO = d) + +/** + * @brief CAP3 捕捉电平超时配置, 最大33554432 + * + * @param cyc - 捕捉电平超时 + */ +#define TMR3_CAPTimeoutCfg(cyc) (R32_TMR3_CNT_END = cyc) + +/** + * @brief 外部信号捕捉功能初始化 + * + * @param cap - select capture mode, refer to CapModeTypeDef + */ +void TMR3_CapInit(CapModeTypeDef cap); + +/** + * @brief 获取脉冲数据 + * + * @return 脉冲数据 + */ +#define TMR3_CAPGetData() R32_TMR3_FIFO + +/** + * @brief 获取当前已捕获数据个数 + * + * @return 当前已捕获数据个数 + */ +#define TMR3_CAPDataCounter() R8_TMR3_FIFO_COUNT + +/** + * @brief 关闭 TMR3 PWM输出 + */ +#define TMR3_PWMDisable() (R8_TMR3_CTRL_MOD &= ~RB_TMR_OUT_EN) + +/** + * @brief 开启 TMR3 PWM输出 + */ +#define TMR3_PWMEnable() (R8_TMR3_CTRL_MOD |= RB_TMR_OUT_EN) + +/** + * @brief 关闭 TMR3 + */ +#define TMR3_Disable() (R8_TMR3_CTRL_MOD &= ~RB_TMR_COUNT_EN) + +/** + * @brief 开启 TMR3 + */ +#define TMR3_Enable() (R8_TMR3_CTRL_MOD |= RB_TMR_COUNT_EN) + +/** + * @brief 中断配置 + * + * @param s - 使能/关闭 + * @param f - refer to TMR interrupt bit define + */ +#define TMR3_ITCfg(s, f) ((s) ? (R8_TMR3_INTER_EN |= f) : (R8_TMR3_INTER_EN &= ~f)) + +/** + * @brief 清除中断标志 + * + * @param f - refer to TMR interrupt bit define + */ +#define TMR3_ClearITFlag(f) (R8_TMR3_INT_FLAG = f) + +/** + * @brief 查询中断标志状态 + * + * @param f - refer to TMR interrupt bit define + */ +#define TMR3_GetITFlag(f) (R8_TMR3_INT_FLAG & f) + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_TIMER_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_uart.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_uart.h new file mode 100644 index 0000000..65ecbbd --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_uart.h @@ -0,0 +1,412 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_uart.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_UART_H__ +#define __CH59x_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief LINE error and status define + */ +#define STA_ERR_BREAK RB_LSR_BREAK_ERR // 数据间隔错误 +#define STA_ERR_FRAME RB_LSR_FRAME_ERR // 数据帧错误 +#define STA_ERR_PAR RB_LSR_PAR_ERR // 奇偶校验位出错 +#define STA_ERR_FIFOOV RB_LSR_OVER_ERR // 接收数据溢出 + +#define STA_TXFIFO_EMP RB_LSR_TX_FIFO_EMP // 当前发送FIFO空，可以继续填充发送数据 +#define STA_TXALL_EMP RB_LSR_TX_ALL_EMP // 当前所有发送数据都发送完成 +#define STA_RECV_DATA RB_LSR_DATA_RDY // 当前有接收到数据 + +/** + * @brief Configuration UART TrigByte num + */ +typedef enum +{ + UART_1BYTE_TRIG = 0, // 1字节触发 + UART_2BYTE_TRIG, // 2字节触发 + UART_4BYTE_TRIG, // 4字节触发 + UART_7BYTE_TRIG, // 7字节触发 + +} UARTByteTRIGTypeDef; + +/** + * @brief 串口默认初始化配置 + */ +void UART0_DefInit(void); + +/** + * @brief 串口波特率配置 + * + * @param baudrate - 波特率 + */ +void UART0_BaudRateCfg(uint32_t baudrate); + +/** + * @brief 串口字节触发中断配置 + * + * @param b - 触发字节数 refer to UARTByteTRIGTypeDef + */ +void UART0_ByteTrigCfg(UARTByteTRIGTypeDef b); + +/** + * @brief 串口中断配置 + * + * @param s - 中断控制状态，是否使能相应中断 + * @param i - 中断类型 + * RB_IER_MODEM_CHG - 调制解调器输入状态变化中断使能位（仅 UART0 支持） + * RB_IER_LINE_STAT - 接收线路状态中断 + * RB_IER_THR_EMPTY - 发送保持寄存器空中断 + * RB_IER_RECV_RDY - 接收数据中断 + */ +void UART0_INTCfg(FunctionalState s, uint8_t i); + +/** + * @brief 串口软件复位 + */ +void UART0_Reset(void); + +/** + * @brief 清除当前接收FIFO + */ +#define UART0_CLR_RXFIFO() (R8_UART0_FCR |= RB_FCR_RX_FIFO_CLR) + +/** + * @brief 清除当前发送FIFO + */ +#define UART0_CLR_TXFIFO() (R8_UART0_FCR |= RB_FCR_TX_FIFO_CLR) + +/** + * @brief 获取当前中断标志 + * + * @return 当前中断标志 + */ +#define UART0_GetITFlag() (R8_UART0_IIR & RB_IIR_INT_MASK) + +/** + * @brief 获取当前通讯状态 + * + * @return refer to LINE error and status define + */ +#define UART0_GetLinSTA() (R8_UART0_LSR) + +/** + * @brief 串口单字节发送 + * + * @param b 待发送的字节 + */ +#define UART0_SendByte(b) (R8_UART0_THR = b) + +/** + * @brief 串口多字节发送 + * + * @param buf - 待发送的数据内容首地址 + * @param l - 待发送的数据长度 + */ +void UART0_SendString(uint8_t *buf, uint16_t l); + +/** + * @brief 串口读取单字节 + * + * @return 读取到的单字节 + */ +#define UART0_RecvByte() (R8_UART0_RBR) + +/** + * @brief 串口读取多字节 + * + * @param buf - 读取数据存放缓存区首地址 + * + * @return 读取数据长度 + */ +uint16_t UART0_RecvString(uint8_t *buf); + +/** + * @brief 串口默认初始化配置 + */ +void UART1_DefInit(void); + +/** + * @brief 串口波特率配置 + * + * @param baudrate - 波特率 + */ +void UART1_BaudRateCfg(uint32_t baudrate); + +/** + * @brief 串口字节触发中断配置 + * + * @param b - 触发字节数 refer to UARTByteTRIGTypeDef + */ +void UART1_ByteTrigCfg(UARTByteTRIGTypeDef b); + +/** + * @brief 串口中断配置 + * + * @param s - 中断控制状态，是否使能相应中断 + * @param i - 中断类型 + * RB_IER_MODEM_CHG - 调制解调器输入状态变化中断使能位（仅 UART0 支持） + * RB_IER_LINE_STAT - 接收线路状态中断 + * RB_IER_THR_EMPTY - 发送保持寄存器空中断 + * RB_IER_RECV_RDY - 接收数据中断 + */ +void UART1_INTCfg(FunctionalState s, uint8_t i); + +/** + * @brief 串口软件复位 + */ +void UART1_Reset(void); + +/** + * @brief 清除当前接收FIFO + */ +#define UART1_CLR_RXFIFO() (R8_UART1_FCR |= RB_FCR_RX_FIFO_CLR) + +/** + * @brief 清除当前发送FIFO + */ +#define UART1_CLR_TXFIFO() (R8_UART1_FCR |= RB_FCR_TX_FIFO_CLR) + +/** + * @brief 获取当前中断标志 + * + * @return 当前中断标志 + */ +#define UART1_GetITFlag() (R8_UART1_IIR & RB_IIR_INT_MASK) + +/** + * @brief 获取当前通讯状态 + * + * @return refer to LINE error and status define + */ +#define UART1_GetLinSTA() (R8_UART1_LSR) + +/** + * @brief 串口单字节发送 + * + * @param b 待发送的字节 + */ +#define UART1_SendByte(b) (R8_UART1_THR = b) + +/** + * @brief 串口多字节发送 + * + * @param buf - 待发送的数据内容首地址 + * @param l - 待发送的数据长度 + */ +void UART1_SendString(uint8_t *buf, uint16_t l); + +/** + * @brief 串口读取单字节 + * + * @return 读取到的单字节 + */ +#define UART1_RecvByte() (R8_UART1_RBR) + +/** + * @brief 串口读取多字节 + * + * @param buf - 读取数据存放缓存区首地址 + * + * @return 读取数据长度 + */ +uint16_t UART1_RecvString(uint8_t *buf); + +/** + * @brief 串口默认初始化配置 + */ +void UART2_DefInit(void); + +/** + * @brief 串口波特率配置 + * + * @param baudrate - 波特率 + */ +void UART2_BaudRateCfg(uint32_t baudrate); + +/** + * @brief 串口字节触发中断配置 + * + * @param b - 触发字节数 refer to UARTByteTRIGTypeDef + */ +void UART2_ByteTrigCfg(UARTByteTRIGTypeDef b); + +/** + * @brief 串口中断配置 + * + * @param s - 中断控制状态，是否使能相应中断 + * @param i - 中断类型 + * RB_IER_MODEM_CHG - 调制解调器输入状态变化中断使能位（仅 UART0 支持） + * RB_IER_LINE_STAT - 接收线路状态中断 + * RB_IER_THR_EMPTY - 发送保持寄存器空中断 + * RB_IER_RECV_RDY - 接收数据中断 + */ +void UART2_INTCfg(FunctionalState s, uint8_t i); + +/** + * @brief 串口软件复位 + */ +void UART2_Reset(void); + +/** + * @brief 清除当前接收FIFO + */ +#define UART2_CLR_RXFIFO() (R8_UART2_FCR |= RB_FCR_RX_FIFO_CLR) + +/** + * @brief 清除当前发送FIFO + */ +#define UART2_CLR_TXFIFO() (R8_UART2_FCR |= RB_FCR_TX_FIFO_CLR) + +/** + * @brief 获取当前中断标志 + * + * @return 当前中断标志 + */ +#define UART2_GetITFlag() (R8_UART2_IIR & RB_IIR_INT_MASK) + +/** + * @brief 获取当前通讯状态 + * + * @return refer to LINE error and status define + */ +#define UART2_GetLinSTA() (R8_UART2_LSR) + +/** + * @brief 串口单字节发送 + * + * @param b 待发送的字节 + */ +#define UART2_SendByte(b) (R8_UART2_THR = b) + +/** + * @brief 串口多字节发送 + * + * @param buf - 待发送的数据内容首地址 + * @param l - 待发送的数据长度 + */ +void UART2_SendString(uint8_t *buf, uint16_t l); + +/** + * @brief 串口读取单字节 + * + * @return 读取到的单字节 + */ +#define UART2_RecvByte() (R8_UART2_RBR) + +/** + * @brief 串口读取多字节 + * + * @param buf - 读取数据存放缓存区首地址 + * + * @return 读取数据长度 + */ +uint16_t UART2_RecvString(uint8_t *buf); + +/** + * @brief 串口默认初始化配置 + */ +void UART3_DefInit(void); + +/** + * @brief 串口波特率配置 + * + * @param baudrate - 波特率 + */ +void UART3_BaudRateCfg(uint32_t baudrate); + +/** + * @brief 串口字节触发中断配置 + * + * @param b - 触发字节数 refer to UARTByteTRIGTypeDef + */ +void UART3_ByteTrigCfg(UARTByteTRIGTypeDef b); + +/** + * @brief 串口中断配置 + * + * @param s - 中断控制状态，是否使能相应中断 + * @param i - 中断类型 + * RB_IER_MODEM_CHG - 调制解调器输入状态变化中断使能位（仅 UART0 支持） + * RB_IER_LINE_STAT - 接收线路状态中断 + * RB_IER_THR_EMPTY - 发送保持寄存器空中断 + * RB_IER_RECV_RDY - 接收数据中断 + */ +void UART3_INTCfg(FunctionalState s, uint8_t i); + +/** + * @brief 串口软件复位 + */ +void UART3_Reset(void); + +/** + * @brief 清除当前接收FIFO + */ +#define UART3_CLR_RXFIFO() (R8_UART3_FCR |= RB_FCR_RX_FIFO_CLR) + +/** + * @brief 清除当前发送FIFO + */ +#define UART3_CLR_TXFIFO() (R8_UART3_FCR |= RB_FCR_TX_FIFO_CLR) + +/** + * @brief 获取当前中断标志 + * + * @return 当前中断标志 + */ +#define UART3_GetITFlag() (R8_UART3_IIR & RB_IIR_INT_MASK) + +/** + * @brief 获取当前通讯状态 + * + * @return refer to LINE error and status define + */ +#define UART3_GetLinSTA() (R8_UART3_LSR) + +/** + * @brief 串口单字节发送 + * + * @param b 待发送的字节 + */ +#define UART3_SendByte(b) (R8_UART3_THR = b) + +/** + * @brief 串口多字节发送 + * + * @param buf - 待发送的数据内容首地址 + * @param l - 待发送的数据长度 + */ +void UART3_SendString(uint8_t *buf, uint16_t l); + +/** + * @brief 串口读取单字节 + * + * @return 读取到的单字节 + */ +#define UART3_RecvByte() (R8_UART3_RBR) + +/** + * @brief 串口读取多字节 + * + * @param buf - 读取数据存放缓存区首地址 + * + * @return 读取数据长度 + */ +uint16_t UART3_RecvString(uint8_t *buf); + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_UART_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_usbdev.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_usbdev.h new file mode 100644 index 0000000..59dd287 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_usbdev.h @@ -0,0 +1,152 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_usbdev.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_USBDEV_H__ +#define __CH59x_USBDEV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* HID类请求 */ +#define DEF_USB_GET_IDLE 0x02 /* get idle for key or mouse */ +#define DEF_USB_GET_PROTOCOL 0x03 /* get protocol for bios type */ +#define DEF_USB_SET_REPORT 0x09 /* set report for key */ +#define DEF_USB_SET_IDLE 0x0A /* set idle for key or mouse */ +#define DEF_USB_SET_PROTOCOL 0x0B /* set protocol for bios type */ + +/* 以下缓存区是USB模块收发使用的数据缓冲区，总共9个通道（9块缓存），用户可根据实际使用的通道数定义相应缓存区 */ +extern uint8_t *pEP0_RAM_Addr; //ep0(64)+ep4_out(64)+ep4_in(64) +extern uint8_t *pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64) +extern uint8_t *pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64) +extern uint8_t *pEP3_RAM_Addr; //ep3_out(64)+ep3_in(64) + +#define pSetupReqPak ((PUSB_SETUP_REQ)pEP0_RAM_Addr) +#define pEP0_DataBuf (pEP0_RAM_Addr) +#define pEP1_OUT_DataBuf (pEP1_RAM_Addr) +#define pEP1_IN_DataBuf (pEP1_RAM_Addr + 64) +#define pEP2_OUT_DataBuf (pEP2_RAM_Addr) +#define pEP2_IN_DataBuf (pEP2_RAM_Addr + 64) +#define pEP3_OUT_DataBuf (pEP3_RAM_Addr) +#define pEP3_IN_DataBuf (pEP3_RAM_Addr + 64) +#define pEP4_OUT_DataBuf (pEP0_RAM_Addr + 64) +#define pEP4_IN_DataBuf (pEP0_RAM_Addr + 128) + +/** + * @brief USB设备功能初始化，4个端点，8个通道。 + */ +void USB_DeviceInit(void); + +/** + * @brief USB设备应答传输处理 + */ +void USB_DevTransProcess(void); + +/** + * @brief 端点1下传数据处理 + * + * @param l - 待处理数据长度(<64B) + */ +void DevEP1_OUT_Deal(uint8_t l); + +/** + * @brief 端点2下传数据处理 + * + * @param l - 待处理数据长度(<64B) + */ +void DevEP2_OUT_Deal(uint8_t l); + +/** + * @brief 端点3下传数据处理 + * + * @param l - 待处理数据长度(<64B) + */ +void DevEP3_OUT_Deal(uint8_t l); + +/** + * @brief 端点4下传数据处理 + * + * @param l - 待处理数据长度(<64B) + */ +void DevEP4_OUT_Deal(uint8_t l); + +/** + * @brief 端点1数据上传 + * + * @param l - 上传数据长度(<64B) + */ +void DevEP1_IN_Deal(uint8_t l); + +/** + * @brief 端点2数据上传 + * + * @param l - 上传数据长度(<64B) + */ +void DevEP2_IN_Deal(uint8_t l); + +/** + * @brief 端点3数据上传 + * + * @param l - 上传数据长度(<64B) + */ +void DevEP3_IN_Deal(uint8_t l); + +/** + * @brief 端点4数据上传 + * + * @param l - 上传数据长度(<64B) + */ +void DevEP4_IN_Deal(uint8_t l); + +/** + * @brief 查询端点1是否上传完成 + * + * @return 0-未完成 (!0)-已完成 + */ +#define EP1_GetINSta() (R8_UEP1_CTRL & UEP_T_RES_NAK) + +/** + * @brief 查询端点2是否上传完成 + * + * @return 0-未完成 (!0)-已完成 + */ +#define EP2_GetINSta() (R8_UEP2_CTRL & UEP_T_RES_NAK) + +/** + * @brief 查询端点3是否上传完成 + * + * @return 0-未完成 (!0)-已完成 + */ +#define EP3_GetINSta() (R8_UEP3_CTRL & UEP_T_RES_NAK) + +/** + * @brief 查询端点4是否上传完成 + * + * @return 0-未完成 (!0)-已完成 + */ +#define EP4_GetINSta() (R8_UEP4_CTRL & UEP_T_RES_NAK) + +/** + * @brief 关闭USB上拉电阻 + */ +#define USB_DisablePin() (R16_PIN_ANALOG_IE &= ~(RB_PIN_USB_IE | RB_PIN_USB_DP_PU)) + +/** + * @brief 关闭USB + */ +#define USB_Disable() (R32_USB_CONTROL = 0) + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_USBDEV_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/CH59x_usbhost.h b/nametag8_CH592/StdPeriphDriver/inc/CH59x_usbhost.h new file mode 100644 index 0000000..dd4ba58 --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/CH59x_usbhost.h @@ -0,0 +1,314 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH59x_usbhost.h + * Author : WCH + * Version : V1.2 + * Date : 2021/11/17 + * Description + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#ifndef __CH59x_USBHOST_H__ +#define __CH59x_USBHOST_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#if DISK_LIB_ENABLE + #if DISK_WITHOUT_USB_HUB + /* 不使用U盘文件系统库或者U盘挂载USBhub下面，需要关闭下面定义 */ + #define FOR_ROOT_UDISK_ONLY + #endif + /* 使用U盘文件系统库，需要开启下面定义, 不使用请关闭 */ + #define DISK_BASE_BUF_LEN 512 /* 默认的磁盘数据缓冲区大小为512字节,建议选择为2048甚至4096以支持某些大扇区的U盘,为0则禁止在.H文件中定义缓冲区并由应用程序在pDISK_BASE_BUF中指定 */ +#endif + +// 各子程序返回状态码 +#define ERR_SUCCESS 0x00 // 操作成功 +#define ERR_USB_CONNECT 0x15 /* 检测到USB设备连接事件,已经连接 */ +#define ERR_USB_DISCON 0x16 /* 检测到USB设备断开事件,已经断开 */ +#define ERR_USB_BUF_OVER 0x17 /* USB传输的数据有误或者数据太多缓冲区溢出 */ +#define ERR_USB_DISK_ERR 0x1F /* USB存储器操作失败,在初始化时可能是USB存储器不支持,在读写操作中可能是磁盘损坏或者已经断开 */ +#define ERR_USB_TRANSFER 0x20 /* NAK/STALL等更多错误码在0x20~0x2F */ +#define ERR_USB_UNSUPPORT 0xFB /* 不支持的USB设备*/ +#define ERR_USB_UNKNOWN 0xFE /* 设备操作出错*/ +#define ERR_AOA_PROTOCOL 0x41 /* 协议版本出错 */ + +/*USB设备相关信息表,最多支持1个设备*/ +#define ROOT_DEV_DISCONNECT 0 +#define ROOT_DEV_CONNECTED 1 +#define ROOT_DEV_FAILED 2 +#define ROOT_DEV_SUCCESS 3 +#define DEV_TYPE_KEYBOARD (USB_DEV_CLASS_HID | 0x20) +#define DEV_TYPE_MOUSE (USB_DEV_CLASS_HID | 0x30) +#define DEF_AOA_DEVICE 0xF0 +#define DEV_TYPE_UNKNOW 0xFF + +/* +约定: USB设备地址分配规则(参考USB_DEVICE_ADDR) +地址值 设备位置 +0x02 内置Root-HUB下的USB设备或外部HUB +0x1x 内置Root-HUB下的外部HUB的端口x下的USB设备,x为1~n +*/ +#define HUB_MAX_PORTS 4 +#define WAIT_USB_TOUT_200US 800 // 等待USB中断超时时间 + +typedef struct +{ + uint8_t DeviceStatus; // 设备状态,0-无设备,1-有设备但尚未初始化,2-有设备但初始化枚举失败,3-有设备且初始化枚举成功 + uint8_t DeviceAddress; // 设备被分配的USB地址 + uint8_t DeviceSpeed; // 0为低速,非0为全速 + uint8_t DeviceType; // 设备类型 + uint16_t DeviceVID; + uint16_t DevicePID; + uint8_t GpVar[4]; // 通用变量，存放端点 + uint8_t GpHUBPortNum; // 通用变量,如果是HUB，表示HUB端口数 +} _RootHubDev; + +typedef struct +{ + UINT8 DeviceStatus; // 设备状态,0-无设备,1-有设备但尚未初始化,2-有设备但初始化枚举失败,3-有设备且初始化枚举成功 + UINT8 DeviceAddress; // 设备被分配的USB地址 + UINT8 DeviceSpeed; // 0为低速,非0为全速 + UINT8 DeviceType; // 设备类型 + UINT16 DeviceVID; + UINT16 DevicePID; + UINT8 GpVar[4]; // 通用变量 +} _DevOnHubPort; // 假定:不超过1个外部HUB,每个外部HUB不超过HUB_MAX_PORTS个端口(多了不管) + +extern _RootHubDev ThisUsbDev; +extern _DevOnHubPort DevOnHubPort[HUB_MAX_PORTS]; // 假定:不超过1个外部HUB,每个外部HUB不超过HUB_MAX_PORTS个端口(多了不管) +extern uint8_t UsbDevEndp0Size; // USB设备的端点0的最大包尺寸 */ +extern uint8_t FoundNewDev; + +extern uint8_t *pHOST_RX_RAM_Addr; +extern uint8_t *pHOST_TX_RAM_Addr; + +extern _RootHubDev ThisUsb2Dev; +extern _DevOnHubPort DevOnU2HubPort[HUB_MAX_PORTS]; // 假定:不超过1个外部HUB,每个外部HUB不超过HUB_MAX_PORTS个端口(多了不管) +extern uint8_t Usb2DevEndp0Size; // USB设备的端点0的最大包尺寸 */ +extern uint8_t FoundNewU2Dev; + +extern uint8_t *pU2HOST_RX_RAM_Addr; +extern uint8_t *pU2HOST_TX_RAM_Addr; + +#define pSetupReq ((PUSB_SETUP_REQ)pHOST_TX_RAM_Addr) +#define pU2SetupReq ((PUSB_SETUP_REQ)pU2HOST_TX_RAM_Addr) +extern uint8_t Com_Buffer[]; +extern uint8_t U2Com_Buffer[]; + +/* 以下为USB主机请求包 */ +extern const uint8_t SetupGetDevDescr[]; // 获取设备描述符*/ +extern const uint8_t SetupGetCfgDescr[]; // 获取配置描述符*/ +extern const uint8_t SetupSetUsbAddr[]; // 设置USB地址*/ +extern const uint8_t SetupSetUsbConfig[]; // 设置USB配置*/ +extern const uint8_t SetupSetUsbInterface[]; // 设置USB接口配置*/ +extern const uint8_t SetupClrEndpStall[]; // 清除端点STALL*/ + +extern const uint8_t SetupGetU2DevDescr[]; // 获取设备描述符*/ +extern const uint8_t SetupGetU2CfgDescr[]; // 获取配置描述符*/ +extern const uint8_t SetupSetUsb2Addr[]; // 设置USB地址*/ +extern const uint8_t SetupSetUsb2Config[]; // 设置USB配置*/ +extern const uint8_t SetupSetUsb2Interface[]; // 设置USB接口配置*/ +extern const uint8_t SetupClrU2EndpStall[]; // 清除端点STALL*/ + +/** + * @brief 关闭ROOT-HUB端口,实际上硬件已经自动关闭,此处只是清除一些结构状态 + */ +void DisableRootHubPort(void); + +/** + * @brief 分析ROOT-HUB状态,处理ROOT-HUB端口的设备插拔事件 + * 如果设备拔出,函数中调用DisableRootHubPort()函数,将端口关闭,插入事件,置相应端口的状态位 + * + * @return 返回ERR_SUCCESS为没有情况,返回ERR_USB_CONNECT为检测到新连接,返回ERR_USB_DISCON为检测到断开 + */ +uint8_t AnalyzeRootHub(void); + +/** + * @brief 设置USB主机当前操作的USB设备地址 + * + * @param addr - USB设备地址 + */ +void SetHostUsbAddr(uint8_t addr); + +/** + * @brief 设置当前USB速度 + * + * @param FullSpeed - USB速度 + */ +void SetUsbSpeed(uint8_t FullSpeed); + +/** + * @brief 检测到设备后,复位总线,为枚举设备准备,设置为默认为全速 + */ +void ResetRootHubPort(void); + +/** + * @brief 使能ROOT-HUB端口,相应的bUH_PORT_EN置1开启端口,设备断开可能导致返回失败 + * + * @return 返回ERR_SUCCESS为检测到新连接,返回ERR_USB_DISCON为无连接 + */ +uint8_t EnableRootHubPort(void); + +/** + * @brief 等待USB中断 + * + * @return 返回ERR_SUCCESS 数据接收或者发送成功,返回ERR_USB_UNKNOWN 数据接收或者发送失败 + */ +uint8_t WaitUSB_Interrupt(void); + +/** + * @brief 传输事务,输入目的端点地址/PID令牌,同步标志,以20uS为单位的NAK重试总时间(0则不重试,0xFFFF无限重试),返回0成功,超时/出错重试 + * 本子程序着重于易理解,而在实际应用中,为了提供运行速度,应该对本子程序代码进行优化 + * + * @param endp_pid - 令牌和地址, 高4位是token_pid令牌, 低4位是端点地址 + * @param tog - 同步标志 + * @param timeout - 超时时间 + * + * @return ERR_USB_UNKNOWN 超时，可能硬件异常 + * ERR_USB_DISCON 设备断开 + * ERR_USB_CONNECT 设备连接 + * ERR_SUCCESS 传输完成 + */ +uint8_t USBHostTransact(uint8_t endp_pid, uint8_t tog, uint32_t timeout); + +/** + * @brief 执行控制传输,8字节请求码在pSetupReq中,DataBuf为可选的收发缓冲区 + * + * @param DataBuf - 如果需要接收和发送数据,那么DataBuf需指向有效缓冲区用于存放后续数据 + * @param RetLen - 实际成功收发的总长度保存在RetLen指向的字节变量中 + * + * @return ERR_USB_BUF_OVER IN状态阶段出错 + * ERR_SUCCESS 数据交换成功 + */ +uint8_t HostCtrlTransfer(uint8_t *DataBuf, uint8_t *RetLen); + +/** + * @brief 复制控制传输的请求包 + * + * @param pReqPkt - 控制请求包地址 + */ +void CopySetupReqPkg(const uint8_t *pReqPkt); + +/** + * @brief 获取设备描述符,返回在 pHOST_TX_RAM_Addr 中 + * + * @return ERR_USB_BUF_OVER 描述符长度错误 + * ERR_SUCCESS 成功 + */ +uint8_t CtrlGetDeviceDescr(void); + +/** + * @brief 获取配置描述符,返回在 pHOST_TX_RAM_Addr 中 + * + * @return ERR_USB_BUF_OVER 描述符长度错误 + * ERR_SUCCESS 成功 + */ +uint8_t CtrlGetConfigDescr(void); + +/** + * @brief 设置USB设备地址 + * + * @param addr - 设备地址 + * + * @return ERR_SUCCESS 成功 + */ +uint8_t CtrlSetUsbAddress(uint8_t addr); + +/** + * @brief 设置USB设备配置 + * + * @param cfg - 配置值 + * + * @return ERR_SUCCESS 成功 + */ +uint8_t CtrlSetUsbConfig(uint8_t cfg); + +/** + * @brief 清除端点STALL + * + * @param endp - 端点地址 + * + * @return ERR_SUCCESS 成功 + */ +uint8_t CtrlClearEndpStall(uint8_t endp); + +/** + * @brief 设置USB设备接口 + * + * @param cfg - 配置值 + * + * @return ERR_SUCCESS 成功 + */ +uint8_t CtrlSetUsbIntercace(uint8_t cfg); + +/** + * @brief USB主机功能初始化 + */ +void USB_HostInit(void); +uint8_t EnumAllHubPort(void);// 枚举所有ROOT-HUB端口下外部HUB后的二级USB设备 +void SelectHubPort(uint8_t HubPortIndex); // HubPortIndex=0选择操作指定的ROOT-HUB端口,否则选择操作指定的ROOT-HUB端口的外部HUB的指定端口 +uint16_t SearchTypeDevice(uint8_t type); // 在ROOT-HUB以及外部HUB各端口上搜索指定类型的设备所在的端口号,输出端口号为0xFFFF则未搜索到. +uint8_t SETorOFFNumLock(uint8_t *buf); // NumLock的点灯判断 + +/*************************************************************/ + +/** + * @brief 初始化指定ROOT-HUB端口的USB设备 + * + * @return 错误码 + */ +uint8_t InitRootDevice(void); + +/** + * @brief 获取HID设备报表描述符,返回在TxBuffer中 + * + * @return 错误码 + */ +uint8_t CtrlGetHIDDeviceReport(uint8_t infc); + +/** + * @brief 获取HUB描述符,返回在Com_Buffer中 + * + * @return 错误码 + */ +uint8_t CtrlGetHubDescr(void); + +/** + * @brief 查询HUB端口状态,返回在Com_Buffer中 + * + * @param HubPortIndex - 端口号 + * + * @return 错误码 + */ +uint8_t HubGetPortStatus(uint8_t HubPortIndex); + +/** + * @brief 设置HUB端口特性 + * + * @param HubPortIndex - 端口号 + * @param FeatureSelt - 端口特性 + * + * @return 错误码 + */ +uint8_t HubSetPortFeature(uint8_t HubPortIndex, uint8_t FeatureSelt); + +/** + * @brief 清除HUB端口特性 + * + * @param HubPortIndex - 端口号 + * @param FeatureSelt - 端口特性 + * + * @return 错误码 + */ +uint8_t HubClearPortFeature(uint8_t HubPortIndex, uint8_t FeatureSelt); + +#ifdef __cplusplus +} +#endif + +#endif // __CH59x_USBHOST_H__ diff --git a/nametag8_CH592/StdPeriphDriver/inc/ISP592.h b/nametag8_CH592/StdPeriphDriver/inc/ISP592.h new file mode 100644 index 0000000..2f93c3c --- /dev/null +++ b/nametag8_CH592/StdPeriphDriver/inc/ISP592.h @@ -0,0 +1,181 @@ +/* CH592 Flash-ROM & Data-Flash */ +/* Website: http://wch.cn */ +/* Email: tech@wch.cn */ +/* Author: W.ch 2020.06 */ +/* V1.0 FlashROM library for USER/BOOT */ +/* for the target in USER code area on the chip divided into USER code area and BOOT area */ +/* 用于具有用户代码区和引导区的芯片、操作目标为用户代码区的情况， + 可以在用户代码中被调用（IAP，擦写自身），也可以在引导代码中被调用（更新用户代码） */ + +/* Flash-ROM feature: + for store program code, support block erasing, dword and page writing, dword verifying, unit for Length is byte, + minimal quantity for write or verify is one dword (4-bytes), + 256 bytes/page for writing, FLASH_ROM_WRITE support one dword or more dword writing, but multiple of 256 is the best, + 4KB (4096 bytes) bytes/block for erasing, so multiple of 4096 is the best */ + +/* Data-Flash(EEPROM) feature: + for store data, support block erasing, byte and page writing, byte reading, + minimal quantity for write or read is one byte, + 256 bytes/page for writing, EEPROM_WRITE support one byte or more byte writing, but multiple of 256 is the best, + 0.25KB/4KB (256/4096 bytes) bytes/block for erasing, so multiple of 256 or 4096 is the best */ + + +#ifndef EEPROM_PAGE_SIZE +#define EEPROM_PAGE_SIZE 256 // Flash-ROM & Data-Flash page size for writing +#define EEPROM_BLOCK_SIZE 4096 // Flash-ROM & Data-Flash block size for erasing +#define EEPROM_MIN_ER_SIZE EEPROM_PAGE_SIZE // Data-Flash minimal size for erasing +//#define EEPROM_MIN_ER_SIZE EEPROM_BLOCK_SIZE // Flash-ROM minimal size for erasing +#define EEPROM_MIN_WR_SIZE 1 // Data-Flash minimal size for writing +#define EEPROM_MAX_SIZE 0x8000 // Data-Flash maximum size, 32KB +#endif +#ifndef FLASH_MIN_WR_SIZE +#define FLASH_MIN_WR_SIZE 4 // Flash-ROM minimal size for writing +#endif +#ifndef FLASH_ROM_MAX_SIZE +#define FLASH_ROM_MAX_SIZE 0x070000 // Flash-ROM maximum program size, 448KB +#endif + +#ifndef CMD_FLASH_ROM_SW_RESET +// CMD_* for caller from FlashROM or RAM, auto execute CMD_FLASH_ROM_SW_RESET before command + +#define CMD_FLASH_ROM_START_IO 0x00 // start FlashROM I/O, without parameter +#define CMD_FLASH_ROM_SW_RESET 0x04 // software reset FlashROM, without parameter +#define CMD_GET_ROM_INFO 0x06 // get information from FlashROM, parameter @Address,Buffer +#define CMD_GET_UNIQUE_ID 0x07 // get 64 bit unique ID, parameter @Buffer +#define CMD_FLASH_ROM_PWR_DOWN 0x0D // power-down FlashROM, without parameter +#define CMD_FLASH_ROM_PWR_UP 0x0C // power-up FlashROM, without parameter +#define CMD_FLASH_ROM_LOCK 0x08 // lock(protect)/unlock FlashROM data block, return 0 if success, parameter @StartAddr +// StartAddr: 0=unlock all, 1=lock boot code, 3=lock all code and data + +#define CMD_EEPROM_ERASE 0x09 // erase Data-Flash block, return 0 if success, parameter @StartAddr,Length +#define CMD_EEPROM_WRITE 0x0A // write Data-Flash data block, return 0 if success, parameter @StartAddr,Buffer,Length +#define CMD_EEPROM_READ 0x0B // read Data-Flash data block, parameter @StartAddr,Buffer,Length +#define CMD_FLASH_ROM_ERASE 0x01 // erase FlashROM block, return 0 if success, parameter @StartAddr,Length +#define CMD_FLASH_ROM_WRITE 0x02 // write FlashROM data block, minimal block is dword, return 0 if success, parameter @StartAddr,Buffer,Length +#define CMD_FLASH_ROM_VERIFY 0x03 // read FlashROM data block, minimal block is dword, return 0 if success, parameter @StartAddr,Buffer,Length +#endif + +#define ROM_CFG_MAC_ADDR 0x7F018 // address for MAC address information +#define ROM_CFG_BOOT_INFO 0x7DFF8 // address for BOOT information + +/** + * @brief execute Flash/EEPROM command, caller from FlashROM or RAM + * + * @param cmd - CMD_* for caller from FlashROM or RAM. + * @param StartAddr - Address of the data to be process. + * @param Buffer - Pointer to the buffer where data should be process, Must be aligned to 4 bytes. + * @param Length - Size of data to be process, in bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +extern uint32_t FLASH_EEPROM_CMD( uint8_t cmd, uint32_t StartAddr, void *Buffer, uint32_t Length ); + +/** + * @brief start FlashROM I/O + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define FLASH_ROM_START_IO( ) FLASH_EEPROM_CMD( CMD_FLASH_ROM_START_IO, 0, NULL, 0 ) + +/** + * @brief software reset FlashROM + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define FLASH_ROM_SW_RESET( ) FLASH_EEPROM_CMD( CMD_FLASH_ROM_SW_RESET, 0, NULL, 0 ) + +/** + * @brief get 6 bytes MAC address + * + * @param Buffer - Pointer to the buffer where data should be stored, Must be aligned to 4 bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define GetMACAddress(Buffer) FLASH_EEPROM_CMD( CMD_GET_ROM_INFO, ROM_CFG_MAC_ADDR, Buffer, 0 ) + +/** + * @brief get 8 bytes BOOT information + * + * @param Buffer - Pointer to the buffer where data should be stored, Must be aligned to 4 bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define GET_BOOT_INFO(Buffer) FLASH_EEPROM_CMD( CMD_GET_ROM_INFO, ROM_CFG_BOOT_INFO, Buffer, 0 ) + +/** + * @brief power-down FlashROM + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define FLASH_ROM_PWR_DOWN( ) FLASH_EEPROM_CMD( CMD_FLASH_ROM_PWR_DOWN, 0, NULL, 0 ) + +/** + * @brief power-up FlashROM + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define FLASH_ROM_PWR_UP( ) FLASH_EEPROM_CMD( CMD_FLASH_ROM_PWR_UP, 0, NULL, 0 ) + +/** + * @brief read Data-Flash data block + * + * @param StartAddr - Address of the data to be read. + * @param Buffer - Pointer to the buffer where data should be stored, Must be aligned to 4 bytes. + * @param Length - Size of data to be read, in bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define EEPROM_READ(StartAddr,Buffer,Length) FLASH_EEPROM_CMD( CMD_EEPROM_READ, StartAddr, Buffer, Length ) + +/** + * + * @param StartAddr - Address of the data to be erased. + * @param Length - Size of data to be erased, in bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define EEPROM_ERASE(StartAddr,Length) FLASH_EEPROM_CMD( CMD_EEPROM_ERASE, StartAddr, NULL, Length ) + +/** + * @brief write Data-Flash data block + * + * @param StartAddr - Address of the data to be written. + * @param Buffer - Pointer to the source buffer, Must be aligned to 4 bytes. + * @param Length - Size of data to be written, in bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define EEPROM_WRITE(StartAddr,Buffer,Length) FLASH_EEPROM_CMD( CMD_EEPROM_WRITE, StartAddr, Buffer, Length ) + +/** + * @brief erase FlashROM block + * + * @param StartAddr - Address of the data to be erased. + * @param Length - Size of data to be erased, in bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define FLASH_ROM_ERASE(StartAddr,Length) FLASH_EEPROM_CMD( CMD_FLASH_ROM_ERASE, StartAddr, NULL, Length ) + +/** + * @brief write FlashROM data block, minimal block is dword. + * + * @param StartAddr - Address of the data to be written. + * @param Buffer - Pointer to the source buffer, Must be aligned to 4 bytes. + * @param Length - Size of data to be written, in bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define FLASH_ROM_WRITE(StartAddr,Buffer,Length) FLASH_EEPROM_CMD( CMD_FLASH_ROM_WRITE, StartAddr, Buffer, Length ) + +/** + * @brief verify FlashROM data block, minimal block is dword. + * + * @param StartAddr - Address of the data to verify. + * @param Buffer - Pointer to the source buffer, Must be aligned to 4 bytes. + * @param Length - Size of data to verify, in bytes. + * + * @return 0-SUCCESS (!0)-FAILURE + */ +#define FLASH_ROM_VERIFY(StartAddr,Buffer,Length) FLASH_EEPROM_CMD( CMD_FLASH_ROM_VERIFY, StartAddr, Buffer, Length ) + diff --git a/nametag8_CH592/StdPeriphDriver/libISP592.a b/nametag8_CH592/StdPeriphDriver/libISP592.a new file mode 100644 index 0000000..4191b26 Binary files /dev/null and b/nametag8_CH592/StdPeriphDriver/libISP592.a differ diff --git a/nametag8_CH592/nametag8_CH592.launch b/nametag8_CH592/nametag8_CH592.launch new file mode 100644 index 0000000..00fc1d8 --- /dev/null +++ b/nametag8_CH592/nametag8_CH592.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nametag8_CH592/nametag8_CH592.wvproj b/nametag8_CH592/nametag8_CH592.wvproj new file mode 100644 index 0000000..bc40256 --- /dev/null +++ b/nametag8_CH592/nametag8_CH592.wvproj @@ -0,0 +1,2 @@ + am782"!qCw[E1| :巗聎51獑qH嫈搄; D;xMOS噴k稥棷(A檪(s*ǚcD繭芺Y攓uA$N绹8d娋道miA3粓wnt,罌怞 +<^*;Es%O<;x禯緧 ^ \ No newline at end of file diff --git a/nametag8_CH592/user/comm/soft_i2c_master.c b/nametag8_CH592/user/comm/soft_i2c_master.c new file mode 100644 index 0000000..66bba2e --- /dev/null +++ b/nametag8_CH592/user/comm/soft_i2c_master.c @@ -0,0 +1,128 @@ +/* + * soft_i2c.c + * + * Created on: Oct 11, 2024 + * Author: true + */ + + +// =================================================================================== +// Software I2C Master Functions for CH32X035/X034/X033 * v1.1 * +// modified for CH592 by true +// =================================================================================== +// +// Simple I2C bitbanging. ACK bit of the slave is ignored. Clock stretching by the +// slave is not allowed. External pull-up resistors (4k7 - 10k) are mandatory! +// +// Further information: https://github.com/wagiminator/ATtiny13-TinyOLEDdemo +// 2023 by Stefan Wagner: https://github.com/wagiminator +// +// This implementation requires 48MHz clock for 400KHz communication. + +#include "soft_i2c_master.h" + +// =================================================================================== +// I2C Delay +// =================================================================================== +#define I2C_DLY_TICKS_H (((F_CPU * 9) / (I2C_CLKRATE * 25)) - 41) +#define I2C_DLY_TICKS_L (((F_CPU * 16) / (I2C_CLKRATE * 25)) - 76) + +#if I2C_DLY_TICKS_H >= 1 + #define I2C_DELAY_H() DLY_ticks(I2C_DLY_TICKS_H) +#else + #define I2C_DELAY_H() +#endif + +#if I2C_DLY_TICKS_L >= 1 + #define I2C_DELAY_L() DLY_ticks(I2C_DLY_TICKS_L) +#else + #define I2C_DELAY_L() +#endif + +// =================================================================================== +// I2C Pin Macros +// =================================================================================== +#define I2C_SDA_HIGH() PIN_input(PIN_SDA) // release SDA -> pulled HIGH by resistor +#define I2C_SDA_LOW() PIN_output(PIN_SDA) // SDA LOW -> pulled LOW by MCU +#define I2C_SCL_HIGH() PIN_input(PIN_SCL) // release SCL -> pulled HIGH by resistor +#define I2C_SCL_LOW() PIN_output(PIN_SCL) // SCL LOW -> pulled LOW by MCU +#define I2C_SDA_READ() PIN_read(PIN_SDA) // read SDA pin +#define I2C_CLOCKOUT() I2C_DELAY_L();I2C_SCL_HIGH();I2C_DELAY_H();I2C_SCL_LOW() + +// =================================================================================== +// I2C Functions +// =================================================================================== + +// I2C init function +void I2C_init(void) { + PIN_input(PIN_SCL); // release SCL + PIN_input(PIN_SDA); // release SDA + PIN_low(PIN_SCL); // preset for SCL low + PIN_low(PIN_SDA); // preset for SDA low +} + +// I2C transmit one data byte to the slave, ignore ACK bit, no clock stretching allowed +void I2C_write(uint8_t data) { + uint8_t i; + for(i=8; i; i--, data<<=1) { // transmit 8 bits, MSB first + (data & 0x80) ? (I2C_SDA_HIGH()) : (I2C_SDA_LOW()); // SDA HIGH if bit is 1 + I2C_CLOCKOUT(); // clock out -> slave reads the bit + } + I2C_SDA_HIGH(); // release SDA for ACK bit of slave + I2C_CLOCKOUT(); // 9th clock pulse is for the ignored ACK bit +} + +// I2C start transmission +void I2C_start(uint8_t addr) { + I2C_SDA_LOW(); // start condition: SDA goes LOW first + I2C_DELAY_H(); // delay + I2C_SCL_LOW(); // start condition: SCL goes LOW second + I2C_write(addr); // send slave address +} + +// I2C restart transmission +void I2C_restart(uint8_t addr) { + I2C_SDA_HIGH(); // prepare SDA for HIGH to LOW transition + I2C_DELAY_H(); // delay + I2C_SCL_HIGH(); // restart condition: clock HIGH + I2C_start(addr); // start again +} + +// I2C stop transmission +void I2C_stop(void) { + I2C_SDA_LOW(); // prepare SDA for LOW to HIGH transition + I2C_DELAY_H(); // delay + I2C_SCL_HIGH(); // stop condition: SCL goes HIGH first + I2C_DELAY_H(); // delay + I2C_SDA_HIGH(); // stop condition: SDA goes HIGH second +} + +// I2C receive one data byte from the slave (ack=0 for last byte, ack>0 if more bytes to follow) +uint8_t I2C_read(uint8_t ack) { + uint8_t i; + uint8_t data = 0; // variable for the received byte + I2C_SDA_HIGH(); // release SDA -> will be toggled by slave + for(i=8; i; i--) { // receive 8 bits + data <<= 1; // bits shifted in right (MSB first) + I2C_DELAY_L(); // delay + I2C_SCL_HIGH(); // clock HIGH + I2C_DELAY_H(); // delay + if(I2C_SDA_READ()) data |= 1; // read bit + I2C_SCL_LOW(); // clock LOW -> slave prepares next bit + } + if(ack) I2C_SDA_LOW(); // pull SDA LOW to acknowledge (ACK) + I2C_CLOCKOUT(); // clock out -> slave reads ACK bit + return data; // return the received byte +} + +// Send data buffer via I2C bus and stop +void I2C_writeBuffer(uint8_t* buf, uint16_t len) { + while(len--) I2C_write(*buf++); // write buffer + I2C_stop(); // stop transmission +} + +// Read data via I2C bus to buffer and stop +void I2C_readBuffer(uint8_t* buf, uint16_t len) { + while(len--) *buf++ = I2C_read(len > 0); + I2C_stop(); +} diff --git a/nametag8_CH592/user/comm/soft_i2c_master.h b/nametag8_CH592/user/comm/soft_i2c_master.h new file mode 100644 index 0000000..4c88fbe --- /dev/null +++ b/nametag8_CH592/user/comm/soft_i2c_master.h @@ -0,0 +1,13 @@ +/* + * soft_i2c.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_COMM_SOFT_I2C_H_ +#define USER_COMM_SOFT_I2C_H_ + + + +#endif /* USER_COMM_SOFT_I2C_H_ */ diff --git a/nametag8_CH592/user/device/aw20xxx.c b/nametag8_CH592/user/device/aw20xxx.c new file mode 100644 index 0000000..7eee92c --- /dev/null +++ b/nametag8_CH592/user/device/aw20xxx.c @@ -0,0 +1,8 @@ +/* + * aw20xxx.c + * + * Created on: Oct 11, 2024 + * Author: true + */ + + diff --git a/nametag8_CH592/user/device/aw20xxx.h b/nametag8_CH592/user/device/aw20xxx.h new file mode 100644 index 0000000..d850ea4 --- /dev/null +++ b/nametag8_CH592/user/device/aw20xxx.h @@ -0,0 +1,13 @@ +/* + * aw20xxx.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_AW20XXX_H_ +#define USER_DEVICE_AW20XXX_H_ + + + +#endif /* USER_DEVICE_AW20XXX_H_ */ diff --git a/nametag8_CH592/user/device/ch32sub.c b/nametag8_CH592/user/device/ch32sub.c new file mode 100644 index 0000000..927735b --- /dev/null +++ b/nametag8_CH592/user/device/ch32sub.c @@ -0,0 +1,47 @@ +/* + * ch32sub.c + * + * the sub MCU is responsible for the following: + * - user buttons (complete handling / filtering) + * - rgb chip hw enable / disable + * - IrDA rx/tx and IrDA transciever enable / disable + * - accelerometer hardware interrupt + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#include "ch32sub.h" +#include "port_intr.h" + + +volatile uint8_t intr_flag = 0; + + +void ch32sub_isr() +{ + // we'll check what the MCU has to say when we're done processing + intr_flag = 1; +} + +void ch32sub_process() +{ + if (intr_flag) { + intr_flag = 0; + + // get interrupt flags + } +} + +void ch32sub_init() +{ + // configure interrupt pin as pull-up + // interrupt driven by CH32V003 is open drain active-lo + GPIOB_ModeCfg(SUB_INTR_PIN, GPIO_ModeIN_PU); + + // register interrupt handler + port_intr_cb_register(PORT_INTR_GPIOB, SUB_INTR_PIN_NR, ch32sub_isr); + + // configure interrupt to be rising edge + GPIOB_ITModeCfg(SUB_INTR_PIN, GPIO_ITMode_RiseEdge); +} diff --git a/nametag8_CH592/user/device/ch32sub.h b/nametag8_CH592/user/device/ch32sub.h new file mode 100644 index 0000000..44f4896 --- /dev/null +++ b/nametag8_CH592/user/device/ch32sub.h @@ -0,0 +1,33 @@ +/* + * ch32sub.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_CH32SUB_H_ +#define USER_DEVICE_CH32SUB_H_ + + +#include "CH59x_common.h" +#include + + + +#define SUB_INTR_PORT GPIOB +#define SUB_INTR_PIN GPIO_Pin_13 +#define SUB_INTR_PIN_NR 13 + +#define SUB_INT_BTN (1 << 0) +#define SUB_INT_ACCEL (1 << 1) +#define SUB_INT_UTX_DONE (1 << 4) +#define SUB_INT_URX_RCVD (1 << 5) + + + +void ch32sub_init(); +void ch32sub_process(); + + + +#endif /* USER_DEVICE_CH32SUB_H_ */ diff --git a/nametag8_CH592/user/device/eeprom16.c b/nametag8_CH592/user/device/eeprom16.c new file mode 100644 index 0000000..b45da0e --- /dev/null +++ b/nametag8_CH592/user/device/eeprom16.c @@ -0,0 +1,8 @@ +/* + * eeprom16.c + * + * Created on: Oct 11, 2024 + * Author: true + */ + + diff --git a/nametag8_CH592/user/device/eeprom16.h b/nametag8_CH592/user/device/eeprom16.h new file mode 100644 index 0000000..6b077d9 --- /dev/null +++ b/nametag8_CH592/user/device/eeprom16.h @@ -0,0 +1,13 @@ +/* + * eeprom16.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_EEPROM16_H_ +#define USER_DEVICE_EEPROM16_H_ + + + +#endif /* USER_DEVICE_EEPROM16_H_ */ diff --git a/nametag8_CH592/user/device/lis2dw.c b/nametag8_CH592/user/device/lis2dw.c new file mode 100644 index 0000000..9b64ff6 --- /dev/null +++ b/nametag8_CH592/user/device/lis2dw.c @@ -0,0 +1,8 @@ +/* + * lis2dw.c + * + * Created on: Oct 11, 2024 + * Author: true + */ + + diff --git a/nametag8_CH592/user/device/lis2dw.h b/nametag8_CH592/user/device/lis2dw.h new file mode 100644 index 0000000..ce46b13 --- /dev/null +++ b/nametag8_CH592/user/device/lis2dw.h @@ -0,0 +1,13 @@ +/* + * lis2dw.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_LIS2DW_H_ +#define USER_DEVICE_LIS2DW_H_ + + + +#endif /* USER_DEVICE_LIS2DW_H_ */ diff --git a/nametag8_CH592/user/device/ssd1306.c b/nametag8_CH592/user/device/ssd1306.c new file mode 100644 index 0000000..da7edc1 --- /dev/null +++ b/nametag8_CH592/user/device/ssd1306.c @@ -0,0 +1,8 @@ +/* + * ssd1306.c + * + * Created on: Oct 11, 2024 + * Author: true + */ + + diff --git a/nametag8_CH592/user/device/ssd1306.h b/nametag8_CH592/user/device/ssd1306.h new file mode 100644 index 0000000..c255905 --- /dev/null +++ b/nametag8_CH592/user/device/ssd1306.h @@ -0,0 +1,13 @@ +/* + * ssd1306.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_SSD1306_H_ +#define USER_DEVICE_SSD1306_H_ + + + +#endif /* USER_DEVICE_SSD1306_H_ */ diff --git a/nametag8_CH592/user/gat/gat_gpio.c b/nametag8_CH592/user/gat/gat_gpio.c new file mode 100644 index 0000000..4d697af --- /dev/null +++ b/nametag8_CH592/user/gat/gat_gpio.c @@ -0,0 +1,37 @@ +/* + * gat_gpio.c + * + * Created on: Oct 11, 2024 + * Author: true + */ + + +#include "gat_gpio.h" + + + +uint8_t gat_id = 0xff; + + + +static void gat_gpio_idle_lo() +{ + GPIOB_ModeCfg(GAT_GPIO_PIN_GP1 | GAT_GPIO_PIN_GP2, GPIO_ModeIN_PD); +} + +void gat_gpio_init() +{ + uint8_t lo, hi; + + // at startup, configure each GPIO as input float. + GPIOB_ModeCfg(GAT_GPIO_PIN_GP1 | GAT_GPIO_PIN_GP2, GPIO_ModeIN_Floating); + + // get ID from GPIO pins + lo = (GPIOB_ReadPort() & GAT_GPIO_PIN_GP1) ? 1 : 0; + hi = (GPIOB_ReadPort() & GAT_GPIO_PIN_GP2) ? 1 : 0; + + gat_id = (hi << 1) | lo; + + // configure as weak pulldowns + gat_gpio_idle_lo(); +} diff --git a/nametag8_CH592/user/gat/gat_gpio.h b/nametag8_CH592/user/gat/gat_gpio.h new file mode 100644 index 0000000..9527c7d --- /dev/null +++ b/nametag8_CH592/user/gat/gat_gpio.h @@ -0,0 +1,30 @@ +/* + * gat_gpio.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_GAT_GAT_GPIO_H_ +#define USER_GAT_GAT_GPIO_H_ + + +#include "CH59x_common.h" +#include + + + +#define GAT_GPIO_PORT GPIOB +#define GAT_GPIO_PIN_GP1 GPIO_Pin_7 +#define GAT_GPIO_PIN_GP2 GPIO_Pin_4 + + + +extern uint8_t gat_id; + + + +void gat_gpio_init(); + + +#endif /* USER_GAT_GAT_GPIO_H_ */ diff --git a/nametag8_CH592/user/gat/gat_i2c.c b/nametag8_CH592/user/gat/gat_i2c.c new file mode 100644 index 0000000..1949251 --- /dev/null +++ b/nametag8_CH592/user/gat/gat_i2c.c @@ -0,0 +1,14 @@ +/* + * gat_i2c.c + * + * Created on: Oct 11, 2024 + * Author: true + * + * implements a shoddy i2c slave. + * maximum speed 100KHz tested. + */ + +void soft_i2c_slave_irq_cb() +{ + +} diff --git a/nametag8_CH592/user/gat/gat_i2c.h b/nametag8_CH592/user/gat/gat_i2c.h new file mode 100644 index 0000000..6f3b95a --- /dev/null +++ b/nametag8_CH592/user/gat/gat_i2c.h @@ -0,0 +1,13 @@ +/* + * gat_i2c.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_GAT_GAT_I2C_H_ +#define USER_GAT_GAT_I2C_H_ + + + +#endif /* USER_GAT_GAT_I2C_H_ */ diff --git a/nametag8_CH592/user/main.c b/nametag8_CH592/user/main.c new file mode 100644 index 0000000..73653d8 --- /dev/null +++ b/nametag8_CH592/user/main.c @@ -0,0 +1,143 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : Main.c + * Author : WCH + * Version : V1.0 + * Date : 2020/08/06 + * Description : 串口1收发演示 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH59x_common.h" + +#include "port_intr.h" +#include "gat/gat_gpio.h" +#include "device/ch32sub.h" + + + +void ch59x_xtal_conf() +{ + HSECFG_Current(HSE_RCur_125); + HSECFG_Capacitance(HSECap_14p); +} + +uint8_t TxBuff[] = "This is a tx exam\r\n"; +uint8_t RxBuff[100]; +uint8_t trigB; + +/********************************************************************* + * @fn main + * + * @brief 主函数 + * + * @return none + */ +int main() +{ + //uint8_t len; + + // configure clock + ch59x_xtal_conf(); + SetSysClock(CLK_SOURCE_PLL_32MHz); + + // enable DC-DC converter + PWR_DCDCCfg(ENABLE); + + // configure port-based interrupts + port_intr_init(); + + // configure aux MCU initial settings, attention interrupt + ch32sub_init(); + + // configure GAT aux GPIOs, get gat ID + gat_gpio_init(); + // configure GAT i2c slave + + +/* + // 配置串口1：先配置IO口模式，再配置串口 + GPIOA_SetBits(GPIO_Pin_9); + GPIOA_ModeCfg(GPIO_Pin_8, GPIO_ModeIN_PU); // RXD-配置上拉输入 + GPIOA_ModeCfg(GPIO_Pin_9, GPIO_ModeOut_PP_5mA); // TXD-配置推挽输出，注意先让IO口输出高电平 + UART1_DefInit(); + +#if 1 // 测试串口发送字符串 + UART1_SendString(TxBuff, sizeof(TxBuff)); + +#endif + +#if 1 // 查询方式：接收数据后发送出去 + while(1) + { + len = UART1_RecvString(RxBuff); + if(len) + { + UART1_SendString(RxBuff, len); + } + } + +#endif + +#if 0 // 中断方式：接收数据后发送出去 + UART1_ByteTrigCfg(UART_7BYTE_TRIG); + trigB = 7; + UART1_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_LINE_STAT); + PFIC_EnableIRQ(UART1_IRQn); +#endif +*/ + + while(1) { + // only care about aux MCU when all other processing is done + ch32sub_process(); + } +} + +/********************************************************************* + * @fn UART1_IRQHandler + * + * @brief UART1中断函数 + * + * @return none + */ +__INTERRUPT +__HIGH_CODE +void UART1_IRQHandler(void) +{ + /* + volatile uint8_t i; + + switch(UART1_GetITFlag()) + { + case UART_II_LINE_STAT: // 线路状态错误 + { + UART1_GetLinSTA(); + break; + } + + case UART_II_RECV_RDY: // 数据达到设置触发点 + for(i = 0; i != trigB; i++) + { + RxBuff[i] = UART1_RecvByte(); + UART1_SendByte(RxBuff[i]); + } + break; + + case UART_II_RECV_TOUT: // 接收超时，暂时一帧数据接收完成 + i = UART1_RecvString(RxBuff); + UART1_SendString(RxBuff, i); + break; + + case UART_II_THR_EMPTY: // 发送缓存区空，可继续发送 + break; + + case UART_II_MODEM_CHG: // 只支持串口0 + break; + + default: + break; + } + */ +} diff --git a/nametag8_CH592/user/port_intr.c b/nametag8_CH592/user/port_intr.c new file mode 100644 index 0000000..c0227b1 --- /dev/null +++ b/nametag8_CH592/user/port_intr.c @@ -0,0 +1,63 @@ +/* + * port_intr.c + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#include "CH59x_common.h" +#include "port_intr.h" + +#include + + + +static void (*cb[2][24])(void) = {0}; + + + +void port_intr_cb_register(uint8_t port, uint8_t idx, void (*fn)(void)) +{ + if (idx >= 24) return; + if (port > 2) return; + + cb[port][idx] = fn; +} + +void port_intr_init() +{ + +} + + + +/* interrupt handlers */ +__INTERRUPT +__HIGH_CODE +void GPIOA_IRQHandler(void) +{ + +} + +__INTERRUPT +__HIGH_CODE +void GPIOB_IRQHandler(void) +{ + uint8_t i; + uint16_t flag = R16_PB_INT_IF; + + // high priority actions + // none. + + // general purpose fallback + for (i = 0; i < 24; i++) { + if (flag & (1 << i)) { + if (cb[PORT_INTR_GPIOB][i]) { + cb[PORT_INTR_GPIOB][i](); + } + } + } + + // clear flags + R16_PB_INT_IF = flag; +} diff --git a/nametag8_CH592/user/port_intr.h b/nametag8_CH592/user/port_intr.h new file mode 100644 index 0000000..b432bb2 --- /dev/null +++ b/nametag8_CH592/user/port_intr.h @@ -0,0 +1,23 @@ +/* + * port_intr.h + * + * Created on: Oct 11, 2024 + * Author: true + */ + +#ifndef USER_PORT_INTR_H_ +#define USER_PORT_INTR_H_ + + + +#define PORT_INTR_GPIOA 0 +#define PORT_INTR_GPIOB 1 + + + +void port_intr_init(); +void port_intr_cb_register(uint8_t port, uint8_t idx, void (*fn)(void)); + + + +#endif /* USER_PORT_INTR_H_ */ diff --git a/nametag8_V003/Core/core_riscv.c b/nametag8_V003/Core/core_riscv.c new file mode 100644 index 0000000..d08ce22 --- /dev/null +++ b/nametag8_V003/Core/core_riscv.c @@ -0,0 +1,276 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V2 Core Peripheral Access Layer Source File for CH32V003 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined(__CC_ARM) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined(__ICCARM__) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined(__GNUC__) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined(__TASKING__) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mstatus": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""misa" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile("csrw misa, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mtvec": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile("csrw mtvec, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mscratch" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mepc" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile("csrw mepc, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mcause": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile("csrw mcause, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mvendorid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""marchid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mimpid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mhartid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0,""sp": "=r"(result):); + return (result); +} diff --git a/nametag8_V003/Core/core_riscv.h b/nametag8_V003/Core/core_riscv.h new file mode 100644 index 0000000..c44a333 --- /dev/null +++ b/nametag8_V003/Core/core_riscv.h @@ -0,0 +1,401 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.1 + * Date : 2023/12/21 + * Description : RISC-V V2 Core Peripheral Access Layer Header File for CH32V003 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint32_t CNT; + uint32_t RESERVED0; + __IO uint32_t CMP; + uint32_t RESERVED1; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + + +/********************************************************************* + * @fn __enable_irq + * This function is only used for Machine mode. + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * This function is only used for Machine mode. + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6] - Sub priority + * bit[5:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:6] - Sub priority + * bit[5:0] - Reserve + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 1) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif/* __CORE_RISCV_H__ */ + + + + + diff --git a/nametag8_V003/Debug/debug.c b/nametag8_V003/Debug/debug.c new file mode 100644 index 0000000..896a94a --- /dev/null +++ b/nametag8_V003/Debug/debug.c @@ -0,0 +1,242 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE00000F4) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE00000F8) + +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_us; + + SysTick->CMP = i; + SysTick->CNT = 0; + SysTick->CTLR |=(1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CNT = 0; + SysTick->CTLR |=(1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)); + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if (DEBUG == DEBUG_UART1_NoRemap) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap1_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap2) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_PartialRemap2_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOD, &GPIO_InitStructure); + +#elif (DEBUG == DEBUG_UART1_Remap3) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_FullRemap_USART1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); +} + +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length. + * + * @return size - Data length + */ +__attribute__((used)) +int _write(int fd, char *buf, int size) +{ + int i = 0; + int writeSize = size; +#if (SDI_PRINT == SDI_PR_OPEN) + do + { + + /** + * data0 data1 8 bytes + * data0 The lowest byte storage length, the maximum is 7 + * + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + +#else + + for(i = 0; i < size; i++){ + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); + } + + +#endif + return writeSize; +} + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +__attribute__((used)) +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + + + diff --git a/nametag8_V003/Debug/debug.h b/nametag8_V003/Debug/debug.h new file mode 100644 index 0000000..367c668 --- /dev/null +++ b/nametag8_V003/Debug/debug.h @@ -0,0 +1,52 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : debug.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for UART + * Printf , Delay functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include + +/* UART Printf Definition */ +#define DEBUG_UART1_NoRemap 1 //Tx-PD5 +#define DEBUG_UART1_Remap1 2 //Tx-PD0 +#define DEBUG_UART1_Remap2 3 //Tx-PD6 +#define DEBUG_UART1_Remap3 4 //Tx-PC0 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1_NoRemap +#endif + +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + +void Delay_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); +void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DEBUG_H */ diff --git a/nametag8_V003/Ld/Link.ld b/nametag8_V003/Ld/Link.ld new file mode 100644 index 0000000..d25e60d --- /dev/null +++ b/nametag8_V003/Ld/Link.ld @@ -0,0 +1,159 @@ +ENTRY( _start ) + +__stack_size = 256; + +PROVIDE( _stack_size = __stack_size ); + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2K +} + +SECTIONS +{ + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + . = ALIGN(4); + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/nametag8_V003/Peripheral/inc/ch32v00x.h b/nametag8_V003/Peripheral/inc/ch32v00x.h new file mode 100644 index 0000000..43eb76e --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x.h @@ -0,0 +1,2201 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/28 + * Description : CH32V00x Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_H +#define __CH32V00x_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz */ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)24000000) /* Value of the Internal oscillator in Hz */ + +/* CH32V00x Standard Peripheral Library version number */ +#define __CH32V00x_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __CH32V00x_STDPERIPH_VERSION_SUB (0x09) /* [7:0] sub version */ +#define __CH32V00x_STDPERIPH_VERSION ( (__CH32V00x_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32V00x_STDPERIPH_VERSION_SUB << 0)) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + FLASH_IRQn = 18, /* FLASH global Interrupt */ + RCC_IRQn = 19, /* RCC global Interrupt */ + EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */ + AWU_IRQn = 21, /* AWU global Interrupt */ + DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 29, /* ADC global Interrupt */ + I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */ + USART1_IRQn = 32, /* USART1 global Interrupt */ + SPI1_IRQn = 33, /* SPI1 global Interrupt */ + TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 38, /* TIM2 global Interrupt */ + +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn + +#include +#include +#include "../../user/system_ch32v00x.h" + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + __IO uint32_t DLYR; +} ADC_TypeDef; + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; + __IO uint32_t BOOT_MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + uint32_t RESERVED0; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; + __IO uint32_t AWUCSR; + __IO uint32_t AWUWR; + __IO uint32_t AWUPSC; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t RESERVED0; + __IO uint32_t RSTSCKR; +} RCC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint32_t CH1CVR; + __IO uint32_t CH2CVR; + __IO uint32_t CH3CVR; + __IO uint32_t CH4CVR; + __IO uint16_t BDTR; + uint16_t RESERVED13; + __IO uint16_t DMACFGR; + uint16_t RESERVED14; + __IO uint16_t DMAADR; + uint16_t RESERVED15; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define EXTEN_BASE ((uint32_t)0x40023800) + +#define VENDOR_CFG0_BASE ((uint32_t)0x1FFFF7D4) +#define CFG0_PLL_TRIM (VENDOR_CFG0_BASE) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ +#define ADC_CALVOLSELECT ((uint32_t)0x06000000) +#define ADC_CALVOLSELECT_0 ((uint32_t)0x02000000) +#define ADC_CALVOLSELECT_1 ((uint32_t)0x04000000) + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x03FF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x03FF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x03FF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x03FF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x03FF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x03FF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0xFFFFFFFF) /* Regular data */ + +/******************** Bit definition for ADC_DLYR register ********************/ +#define ADC_DLYR_DLYVLU ((uint32_t)0x1FF) +#define ADC_DLYR_DLYSRC ((uint32_t)0x200) + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_MODE ((uint16_t)0x4000) +#define FLASH_STATR_LOCK ((uint16_t)0x8000) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint16_t)0x0001) /* Programming */ +#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase 1KByte*/ +#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */ +#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FLOCK ((uint16_t)0x8000) +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 64Byte */ +#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 64Byte */ +#define FLASH_CTLR_BUF_LOAD ((uint32_t)0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST ((uint32_t)0x00080000) /* Buffer Reset */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) +#define FLASH_OBR_STANDY_RST ((uint16_t)0x0010) +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) +#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */ +#define FLASH_OBR_STATR_MODE ((uint16_t)0x0080) +#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH__BOOT_MODEKEYR register ******************/ +#define FLASH_BOOT_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_BOOT_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCKK ((uint32_t)0x00000100) + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP_1 ((uint32_t)0x00000080) +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_PA12_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_USART1_HIGH_BIT_REMAP ((uint32_t)0x00200000) +#define AFIO_PCFR1_I2C1_HIGH_BIT_REMAP ((uint32_t)0x00400000) +#define AFIO_PCFR1_TIM1_1_RM ((uint32_t)0x00800000) + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */ +#define AFIO_EXTICR1_EXTI4 ((uint16_t)0x0300) +#define AFIO_EXTICR1_EXTI5 ((uint16_t)0x0C00) +#define AFIO_EXTICR1_EXTI6 ((uint16_t)0x3000) +#define AFIO_EXTICR1_EXTI7 ((uint16_t)0xC000) + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */ + +#define AFIO_EXTICR1_EXTI4_PA ((uint16_t)0x0000) +#define AFIO_EXTICR1_EXTI4_PC ((uint16_t)0x0200) +#define AFIO_EXTICR1_EXTI4_PD ((uint16_t)0x0300) + +#define AFIO_EXTICR1_EXTI5_PA ((uint16_t)0x0000) +#define AFIO_EXTICR1_EXTI5_PC ((uint16_t)0x0800) +#define AFIO_EXTICR1_EXTI5_PD ((uint16_t)0x0C00) + +#define AFIO_EXTICR1_EXTI6_PA ((uint16_t)0x0000) +#define AFIO_EXTICR1_EXTI6_PC ((uint16_t)0x2000) +#define AFIO_EXTICR1_EXTI6_PD ((uint16_t)0x3000) + +#define AFIO_EXTICR1_EXTI7_PA ((uint16_t)0x0000) +#define AFIO_EXTICR1_EXTI7_PC ((uint16_t)0x8000) +#define AFIO_EXTICR1_EXTI7_PD ((uint16_t)0xC000) + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_PVDLevel_0 ((uint16_t)0x0000) +#define PWR_PVDLevel_1 ((uint16_t)0x0020) +#define PWR_PVDLevel_2 ((uint16_t)0x0040) +#define PWR_PVDLevel_3 ((uint16_t)0x0060) +#define PWR_PVDLevel_4 ((uint16_t)0x0080) +#define PWR_PVDLevel_5 ((uint16_t)0x00A0) +#define PWR_PVDLevel_6 ((uint16_t)0x00C0) +#define PWR_PVDLevel_7 ((uint16_t)0x00E0) + +/******************* Bit definition for PWR_AWUCSR register ********************/ +#define PWR_AWUCSR_AWUEN ((uint16_t)0x0002) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ + +/******************* Bit definition for PWR_AWUWR register ********************/ +#define PWR_AWUWR ((uint16_t)0x003F) + +/******************* Bit definition for PWR_AWUWR register ********************/ +#define PWR_AWUPSC ((uint16_t)0x000F) +#define PWR_AWUPSC_0 ((uint16_t)0x0000) +#define PWR_AWUPSC_2 ((uint16_t)0x0002) +#define PWR_AWUPSC_4 ((uint16_t)0x0003) +#define PWR_AWUPSC_8 ((uint16_t)0x0004) +#define PWR_AWUPSC_16 ((uint16_t)0x0005) +#define PWR_AWUPSC_32 ((uint16_t)0x0006) +#define PWR_AWUPSC_64 ((uint16_t)0x0007) +#define PWR_AWUPSC_128 ((uint16_t)0x0008) +#define PWR_AWUPSC_256 ((uint16_t)0x0009) +#define PWR_AWUPSC_512 ((uint16_t)0x000A) +#define PWR_AWUPSC_1024 ((uint16_t)0x000B) +#define PWR_AWUPSC_2048 ((uint16_t)0x000C) +#define PWR_AWUPSC_4096 ((uint16_t)0x000D) +#define PWR_AWUPSC_10240 ((uint16_t)0x000E) +#define PWR_AWUPSC_61440 ((uint16_t)0x000F) + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */ +#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */ +#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */ + +#define RCC_ADCPRE ((uint32_t)0x0000F800) /* ADCPRE[4:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_ADCPRE_2 ((uint32_t)0x00002000) +#define RCC_ADCPRE_3 ((uint32_t)0x00004000) +#define RCC_ADCPRE_4 ((uint32_t)0x00008000) + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ +#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register ******************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ + +#define EXTEN_OPA_EN ((uint32_t)0x00010000) +#define EXTEN_OPA_NSEL ((uint32_t)0x00020000) +#define EXTEN_OPA_PSEL ((uint32_t)0x00040000) + +#include "../../user/ch32v00x_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_adc.h b/nametag8_V003/Peripheral/inc/ch32v00x_adc.h new file mode 100644 index 0000000..2660802 --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_adc.h @@ -0,0 +1,175 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/20 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_ADC_H +#define __CH32V00x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) + +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) +#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9) + +/* ADC_sampling_time */ +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_9Cycles ((uint8_t)0x01) +#define ADC_SampleTime_15Cycles ((uint8_t)0x02) +#define ADC_SampleTime_30Cycles ((uint8_t)0x03) +#define ADC_SampleTime_43Cycles ((uint8_t)0x04) +#define ADC_SampleTime_57Cycles ((uint8_t)0x05) +#define ADC_SampleTime_73Cycles ((uint8_t)0x06) +#define ADC_SampleTime_241Cycles ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +/* ADC_calibration_voltage_definition */ +#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000) +#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) + +/* ADC_external_trigger_sources_delay_channels_definition */ +#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200) + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_StartCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL); +void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_ADC_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_dbgmcu.h b/nametag8_V003/Peripheral/inc/ch32v00x_dbgmcu.h new file mode 100644 index 0000000..b6290f3 --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_dbgmcu.h @@ -0,0 +1,38 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_dbgmcu.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * DBGMCU firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_DBGMCU_H +#define __CH32V00x_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* CFGR0 Register */ +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020) + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_DBGMCU_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_dma.h b/nametag8_V003/Peripheral/inc/ch32v00x_dma.h new file mode 100644 index 0000000..a4964f0 --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_dma.h @@ -0,0 +1,177 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_DMA_H +#define __CH32V00x_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_DMA_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_exti.h b/nametag8_V003/Peripheral/inc/ch32v00x_exti.h new file mode 100644 index 0000000..f371e3c --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_exti.h @@ -0,0 +1,78 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_exti.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * EXTI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_EXTI_H +#define __CH32V00x_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_EXTI_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_flash.h b/nametag8_V003/Peripheral/inc/ch32v00x_flash.h new file mode 100644 index 0000000..82384e9 --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_flash.h @@ -0,0 +1,138 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_flash.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : This file contains all the functions prototypes for the FLASH + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_FLASH_H +#define __CH32V00x_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +} FLASH_Status; + +/* Flash_Latency */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ + +/* Values to be used with CH32V00x devices (1page = 64Byte) */ +#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ +#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ +#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ +#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */ +#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ +#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ +#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ +#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ +#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ +#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ +#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ +#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ +#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ +#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ +#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ +#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* Option_Bytes_RST_ENandDT */ +#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ +#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ +#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ +#define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128us */ + +/* Option_Bytes_Power_ON_Start_Mode */ +#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */ +#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* System_Reset_Start_Mode */ +#define Start_Mode_USER ((uint32_t)0x00000000) +#define Start_Mode_BOOT ((uint32_t)0x00004000) + + +/*Functions used for all CH32V00x devices*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_BufReset(void); +void FLASH_BufLoad(uint32_t Address, uint32_t Data0); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address); +void SystemReset_StartMode(uint32_t Mode); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_FLASH_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_gpio.h b/nametag8_V003/Peripheral/inc/ch32v00x_gpio.h new file mode 100644 index 0000000..9880883 --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_gpio.h @@ -0,0 +1,132 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/02/27 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_GPIO_H +#define __CH32V00x_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_30MHz +} GPIOSpeed_TypeDef; + +#define GPIO_Speed_50MHz GPIO_Speed_30MHz + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ +#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_GPIO_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_i2c.h b/nametag8_V003/Peripheral/inc/ch32v00x_i2c.h new file mode 100644 index 0000000..cb1e629 --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_i2c.h @@ -0,0 +1,415 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_I2C_H +#define __CH32V00x_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode -----------------------*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef *I2Cx); +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32V03RM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32V00x_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_I2C_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_iwdg.h b/nametag8_V003/Peripheral/inc/ch32v00x_iwdg.h new file mode 100644 index 0000000..3fd8fbb --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_iwdg.h @@ -0,0 +1,50 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_iwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * IWDG firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_IWDG_H +#define __CH32V00x_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_IWDG_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_misc.h b/nametag8_V003/Peripheral/inc/ch32v00x_misc.h new file mode 100644 index 0000000..f488c8f --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_misc.h @@ -0,0 +1,74 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00X_MISC_H +#define __CH32V00X_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) +* interrupt nesting enable(CSR-0x804 bit1 = 1) +* priority - bit[7] - Preemption Priority +* bit[6] - Sub priority +* bit[5:0] - Reserve +* interrupt nesting disable(CSR-0x804 bit1 = 0) +* priority - bit[7:6] - Sub priority +* bit[5:0] - Reserve +*/ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#endif + + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_MISC_H */ + diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_opa.h b/nametag8_V003/Peripheral/inc/ch32v00x_opa.h new file mode 100644 index 0000000..cfdd6bd --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_opa.h @@ -0,0 +1,53 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_opa.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * OPA firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_OPA_H +#define __CH32V00x_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v00x.h" + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0 = 0, + CHP1 +} OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0 = 0, + CHN1 +} OPA_NSEL_TypeDef; + + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ +} OPA_InitTypeDef; + +void OPA_DeInit(void); +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); +void OPA_Cmd(FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_pwr.h b/nametag8_V003/Peripheral/inc/ch32v00x_pwr.h new file mode 100644 index 0000000..dec08c1 --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_pwr.h @@ -0,0 +1,78 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the PWR + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_PWR_H +#define __CH32V00x_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* PVD_detection_level */ +#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) + +#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE0 +#define PWR_PVDLevel_3V1 PWR_PVDLevel_MODE1 +#define PWR_PVDLevel_3V3 PWR_PVDLevel_MODE2 +#define PWR_PVDLevel_3V5 PWR_PVDLevel_MODE3 +#define PWR_PVDLevel_3V7 PWR_PVDLevel_MODE4 +#define PWR_PVDLevel_3V9 PWR_PVDLevel_MODE5 +#define PWR_PVDLevel_4V1 PWR_PVDLevel_MODE6 +#define PWR_PVDLevel_4V4 PWR_PVDLevel_MODE7 + +/* PWR_AWU_Prescaler */ +#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) +#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) +#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) +#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) +#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) +#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) +#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) +#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) +#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) +#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) +#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) +#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) +#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) +#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) +#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) + +/* STOP_mode_entry */ +#define PWR_STANDBYEntry_WFI ((uint8_t)0x01) +#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + +void PWR_DeInit(void); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_AutoWakeUpCmd(FunctionalState NewState); +void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler); +void PWR_AWU_SetWindowValue(uint8_t WindowValue); +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_PWR_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_rcc.h b/nametag8_V003/Peripheral/inc/ch32v00x_rcc.h new file mode 100644 index 0000000..39743db --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_rcc.h @@ -0,0 +1,154 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_RCC_H +#define __CH32V00x_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00010000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) +#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) +#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) +#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) +#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) +#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) +#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) +#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) +#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) +#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) +#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) +#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) +#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSICmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_RCC_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_spi.h b/nametag8_V003/Peripheral/inc/ch32v00x_spi.h new file mode 100644 index 0000000..b1ebc6b --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_spi.h @@ -0,0 +1,156 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/01 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_SPI_H +#define __CH32V00x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity + When using SPI slave mode to send data, the CPOL bit should be set to 1 */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1. + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + +void SPI_I2S_DeInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef *SPIx); +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_SPI_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_tim.h b/nametag8_V003/Peripheral/inc/ch32v00x_tim.h new file mode 100644 index 0000000..00fc36c --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_tim.h @@ -0,0 +1,509 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_TIM_H +#define __CH32V00x_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_TIM_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_usart.h b/nametag8_V003/Peripheral/inc/ch32v00x_usart.h new file mode 100644 index 0000000..a6be0db --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_usart.h @@ -0,0 +1,187 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the + * USART firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_USART_H +#define __CH32V00x_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_USART_H */ diff --git a/nametag8_V003/Peripheral/inc/ch32v00x_wwdg.h b/nametag8_V003/Peripheral/inc/ch32v00x_wwdg.h new file mode 100644 index 0000000..ebe3b37 --- /dev/null +++ b/nametag8_V003/Peripheral/inc/ch32v00x_wwdg.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_wwdg.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file contains all the functions prototypes for the WWDG + * firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V00x_WWDG_H +#define __CH32V00x_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V00x_WWDG_H */ diff --git a/nametag8_V003/Peripheral/src/ch32v00x_adc.c b/nametag8_V003/Peripheral/src/ch32v00x_adc.c new file mode 100644 index 0000000..5b03a77 --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_adc.c @@ -0,0 +1,1060 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the ADC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_Vcalint - ADC Channel9 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_3Cycles - Sample time equal to 3 cycles. + * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. + * ADC_SampleTime_15Cycles - Sample time equal to 15 cycles. + * ADC_SampleTime_30Cycles - Sample time equal to 30 cycles. + * ADC_SampleTime_43Cycles - Sample time equal to 43 cycles. + * ADC_SampleTime_57Cycles - Sample time equal to 57 cycles. + * ADC_SampleTime_73Cycles - Sample time equal to 73 cycles. + * ADC_SampleTime_241Cycles - Sample time equal to 241 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_CC3 - Timer1 capture compare3 selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_CC3 - Timer2 capture compare3 selected. + * ADC_ExternalTrigInjecConv_T2_CC4 - Timer2 capture compare4 selected. + * ADC_ExternalTrigInjecConv_Ext_PD1_PA2 - PD1 or PA2 selected. + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_Vcalint - ADC Channel9 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_3Cycles - Sample time equal to 3 cycles. + * ADC_SampleTime_9Cycles - Sample time equal to 9 cycles. + * ADC_SampleTime_15Cycles - Sample time equal to 15 cycles. + * ADC_SampleTime_30Cycles - Sample time equal to 30 cycles. + * ADC_SampleTime_43Cycles - Sample time equal to 43 cycles. + * ADC_SampleTime_57Cycles - Sample time equal to 57 cycles. + * ADC_SampleTime_73Cycles - Sample time equal to 73 cycles. + * ADC_SampleTime_241Cycles - Sample time equal to 241 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 10bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 10bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 10bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_Vrefint - ADC Channel8 selected. + * ADC_Channel_Vcalint - ADC Channel9 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return ITStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn ADC_Calibration_Vol + * + * @brief ADC calibration voltage. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_CALVOL - ADC calibration voltage. + * ADC_CALVOL_50PERCENT - 50% VDD. + * ADC_CALVOL_75PERCENT - 75% VDD. + * + * @return none + */ +void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL) +{ + ADCx->CTLR1 &= ~(uint32_t)(3<<25); + ADCx->CTLR1 |= ADC_CALVOL; +} + +/********************************************************************* + * @fn ADC_ExternalTrig_DLY + * + * @brief ADC external trigger sources delay channels and time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * channel - ADC external trigger sources delay channels. + * ADC_ExternalTrigRegul_DLY - External trigger sources regular. + * ADC_ExternalTrigInjec_DLY - External trigger sources injected. + * DelayTim - ADC external trigger sources delay time + * This parameter must range from 0 to 0x1FF. + * + * @return none + */ +void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim) +{ + ADCx->DLYR &= ~(uint32_t)(0x3FF); + ADCx->DLYR |= channel; + ADCx->DLYR |= DelayTim; +} + diff --git a/nametag8_V003/Peripheral/src/ch32v00x_dbgmcu.c b/nametag8_V003/Peripheral/src/ch32v00x_dbgmcu.c new file mode 100644 index 0000000..9bd2870 --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_dbgmcu.c @@ -0,0 +1,116 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_dbgmcu.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the DBGMCU firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF7C4) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF7C4) & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } +} +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32V003F4P6-0x003005x0 + * CH32V003F4U6-0x003105x0 + * CH32V003A4M6-0x003205x0 + * CH32V003J4M6-0x003305x0 + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF7C4 ); +} diff --git a/nametag8_V003/Peripheral/src/ch32v00x_dma.c b/nametag8_V003/Peripheral/src/ch32v00x_dma.c new file mode 100644 index 0000000..0605284 --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_dma.c @@ -0,0 +1,416 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the DMA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be + * 1 to 7 for DMA1 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + + DMA1->INTFCR = DMAy_FLAG; + +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + tmpreg = DMA1->INTFR; + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + DMA1->INTFCR = DMAy_IT; +} diff --git a/nametag8_V003/Peripheral/src/ch32v00x_exti.c b/nametag8_V003/Peripheral/src/ch32v00x_exti.c new file mode 100644 index 0000000..b3fd8ff --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_exti.c @@ -0,0 +1,182 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_exti.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the EXTI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/nametag8_V003/Peripheral/src/ch32v00x_flash.c b/nametag8_V003/Peripheral/src/ch32v00x_flash.c new file mode 100644 index 0000000..cf5634c --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_flash.c @@ -0,0 +1,1066 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_flash.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/15 + * Description : This file provides all the FLASH firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0xFFFFFFFC) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BUF_LOAD ((uint32_t)0x00040000) +#define CR_BUF_RST ((uint32_t)0x00080000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x4000) + +/* FLASH Size */ +#define Size_64B 0x40 +#define Size_1KB 0x400 + +/******************************************************************************** + * @fn FLASH_SetLatency + * + * @brief Sets the code latency value. + * + * @param FLASH_Latency - specifies the FLASH Latency value. + * FLASH_Latency_0 - FLASH Zero Latency cycle + * FLASH_Latency_1 - FLASH One Latency cycle + * FLASH_Latency_2 - FLASH Two Latency cycles + * + * @return None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + tmpreg = FLASH->ACTLR; + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + FLASH->ACTLR = tmpreg; +} + +/******************************************************************************** + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/******************************************************************************** + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return None + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/******************************************************************************** + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(1KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/******************************************************************************** + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + OB->RDPR = (uint16_t)rdptmp; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramWord + * + * @brief Programs a word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + + *(__IO uint16_t *)Address = (uint16_t)Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + tmp = Address + 2; + *(__IO uint16_t *)tmp = Data >> 16; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + else + { + FLASH->CTLR &= CR_PG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramHalfWord + * + * @brief Programs a half word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramOptionByteData + * + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTPG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRPR0 = WRP0_Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRPR1 = WRP1_Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_ReadOutProtection + * + * @brief Enables or disables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDPR = 0x00; + } + else + { + OB->RDPR = RDP_Key; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTER_Reset; + } + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * OB_RST - Selects the reset IO mode and Ignore delay time + * OB_RST_NoEN - Reset IO disable (PD7) + * OB_RST_EN_DT12ms - Reset IO enable (PD7) and Ignore delay time 12ms + * OB_RST_EN_DT1ms - Reset IO enable (PD7) and Ignore delay time 1ms + * OB_RST_EN_DT128us - Reset IO enable (PD7) and Ignore delay time 128us + * OB_PowerON_Start_Mode - Selects start mode after power on. + * OB_PowerON_Start_Mode_BOOT - from Boot after power on. + * OB_PowerON_Start_Mode_USER - from User after power on. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode) +{ + FLASH_Status status = FLASH_COMPLETE; + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STDBY | (uint16_t)(OB_RST | (uint16_t)(OB_PowerON_Start_Mode| (uint16_t)0xC2))); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_BufReset + * + * @brief Flash Buffer reset. + * + * @return none + */ +void FLASH_BufReset(void) +{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_BufLoad + * + * @brief Flash Buffer load(4Byte). + * + * @param Address - specifies the address to be programmed. + * Data0 - specifies the data0 to be programmed. + * + * @return none + */ +void FLASH_BufLoad(uint32_t Address, uint32_t Data0) +{ + if((Address >= ValidAddrStart) && (Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_PG; + *(__IO uint32_t *)(Address) = Data0; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + } +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 64Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; + } +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 64Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address) +{ + if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd)) + { + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + } +} + +/********************************************************************* + * @fn SystemReset_StartMode + * + * @brief Start mode after system reset. + * + * @param Mode - Start mode. + * Start_Mode_USER - USER start after system reset + * Start_Mode_BOOT - Boot start after system reset + * @return none + */ +void SystemReset_StartMode(uint32_t Mode) +{ + FLASH_Unlock(); + + FLASH->BOOT_MODEKEYR = FLASH_KEY1; + FLASH->BOOT_MODEKEYR = FLASH_KEY2; + + FLASH->STATR &= ~(1<<14); + if(Mode == Start_Mode_BOOT){ + FLASH->STATR |= (1<<14); + } + + FLASH_Lock(); +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%64 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_1KB, Size_64B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + do{ + if(Erase_Size == Size_1KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_64B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_1KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_1KB; + } + else if(Erase_Size == Size_64B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_64B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%64 == 0). + * Length - Erases Flash start Length(Length%64 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE( uint32_t StartAddr, uint32_t Length ) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_64B-1)) || (Length & (Size_64B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_1KB) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_64B) + { + Length0 = Length; + } + + /* Erase 1KB */ + if(Length0 >= Size_1KB) //front + { + Length = Length0; + if(Addr0 & (Size_1KB - 1)) + { + Length0 = Size_1KB - (Addr0 & (Size_1KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB); + } + + if(Length1 >= Size_1KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_1KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1))); + Length1 = (StartAddr + Length1) & (Size_1KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB); + } + + /* Erase 64B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 6), Size_64B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 6), Size_64B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%64 == 0). + * Length - Writes Flash start Length(Length%64 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE( uint32_t StartAddr, uint32_t *pbuf, uint32_t Length ) +{ + uint32_t i, adr; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_64B-1)) || (Length & (Size_64B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + adr = StartAddr; + i = Length >> 6; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + do{ + FLASH->CTLR |= CR_PAGE_PG; + FLASH->CTLR |= CR_BUF_RST; + while(FLASH->STATR & SR_BSY) + ; + size = 16; + while(size) + { + *(__IO uint32_t *)(StartAddr) = *(uint32_t *)pbuf; + FLASH->CTLR |= CR_BUF_LOAD; + while(FLASH->STATR & SR_BSY) + ; + + StartAddr += 4; + pbuf += 1; + size -= 1; + } + + FLASH->CTLR |= CR_PAGE_PG; + FLASH->ADDR = adr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + + adr += 64; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/nametag8_V003/Peripheral/src/ch32v00x_gpio.c b/nametag8_V003/Peripheral/src/ch32v00x_gpio.c new file mode 100644 index 0000000..b8b465c --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_gpio.c @@ -0,0 +1,477 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/09 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* MASK */ +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..7). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx: where x can be (A..D) to select the GPIO peripheral. + * + * @return The input port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..7). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..D) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_PartialRemap_I2C1 - I2C1 Partial Alternate Function mapping + * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping + * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping + * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_Remap_PA1_2 - PA1_2 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping + * GPIO_Remap_SDI_Disable - SDI Disabled + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + tmpreg = AFIO->PCFR1; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if((GPIO_Remap & 0x10000000) == 0x10000000) + { + tmpreg &= ~((1<<1) | (1<<22)); + tmpreg |= ~DBGAFR_SDI_MASK; + if(NewState != DISABLE) + { + tmpreg |= (GPIO_Remap & 0xEFFFFFFF); + } + + } + else if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg &= ~((1<<2) | (1<<21)); + tmpreg |= ~DBGAFR_SDI_MASK; + if(NewState != DISABLE) + { + tmpreg |= (GPIO_Remap & 0x7FFFFFFF); + } + + } + else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))/* SDI */ + { + tmpreg &= DBGAFR_SDI_MASK; + AFIO->PCFR1 &= DBGAFR_SDI_MASK; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)/* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SDI_MASK; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + } + else/* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SDI_MASK; + + if(NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + } + + + AFIO->PCFR1 = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..D). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..7). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)(3<<(GPIO_PinSource<<1))); + AFIO->EXTICR &= ~tmp; + AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1))); +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-up. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC, ENABLE); + chip = *( uint32_t * )0x1FFFF7C4 & (~0x000000F0); + switch(chip) + { + case 0x00320500: //CH32V003A4M6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ + |GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + case 0x00330500: //CH32V003J4M6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + break; + } + default: + { + break; + } + + } + +} + + + diff --git a/nametag8_V003/Peripheral/src/ch32v00x_i2c.c b/nametag8_V003/Peripheral/src/ch32v00x_i2c.c new file mode 100644 index 0000000..0bb0c82 --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_i2c.c @@ -0,0 +1,975 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the I2C firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + + + + + + + diff --git a/nametag8_V003/Peripheral/src/ch32v00x_iwdg.c b/nametag8_V003/Peripheral/src/ch32v00x_iwdg.c new file mode 100644 index 0000000..2473219 --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_iwdg.c @@ -0,0 +1,126 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_iwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : This file provides all the IWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while ((RCC->RSTSCKR & 0x2) == RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + + diff --git a/nametag8_V003/Peripheral/src/ch32v00x_misc.c b/nametag8_V003/Peripheral/src/ch32v00x_misc.c new file mode 100644 index 0000000..fb382d4 --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_misc.c @@ -0,0 +1,81 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : This file provides all the miscellaneous firmware functions . + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 2 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 1 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/nametag8_V003/Peripheral/src/ch32v00x_opa.c b/nametag8_V003/Peripheral/src/ch32v00x_opa.c new file mode 100644 index 0000000..24179ae --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_opa.c @@ -0,0 +1,82 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_opa.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the OPA firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + + +/********************************************************************* + * @fn OPA_DeInit + * + * @brief Deinitializes the OPA peripheral registers to their default + * reset values. + * + * @return none + */ +void OPA_DeInit(void) +{ + EXTEN->EXTEN_CTR &= ~(uint32_t)(7 << 16); +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmp = 0; + tmp = EXTEN->EXTEN_CTR; + tmp &= ~(uint32_t)(3<<17); + tmp |= (OPA_InitStruct->PSEL << 18) | (OPA_InitStruct->NSEL << 17); + EXTEN->EXTEN_CTR = tmp; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->NSEL = CHN0; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + EXTEN->EXTEN_CTR |= (uint32_t)(1 << 16); + } + else + { + EXTEN->EXTEN_CTR &= ~(uint32_t)(1 << 16); + } +} diff --git a/nametag8_V003/Peripheral/src/ch32v00x_pwr.c b/nametag8_V003/Peripheral/src/ch32v00x_pwr.c new file mode 100644 index 0000000..ac23650 --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_pwr.c @@ -0,0 +1,213 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the PWR firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) +#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_MODE0 - PVD detection level set to mode 0. + * PWR_PVDLevel_MODE1 - PVD detection level set to mode 1. + * PWR_PVDLevel_MODE2 - PVD detection level set to mode 2. + * PWR_PVDLevel_MODE3 - PVD detection level set to mode 3. + * PWR_PVDLevel_MODE4 - PVD detection level set to mode 4. + * PWR_PVDLevel_MODE5 - PVD detection level set to mode 5. + * PWR_PVDLevel_MODE6 - PVD detection level set to mode 6. + * PWR_PVDLevel_MODE7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_AutoWakeUpCmd + * + * @brief Enables or disables the Auto WakeUp functionality. + * + * @param NewState - new state of the Auto WakeUp functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_AutoWakeUpCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->AWUCSR |= (1 << 1); + } + else + { + PWR->AWUCSR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn PWR_AWU_SetPrescaler + * + * @brief Sets the Auto Wake up Prescaler + * + * @param AWU_Prescaler - specifies the Auto Wake up Prescaler + * PWR_AWU_Prescaler_1 - AWU counter clock = LSI/1 + * PWR_AWU_Prescaler_2 - AWU counter clock = LSI/2 + * PWR_AWU_Prescaler_4 - AWU counter clock = LSI/4 + * PWR_AWU_Prescaler_8 - AWU counter clock = LSI/8 + * PWR_AWU_Prescaler_16 - AWU counter clock = LSI/16 + * PWR_AWU_Prescaler_32 - AWU counter clock = LSI/32 + * PWR_AWU_Prescaler_64 - AWU counter clock = LSI/64 + * PWR_AWU_Prescaler_128 - AWU counter clock = LSI/128 + * PWR_AWU_Prescaler_256 - AWU counter clock = LSI/256 + * PWR_AWU_Prescaler_512 - AWU counter clock = LSI/512 + * PWR_AWU_Prescaler_1024 - AWU counter clock = LSI/1024 + * PWR_AWU_Prescaler_2048 - AWU counter clock = LSI/2048 + * PWR_AWU_Prescaler_4096 - AWU counter clock = LSI/4096 + * PWR_AWU_Prescaler_10240 - AWU counter clock = LSI/10240 + * PWR_AWU_Prescaler_61440 - AWU counter clock = LSI/61440 + * + * @return none + */ +void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->AWUPSC & AWUPSC_MASK; + tmpreg |= AWU_Prescaler; + PWR->AWUPSC = tmpreg; +} + +/********************************************************************* + * @fn PWR_AWU_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x3F + * + * @return none + */ +void PWR_AWU_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = PWR->AWUWR & AWUWR_MASK; + + tmpreg |= WindowValue; + + PWR->AWUWR = tmpreg; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @param PWR_STANDBYEntry - specifies if STANDBY mode in entered with WFI or WFE instruction. + * PWR_STANDBYEntry_WFI - enter STANDBY mode with WFI instruction + * PWR_STANDBYEntry_WFE - enter STANDBY mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry) +{ + PWR->CTLR &= CTLR_DS_MASK; + PWR->CTLR |= PWR_CTLR_PDDS; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STANDBYEntry == PWR_STANDBYEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_PVDO - PVD Output + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + diff --git a/nametag8_V003/Peripheral/src/ch32v00x_rcc.c b/nametag8_V003/Peripheral/src/ch32v00x_rcc.c new file mode 100644 index 0000000..690d0da --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_rcc.c @@ -0,0 +1,771 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/03/18 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFFEFFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; +static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; + RCC->INTR = 0x009F0000; + + RCC_AdjustHSICalibrationValue(0x10); +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_MUL2 - HSI oscillator clock*2 + * selected as PLL clock entry. + * RCC_PLLSource_HSE_MUL2 - HSE oscillator clock*2 + * selected as PLL clock entry. + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + uint8_t tmp = 0; + + tmp = *( uint8_t * )CFG0_PLL_TRIM; + + if(tmp != 0xFF) + { + if((RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK) && ((RCC->CFGR0 & (1<<16)) == RCC_PLLSource_HSI_MUL2)) + { + RCC_AdjustHSICalibrationValue((tmp & 0x1F)); + } + else + { + RCC_AdjustHSICalibrationValue(0x10); + } + } + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5. + * RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6. + * RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * RCC_PCLK2_Div12 - ADC clock = PCLK2/12. + * RCC_PCLK2_Div16 - ADC clock = PCLK2/16. + * RCC_PCLK2_Div24 - ADC clock = PCLK2/24. + * RCC_PCLK2_Div32 - ADC clock = PCLK2/32. + * RCC_PCLK2_Div48 - ADC clock = PCLK2/48. + * RCC_PCLK2_Div64 - ADC clock = PCLK2/64. + * RCC_PCLK2_Div96 - ADC clock = PCLK2/96. + * RCC_PCLK2_Div128 - ADC clock = PCLK2/128. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + if(pllsource == 0x00) + { + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE * 2; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * 2; + } + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + + if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; + } + else + { + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + } + + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 11; + tmp = ((tmp & 0x18) >> 3) | ((tmp & 0x7) << 2); + + if((tmp & 0x13) >= 4) + { + tmp -= 12; + } + else + { + tmp &= 0x3; + } + + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_SRAM. + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_PWR. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK - PLL clock selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + + + diff --git a/nametag8_V003/Peripheral/src/ch32v00x_spi.c b/nametag8_V003/Peripheral/src/ch32v00x_spi.c new file mode 100644 index 0000000..f4f05ca --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_spi.c @@ -0,0 +1,517 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the SPI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * When using SPI slave mode to send data, the CPOL bit should be set to 1. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /*"SPI_FirstBit_LSB" not support SPI slave mode*/ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI interrupts. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx DMA interface. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_DMAReq - specifies the SPI DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx peripheral. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI flag is set or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * I2S_FLAG_UDR - Underrun Error flag. + * I2S_FLAG_CHSIDE - Channel Side flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * I2S_IT_UDR - Underrun Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} + + + + + + diff --git a/nametag8_V003/Peripheral/src/ch32v00x_tim.c b/nametag8_V003/Peripheral/src/ch32v00x_tim.c new file mode 100644 index 0000000..1bfdcac --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_tim.c @@ -0,0 +1,2367 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/25 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if(TIMx == TIM1) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if(TIMx == TIM1) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/********************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values . + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 2 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return SET or RESET. + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 2 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 2 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 3 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 3 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 4 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 4 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_IndicateCaptureLevelCmd + * + * @brief Enables or disables the TIMx capture level indication. + * + * @param TIMx - where x can be 1 to 2 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState) + { + TIMx->CTLR1 |= (1<<15); + } + else{ + TIMx->CTLR1 &= ~(1<<15); + } +} + diff --git a/nametag8_V003/Peripheral/src/ch32v00x_usart.c b/nametag8_V003/Peripheral/src/ch32v00x_usart.c new file mode 100644 index 0000000..1090186 --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_usart.c @@ -0,0 +1,796 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the USART firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else + { + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values . + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values . + * + * @param USARTx - where x can be to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_OverSampling8Cmd + * + * @brief Enables or disables the USART's 8x oversampling mode. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @return none + */ +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_OVER8_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_OVER8_Reset; + } +} + +/********************************************************************* + * @fn USART_OneBitMethodCmd + * + * @brief Enables or disables the USART's one bit sampling method. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_ONEBITE_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/nametag8_V003/Peripheral/src/ch32v00x_wwdg.c b/nametag8_V003/Peripheral/src/ch32v00x_wwdg.c new file mode 100644 index 0000000..dea550e --- /dev/null +++ b/nametag8_V003/Peripheral/src/ch32v00x_wwdg.c @@ -0,0 +1,141 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_wwdg.c + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : This file provides all the WWDG firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include +#include + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/nametag8_V003/Startup/startup_ch32v00x.S b/nametag8_V003/Startup/startup_ch32v00x.S new file mode 100644 index 0000000..da170db --- /dev/null +++ b/nametag8_V003/Startup/startup_ch32v00x.S @@ -0,0 +1,166 @@ +;/********************************** (C) COPYRIGHT ******************************* +;* File Name : startup_ch32v00x.s +;* Author : WCH +;* Version : V1.0.1 +;* Date : 2023/12/11 +;* Description : vector table for eclipse toolchain. +;********************************************************************************* +;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +;* Attention: This software (modified or not) and binary are used for +;* microcontroller manufactured by Nanjing Qinheng Microelectronics. +;*******************************************************************************/ + + .section .init, "ax", @progbits + .globl _start + .align 2 +_start: + .option norvc; + j handle_reset + .word 0 + .word NMI_Handler /* NMI Handler */ + .word HardFault_Handler /* Hard Fault Handler */ + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SysTick_Handler /* SysTick Handler */ + .word 0 + .word SW_Handler /* SW Handler */ + .word 0 + /* External Interrupts */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word FLASH_IRQHandler /* Flash */ + .word RCC_IRQHandler /* RCC */ + .word EXTI7_0_IRQHandler /* EXTI Line 7..0 */ + .word AWU_IRQHandler /* AWU */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word USART1_IRQHandler /* USART1 */ + .word SPI1_IRQHandler /* SPI1 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + + .option rvc; + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler + .weak HardFault_Handler + .weak SysTick_Handler + .weak SW_Handler + .weak WWDG_IRQHandler + .weak PVD_IRQHandler + .weak FLASH_IRQHandler + .weak RCC_IRQHandler + .weak EXTI7_0_IRQHandler + .weak AWU_IRQHandler + .weak DMA1_Channel1_IRQHandler + .weak DMA1_Channel2_IRQHandler + .weak DMA1_Channel3_IRQHandler + .weak DMA1_Channel4_IRQHandler + .weak DMA1_Channel5_IRQHandler + .weak DMA1_Channel6_IRQHandler + .weak DMA1_Channel7_IRQHandler + .weak ADC1_IRQHandler + .weak I2C1_EV_IRQHandler + .weak I2C1_ER_IRQHandler + .weak USART1_IRQHandler + .weak SPI1_IRQHandler + .weak TIM1_BRK_IRQHandler + .weak TIM1_UP_IRQHandler + .weak TIM1_TRG_COM_IRQHandler + .weak TIM1_CC_IRQHandler + .weak TIM2_IRQHandler + +NMI_Handler: +HardFault_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI7_0_IRQHandler: +AWU_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +USART1_IRQHandler: +SPI1_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +1: + j 1b + + .section .text.handle_reset, "ax", @progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop +1: + la sp, _eusrstack +2: +/* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: +/* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: +/* Enable global interrupt and configure privileged mode */ + li t0, 0x1880 + csrw mstatus, t0 +/* Enable interrupt nesting and hardware stack */ + li t0, 0x3 + csrw 0x804, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ + la t0, _start + ori t0, t0, 3 + csrw mtvec, t0 + + jal SystemInit + la t0, main + csrw mepc, t0 + mret + diff --git a/nametag8_V003/nametag8_V003.launch b/nametag8_V003/nametag8_V003.launch new file mode 100644 index 0000000..f7a9ad5 --- /dev/null +++ b/nametag8_V003/nametag8_V003.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nametag8_V003/nametag8_V003.wvproj b/nametag8_V003/nametag8_V003.wvproj new file mode 100644 index 0000000..38fa8b9 Binary files /dev/null and b/nametag8_V003/nametag8_V003.wvproj differ diff --git a/nametag8_V003/user/ch32v00x_conf.h b/nametag8_V003/user/ch32v00x_conf.h new file mode 100644 index 0000000..ce626b7 --- /dev/null +++ b/nametag8_V003/user/ch32v00x_conf.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v00x_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/08/08 + * Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V00x_CONF_H +#define __CH32V00x_CONF_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ch32v00x_it.h" + + + +#endif /* __CH32V00x_CONF_H */ + + + + + diff --git a/nametag8_V003/user/ch32v00x_it.c b/nametag8_V003/user/ch32v00x_it.c new file mode 100644 index 0000000..8b29546 --- /dev/null +++ b/nametag8_V003/user/ch32v00x_it.c @@ -0,0 +1,80 @@ +/* + * ch32v003 interrupts + */ + +#include "ch32v00x_it.h" + +#include + +#include + +#include "device/btn.h" +#include "device/intr_out.h" +#include "device/irda.h" +#include "i2c_slave.h" + + + + +void NMI_Handler(void); //__attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void); //__attribute__((interrupt("WCH-Interrupt-fast"))); + + + +void NMI_Handler(void) +{ + while (1); +} + +void HardFault_Handler(void) +{ + while (1); +} + +void SysTick_Handler(void) +{ + // ---- PROCESS UI AND COMMS + + // button handler + btn_poll(); + + // irda timeout and retry + irda_process(); + + // clear comparison flag + SysTick->SR = 0; + + + // ---- DISABLE INTERRUPT + + // see if any buttons are currently pushed + if ((BTN_PORT->INDR & BTN_PIN_MASK) != BTN_PIN_MASK) { + // yup, something is pushed, so keep the interrupt on + return; + } + + // see if irda is active + + // nothing is active, so shut down this interrupt + NVIC_DisableIRQ(SysTicK_IRQn); +} + +__attribute__((interrupt("WCH-Interrupt-fast"))) +void EXTI7_0_IRQHandler(void) +{ + if (EXTI_GetITStatus(EXTI_Line3)) { + // accelerometer has triggered. + // let the master know right away. + i2cs_append_flag(INT_ACCEL); + EXTI_ClearITPendingBit(EXTI_Line3); + } + + if (EXTI_GetITStatus(EXTI_Line0 | EXTI_Line4 | EXTI_Line5 | EXTI_Line6 | EXTI_Line7)) { + // button is pushed. + // enable main tick handler on button push. + // tick handler will sense when it isn't needed and shut itself off. + SysTick->SR = 0; + NVIC_EnableIRQ(SysTicK_IRQn); + EXTI_ClearITPendingBit(EXTI_Line0 | EXTI_Line4 | EXTI_Line5 | EXTI_Line6 | EXTI_Line7); + } +} diff --git a/nametag8_V003/user/ch32v00x_it.h b/nametag8_V003/user/ch32v00x_it.h new file mode 100644 index 0000000..fee9b56 --- /dev/null +++ b/nametag8_V003/user/ch32v00x_it.h @@ -0,0 +1,10 @@ +/* + * ch32v003 interrupts + */ + +#ifndef __CH32V00x_IT_H +#define __CH32V00x_IT_H + + + +#endif /* __CH32V00x_IT_H */ diff --git a/nametag8_V003/user/device/btn.c b/nametag8_V003/user/device/btn.c new file mode 100644 index 0000000..d37541d --- /dev/null +++ b/nametag8_V003/user/device/btn.c @@ -0,0 +1,170 @@ +/* + * Created on: Jul 27, 2024 + * + * generic button handler like I do on most of my projects + */ + +#include "btn.h" + +#include "intr_out.h" +#include "../i2c_slave.h" + +#include + + + + +struct Btn btn[BTN_COUNT] = {0}; + +static uint8_t set_interrupt = 0; + + + +static void update_i2c_reg(uint8_t idx) +{ + if (idx > BTN_COUNT) return; + + // set raw masks + i2cs_reg[REG_BTN1_MASK + idx] = btn[idx]._mask; + + // set interrupt line high if interrupt is enabled for the button + if (btn[idx]._mask & i2cs_reg[REG_BTN1_INT_ENABLE + idx]) { + set_interrupt = 1; + } +} + +void btn_push_cb(uint8_t idx) +{ + update_i2c_reg(idx); +} + +void btn_hold_cb(uint8_t idx) +{ + update_i2c_reg(idx); +} + +void btn_release_cb(uint8_t idx) +{ + update_i2c_reg(idx); +} + + +void btn_init() +{ + uint8_t i; + + EXTI_InitTypeDef exti = {0}; + + // it is assumed that GPIO is already configured for these pins + + // configure default setup + for (i = 0; i < BTN_COUNT; i++) { + btn[i]._mask = BTN_RELEASE; + } + + btn[0]._pintype = BTN1_PIN; + btn[1]._pintype = BTN2_PIN; + btn[2]._pintype = BTN3_PIN; + btn[3]._pintype = BTN4_PIN; + btn[4]._pintype = BTN5_PIN; + + GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource0); + GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource4); + GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource5); + GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource6); + GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource7); + + for (i = 0; i < BTN_COUNT; i++) { + // check buttons, and ignore if held + if (!(BTN_PORT->INDR & (1 << btn[i]._pintype))) { + btn[i]._mask |= BTN_IGNORE; + } + + // set initial callbacks + btn[i].cb_push = btn_push_cb; + btn[i].cb_hold = btn_hold_cb; + btn[i].cb_release = btn_release_cb; + + // set up exti line to fire interrupt when button is pushed + exti.EXTI_Line = (1 << btn[i]._pintype); + exti.EXTI_Mode = EXTI_Mode_Interrupt; + exti.EXTI_Trigger = EXTI_Trigger_Falling; + exti.EXTI_LineCmd = ENABLE; + EXTI_Init(&exti); + } + + // set default debounce + i2cs_reg[REG_BTN_DEBOUNCE_TIME] = BTN_DEBOUNCE; +} + +void btn_poll() +{ + uint8_t i; + uint8_t r; + uint8_t ignore; + + uint8_t pushed; + + for (i = 0; i < BTN_COUNT; i++) { + pushed = 0; + + ignore = btn[i]._mask & BTN_IGNORE; + r = BTN_PORT->INDR & (1 << (btn[i]._pintype & BTN_PIN_MASK)); + + // active low type buttons + if (!r && (btn[i]._pintype & BTN_ACTIVE_LO)) pushed = 1; + // active high type buttons + if (r && !(btn[i]._pintype & BTN_ACTIVE_LO)) pushed = 1; + + if (pushed) { + // hold counter + if (btn[i]._count < 0xffff) btn[i]._count++; + + // pushed long enough? + if (btn[i]._count < i2cs_reg[REG_BTN_DEBOUNCE_TIME]) continue; + + // first push? + if (!(btn[i]._mask & BTN_PUSH)) { + btn[i]._mask = BTN_PUSH | ignore; + if (btn[i].cb_push && !ignore) { + btn[i].cb_push(i); + btn[i]._mask |= (BTN_PUSH << 4); + } + } else if (btn[i]._count >= btn[i].hold) { + // held to count limit + + // if button is not repeatable, do not retrigger + if ((btn[i]._mask & BTN_HOLD) && !btn[i].repeat) continue; + + btn[i]._mask |= BTN_HOLD; + // call callback only if not in ignore state + if (btn[i].cb_hold && !ignore) { + btn[i].cb_hold(i); + btn[i]._mask |= (BTN_HOLD << 4); + } + + // apply repeat rate to count + if (btn[i].repeat > btn[i]._count) { + btn[i]._count = 0; + } else btn[i]._count -= btn[i].repeat; + } + } else { + // is not pushed + if (!(btn[i]._mask & BTN_RELEASE)) { + // note: release will remove ignore status + btn[i]._mask = BTN_RELEASE; + btn[i]._count = 0; + // call callback only if not in ignore state + if (btn[i].cb_release && !ignore) { + btn[i].cb_release(i); + btn[i]._mask |= (BTN_RELEASE << 4); + } + } + } + } + + if (set_interrupt) { + i2cs_append_flag(INT_BTN); + set_interrupt = 0; + } +} diff --git a/nametag8_V003/user/device/btn.h b/nametag8_V003/user/device/btn.h new file mode 100644 index 0000000..37ec08f --- /dev/null +++ b/nametag8_V003/user/device/btn.h @@ -0,0 +1,73 @@ +/* + * btn.h + * + * Created on: Jul 27, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_BTN_H_ +#define USER_DEVICE_BTN_H_ + + + +#include + + + +#define BTN_COUNT 4 +#define BTN_DEBOUNCE (12 >> 1) // debounce time in 2ms + +#define BTN_PORT GPIOC +#define BTN_MODE 0x80 + +#define BTN_PULL_UP (1 << 0) +#define BTN_PULL_DOWN (1 << 16) + +#define BTN_ACTIVE_LO 0xf1 +#define BTN_PIN_MASK 0xf1 + +#define BTN1_PIN 4 +#define BTN1_PUPD BTN_PULL_UP + +#define BTN2_PIN 5 +#define BTN2_PUPD BTN_PULL_UP + +#define BTN3_PIN 6 +#define BTN3_PUPD BTN_PULL_UP + +#define BTN4_PIN 7 +#define BTN4_PUPD BTN_PULL_UP + +#define BTN5_PIN 0 // side button +#define BTN5_PUPD BTN_PULL_UP + +#define BTN_PUSH (1 << 0) +#define BTN_HOLD (1 << 1) +#define BTN_RELEASE (1 << 2) +#define BTN_IGNORE (1 << 3) + + + +typedef struct Btn { + uint8_t _mask; + uint8_t _pintype; + uint16_t _count; // held counts + uint16_t hold; // initial hold + uint16_t repeat; // repeated hold + void (*cb_push)(uint8_t); + void (*cb_hold)(uint8_t); + void (*cb_release)(uint8_t); +} Btn; + + + +extern struct Btn btn[BTN_COUNT]; + + + +void btn_init(); +void btn_poll(); + + + +#endif /* USER_SRC_BTN_H_ */ diff --git a/nametag8_V003/user/device/intr_out.c b/nametag8_V003/user/device/intr_out.c new file mode 100644 index 0000000..16d06a2 --- /dev/null +++ b/nametag8_V003/user/device/intr_out.c @@ -0,0 +1,28 @@ +/* + * intr_out.c + * + * updates read-only registers and notifies the master + * when there are priority updates. + * + */ + +#include "i2c_slave.h" + + +void intr_init() +{ + EXTI_InitTypeDef exti = {0}; + + // set up exti line for when the accelerometer interrupt fires + GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource3); + exti.EXTI_Line = EXTI_Line3; + exti.EXTI_Mode = EXTI_Mode_Interrupt; + exti.EXTI_Trigger = EXTI_Trigger_Rising; + exti.EXTI_LineCmd = ENABLE; + EXTI_Init(&exti); +} + +void intr_process() +{ + +} diff --git a/nametag8_V003/user/device/intr_out.h b/nametag8_V003/user/device/intr_out.h new file mode 100644 index 0000000..301a4b7 --- /dev/null +++ b/nametag8_V003/user/device/intr_out.h @@ -0,0 +1,53 @@ +/* + * int_out.h + * + * Created on: Oct 12, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_INT_OUT_H_ +#define USER_DEVICE_INT_OUT_H_ + + + +#define INT_I2C_ADDR 0x5e + +#define INT_OUT_PORT GPIOA +#define INT_OUT_PIN GPIO_Pin_1 + +#define INT_ACCEL_PORT GPIOC +#define INT_ACCEL_PIN GPIO_Pin_3 + + +#define INT_OUT_SET() INT_OUT_PORT->BCR = INT_OUT_PIN +#define INT_OUT_CLEAR() INT_OUT_PORT->BSHR = INT_OUT_PIN + + + +#define INT_BTN (1 << 0) // user pressed / held / released a button + // set if per-button interrupt enabled for the action when action is taken + // cleared on writing 1 to bit offset in REG_INT_FLAGS_CLEAR or reading any REG_BTNx_MASK register + +#define INT_ACCEL (1 << 1) // accelerometer has interrupt + // set when accelerometer INT pin goes high + // cleared on writing 1 to bit offset in REG_INT_FLAGS_CLEAR + +#define INT_UTX_DONE (1 << 4) // queued transmission is complete + // set when a successful IrDA transmission has been performed + // cleared on writing 1 to bit offset in REG_INT_FLAGS_CLEAR + +#define INT_UTX_TIMEOUT (1 << 5) // queued transmission timed out; no receiver got our message + // set when transmission times out + // cleared on writing 1 to bit offset in REG_INT_FLAGS_CLEAR + +#define INT_UTX_ERROR (1 << 6) // queued transmission failed due to an error (bad payload, etc) + // set when the transmission timer has timed out + // cleared on writing 1 to bit offset in REG_INT_FLAGS_CLEAR + +#define INT_URX_RCVD (1 << 7) // received valid data packet + // set when a packet is received and passes validation checks + // cleared on writing 1 to bit offset in REG_INT_FLAGS_CLEAR + + + +#endif /* USER_DEVICE_INT_OUT_H_ */ diff --git a/nametag8_V003/user/device/irda.c b/nametag8_V003/user/device/irda.c new file mode 100644 index 0000000..1f3ca1d --- /dev/null +++ b/nametag8_V003/user/device/irda.c @@ -0,0 +1,373 @@ +/* + * irda.c + * + * had a nice protocol planned, but no time. so we bruteforce it + * + * transmitter will spew packets with the following data: + * 2-byte header 0x5aa5 + * 2-byte length, though messages cannot be longer than 248 bytes currently + * 2-byte checksum of message content + * message content + * + * if a receiver receives the data, and checksum passes, it will flash or something. + * receiver will respond with the following data: + * 2-byte header 0xa55a (swapped bytes from transmit header) + * 2-byte ascii 'OK' + * 2-byte 0xffff xor checksum of the sent content + * + * if the transmitter sees the OK packet with inverted checksum, it will flash or something. + * if transmitter sees anything else, it will be ignored and cleared. + * + * transmission is handled via DMA. + * reception is handled via interrupt. + * + */ + +#include "irda.h" + +#include "intr_out.h" +#include "../i2c_slave.h" + + + +static DMA_InitTypeDef tx_dma = {0}; + +static uint16_t irda_timeout; +static uint8_t irda_state; + +volatile uint8_t *irda_tx_buf; +uint16_t irda_tx_len; +uint16_t irda_tx_timer; +uint8_t irda_tx_hdr[6]; // contains header, length, and checksum + +volatile uint8_t *irda_rx_buf; +uint16_t irda_rx_len; // filled after receiving header +uint16_t irda_rx_csum; // filled after receiving header +uint16_t irda_rx_pos; +uint16_t irda_rx_timeout; +uint8_t irda_rx_hdr[6]; + + + +void irda_init() +{ + USART_InitTypeDef usart = {0}; + + IrDA_Shutdown(); + + // buffers + irda_tx_buf = &i2cs_reg[0x100]; + irda_rx_buf = &i2cs_reg[0x200]; + + // configure USART peripheral + usart.USART_BaudRate = 115200; + usart.USART_WordLength = USART_WordLength_8b; + usart.USART_StopBits = USART_StopBits_1; + usart.USART_Parity = USART_Parity_No; + usart.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + usart.USART_Mode = 0; // USART_Mode_Tx | USART_Mode_Rx; + USART_Init(USART1, &usart); + + USART_IrDACmd(USART1, ENABLE); + + // configure and enable USART interrupt + NVIC_SetPriority(USART1_IRQn, 2 << 6); + NVIC_EnableIRQ(USART1_IRQn); + + // configure transmitter DMA + DMA_DeInit(DMA1_Channel4); + tx_dma.DMA_PeripheralBaseAddr = (u32)(&USART1->DATAR); + tx_dma.DMA_DIR = DMA_DIR_PeripheralDST; + tx_dma.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + tx_dma.DMA_MemoryInc = DMA_MemoryInc_Enable; + tx_dma.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + tx_dma.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + tx_dma.DMA_Mode = DMA_Mode_Normal; + tx_dma.DMA_Priority = DMA_Priority_High; + tx_dma.DMA_M2M = DMA_M2M_Disable; + + + USART_DMACmd(USART1, USART_DMAReq_Tx, ENABLE); + + // configure and enable transmitter DMA complete interrupt + DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE); +} + +void irda_ena_tx() +{ + USART_ITConfig(USART1, USART_IT_RXNE, DISABLE); + + USART1->CTLR2 &= ~USART_CTLR1_RE; + USART1->CTLR2 |= USART_CTLR1_TE; +} + +void irda_ena_rx() +{ + USART1->CTLR2 &= ~USART_CTLR1_TE; + USART1->CTLR2 |= USART_CTLR1_RE; + + USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); +} + +uint16_t irda_csum(uint8_t *dat, uint16_t len) +{ + uint16_t i; + uint16_t csum = 0; + + for (i = 0; i < len; i++) { + csum += *dat++; + } + + return csum; +} + +// starts or restarts a transmission +void irda_restart_tx(uint8_t ack) +{ + uint16_t csum; + + if ((!i2cs_reg[REG_IRDA_WRITE_HI] && (i2cs_reg[REG_IRDA_WRITE_LO] <= 248)) || ack) { + // stop any transmit + USART_DMACmd(USART1, USART_DMAReq_Tx, DISABLE); + + if (!ack) { + // standard data header + irda_tx_hdr[0] = IRDA_HEADER_01; + irda_tx_hdr[1] = IRDA_HEADER_02; + irda_tx_hdr[2] = 0; + irda_tx_hdr[3] = i2cs_reg[REG_IRDA_WRITE_LO]; + + csum = irda_csum((uint8_t *)irda_tx_buf, irda_tx_hdr[3]); + irda_tx_hdr[4] = csum >> 8; + irda_tx_hdr[5] = csum & 0xff; + + // we'll try again after some time + irda_tx_timer = i2cs_reg[REG_IRDA_WRITE_RETRY] * 2; + + // set data length + irda_tx_len = i2cs_reg[REG_IRDA_WRITE_LO]; + } else { + // rx ack header + irda_tx_hdr[0] = IRDA_HEADER_02; + irda_tx_hdr[1] = IRDA_HEADER_01; + irda_tx_hdr[2] = 'O'; + irda_tx_hdr[3] = 'K'; + + irda_tx_hdr[4] = irda_rx_hdr[4] ^ 0xff; + irda_tx_hdr[5] = irda_rx_hdr[5] ^ 0xff; + + irda_tx_timer = 200 / 6; // acks are always sent 9 times + irda_tx_len = 0; + } + + // prepare the new write + tx_dma.DMA_MemoryBaseAddr = (uint32_t)irda_tx_hdr; + tx_dma.DMA_BufferSize = 6; + DMA_Init(DMA1_Channel4, &tx_dma); + + // then go for it + USART_DMACmd(USART1, USART_DMAReq_Tx, ENABLE); + } else { + // data to write is too long; set transmit error interrupt flag + i2cs_append_flag(INT_UTX_ERROR); + } +} + +void irda_stop() +{ + // disable all related internal peripherals + USART_ITConfig(USART1, USART_IT_RXNE, DISABLE); + USART_DMACmd(USART1, USART_DMAReq_Tx, DISABLE); + + USART_Cmd(USART1, DISABLE); + + // reset internal state + irda_state = IRDA_STATE_IDLE; + irda_timeout = 0; + + // disable the PHY + IrDA_Shutdown(); + + // reset register mode + i2cs_reg[REG_IRDA_MODE] = 0; +} + + +void irda_mode(uint8_t mode, uint16_t timeout) +{ + irda_state = mode; + + switch (mode) { + case IRDA_STATE_IDLE: { + // cancel any pending operations + irda_stop(); + break; + } + + case IRDA_STATE_TX_HEADER: { + IrDA_Enable(); + irda_ena_tx(); + + irda_timeout = timeout; + irda_restart_tx(0); + break; + } + case IRDA_STATE_TX_ACK: { + IrDA_Enable(); + irda_ena_tx(); + + irda_timeout = 300; // we only send acks for a little over a second + irda_restart_tx(1); + break; + } + + case IRDA_STATE_RX_DATA: + case IRDA_STATE_RX_ACK: { + irda_rx_pos = 0; + irda_rx_len = 0; + + IrDA_Enable(); + irda_ena_rx(); + + irda_timeout = timeout; + } + } +} + +void irda_process() +{ + if (!irda_timeout) { + switch (irda_state) { + case IRDA_STATE_TX_HEADER: + case IRDA_STATE_TX_BODY: + case IRDA_STATE_TX_ACK: { + // didn't complete in time; set timeout flag + i2cs_append_flag(INT_UTX_TIMEOUT); + break; + } + default: { + // receiving just doesn't send an interrupt + break; + } + } + irda_stop(); + return; + } + + irda_timeout--; + + switch (irda_state) { + case IRDA_STATE_TX_HEADER: + case IRDA_STATE_TX_BODY: + case IRDA_STATE_TX_ACK: { + if (!irda_tx_timer) { + irda_restart_tx((irda_state == IRDA_STATE_TX_ACK) ? 1 : 0); + } else { + irda_tx_timer--; + } + break; + } + + case IRDA_STATE_RX_DATA: + case IRDA_STATE_RX_ACK: { + if (irda_rx_pos) { + if (irda_rx_timeout) { + irda_rx_timeout--; + } else { + // we received some data but it didn't get completed + // so abort + irda_rx_pos = 0; + } + } + } + } +} + +void USART1_IRQHandler(void) +{ + uint16_t csum; + + // receive + if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET) { + if (irda_rx_pos <= 248+6) { + if (irda_rx_pos < 6) { + irda_rx_hdr[irda_rx_pos] = USART_ReceiveData(USART1); + } else { + irda_rx_buf[irda_rx_pos - 6] = USART_ReceiveData(USART1); + + if ((irda_rx_pos - 6) == irda_rx_len) { + // full packet received. validate the checksum + csum = irda_csum((uint8_t *)irda_rx_buf, irda_rx_len); + if (((csum >> 8) == irda_rx_hdr[2]) && ((csum & 0xff) == irda_rx_hdr[3])) { + // checksum matches! let the host to commit the data + i2cs_reg[REG_IRDA_READ_HI] = 0; + i2cs_reg[REG_IRDA_READ_LO] = irda_rx_len; + i2cs_append_flag(INT_URX_RCVD); + + // and let the transmitter know it was received successfully + irda_mode(IRDA_STATE_TX_ACK, 0); + + } + } + } + irda_rx_pos++; + + // validate the header + if (irda_rx_pos == 6) { + switch (irda_state) { + case IRDA_STATE_RX_DATA: { + // is the header valid? + if ((irda_rx_hdr[0] == IRDA_HEADER_01) && (irda_rx_hdr[1] == IRDA_HEADER_02)) { + // is the length valid? + if (!irda_rx_hdr[2] && (irda_rx_hdr[3] <= 248)) { + // good to go + irda_rx_len = irda_rx_hdr[3]; + irda_rx_csum = (irda_rx_hdr[4] << 8) | irda_rx_hdr[5]; + break; + } + } + + // something isn't valid; cancel this rx + irda_rx_pos = 0; + irda_rx_len = 0; + break; + } + case IRDA_STATE_RX_ACK: { + irda_rx_len = 0; + + // is the header valid? + if ((irda_rx_hdr[0] == IRDA_HEADER_02) && (irda_rx_hdr[1] == IRDA_HEADER_01)) { + // are the third and fourth bytes 'OK'? + if ((irda_rx_hdr[2] == 'O') && (irda_rx_hdr[3] == 'K')) { + // how about the checksum? + csum = (irda_tx_hdr[4] << 8) | irda_tx_hdr[5]; + csum ^= 0xffff; + if (csum == irda_rx_csum) { + // seems good; let the master know + irda_stop(); + i2cs_append_flag(INT_UTX_DONE); + } + } + } + } + } + } + } + } +} + +void DMA1_Channel4_IRQHandler(void) +{ + if (DMA_GetITStatus(DMA1_IT_TC4)) { + if (tx_dma.DMA_MemoryBaseAddr == (uint32_t)irda_tx_hdr) { + if (irda_tx_len) { + tx_dma.DMA_MemoryBaseAddr = (uint32_t)irda_tx_buf; + tx_dma.DMA_BufferSize = irda_tx_len; + + USART_DMACmd(USART1, USART_DMAReq_Tx, ENABLE); + } + } + } + + DMA_ClearITPendingBit(DMA1_IT_GL4 | DMA1_IT_TC4 | DMA1_IT_HT4 | DMA1_IT_TE4); +} diff --git a/nametag8_V003/user/device/irda.h b/nametag8_V003/user/device/irda.h new file mode 100644 index 0000000..f33d2ce --- /dev/null +++ b/nametag8_V003/user/device/irda.h @@ -0,0 +1,55 @@ +/* + * irda.h + * + * Created on: Oct 12, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_IRDA_H_ +#define USER_DEVICE_IRDA_H_ + + + +#include +#include + + +enum { + IRDA_STATE_IDLE, + IRDA_STATE_TX_HEADER, + IRDA_STATE_TX_BODY, + IRDA_STATE_TX_ACK, + IRDA_STATE_RX_DATA, + IRDA_STATE_RX_ACK +}; + + + +#define IRDA_HEADER_01 0x5a +#define IRDA_HEADER_02 0xa5 + + +#define IRDA_SD_PORT GPIOA +#define IRDA_SD_PIN GPIO_Pin_1 + +#define IrDA_Shutdown() IRDA_SD_PORT->BSHR = GPIO_Pin_1 +#define IrDA_Enable() IRDA_SD_PORT->BCR = GPIO_Pin_1 + +#define IrDA_USART_ENA_TX() (USART1->CTLR1 &= ~(USART_Mode_Rx); USART1->CTLR1 |= USART_Mode_Tx); +#define IrDA_USART_ENA_RX() (USART1->CTLR1 &= ~(USART_Mode_Tx); USART1->CTLR1 |= USART_Mode_Rx); + + + +extern uint16_t irda_tx_timer; +extern uint16_t irda_tx_timeout; + + + +void irda_init(); +void irda_process(); + +void irda_mode(uint8_t mode, uint16_t timeout); + + + +#endif /* USER_DEVICE_IRDA_H_ */ diff --git a/nametag8_V003/user/device/misc_gpo.h b/nametag8_V003/user/device/misc_gpo.h new file mode 100644 index 0000000..868e3c4 --- /dev/null +++ b/nametag8_V003/user/device/misc_gpo.h @@ -0,0 +1,22 @@ +/* + * misc_gpo.h + * + * Created on: Oct 12, 2024 + * Author: true + */ + +#ifndef USER_DEVICE_MISC_GPO_H_ +#define USER_DEVICE_MISC_GPO_H_ + + +#include +#include + + + +#define GPO_RGB_HWEN_PORT GPIOD +#define GPO_RGB_HWEN_PIN GPIO_Pin_0 + + + +#endif /* USER_DEVICE_MISC_GPO_H_ */ diff --git a/nametag8_V003/user/i2c_slave.c b/nametag8_V003/user/i2c_slave.c new file mode 100644 index 0000000..8e99ebe --- /dev/null +++ b/nametag8_V003/user/i2c_slave.c @@ -0,0 +1,281 @@ +/* + * i2c_device.c + * started Oct 12, 2024 + * + * ended up using some code from 003fun project, adapting it to my + * needs. it isn't quite what I want, but the emulated register file + * can be made to work in a time crunch. + * + * some notes: + * - writing does not loop; if writing to the end then new writes + * will cause an error. + * - added write protection for first 16 bytes. + * - many registers will only commit to action upon valid I2C stop received. + * + * + * register map: + * see i2c_slave.h + * + */ + +#include "i2c_slave.h" + +#include "device/btn.h" +#include "device/intr_out.h" +#include "device/irda.h" +#include "device/misc_gpo.h" + + + +volatile uint8_t i2cs_reg[256*3] = {0}; + +i2c_slave_state i2cs_state; + +static const uint8_t write_cb_trig[] = { + REG_INT_FLAGS_CLEAR, + REG_RGB_HWEN, + REG_IRDA_MODE, + REG_BTN1_HOLD_LO, + REG_BTN2_HOLD_LO, + REG_BTN3_HOLD_LO, + REG_BTN4_HOLD_LO, + REG_BTN5_HOLD_LO, + REG_BTN1_REPEAT_LO, + REG_BTN2_REPEAT_LO, + REG_BTN3_REPEAT_LO, + REG_BTN4_REPEAT_LO, + REG_BTN5_REPEAT_LO, +}; + +static void i2cs_int_check() +{ + if (i2cs_reg[REG_INT_FLAGS] & i2cs_reg[REG_INT_ENABLE]) { + INT_OUT_SET(); + } else { + INT_OUT_CLEAR(); + } +} + + +// called on a stop event. +// reg - first register sent by master +// last - last register written by master - if less than reg, nothing was written +void i2cs_write_cb(uint16_t initial_reg, uint16_t last_reg) +{ + uint8_t i; + uint8_t trig = 0; + uint16_t w; + + // nothing written? + if (initial_reg > last_reg) return; + + // button registers + if ((initial_reg <= REG_BTN1_MASK) && (last_reg >= REG_BTN5_MASK)) { + // if any button is read, clear the button interrupt automatically + i2cs_reg[REG_INT_FLAGS] &= ~INT_BTN; + i2cs_int_check(); + } + + // other single registers + for (i = 0; i < sizeof(write_cb_trig); i++) { + if ((initial_reg <= write_cb_trig[i]) && (last_reg >= write_cb_trig[i])) { + trig = write_cb_trig[i]; + } + + switch (trig) { + case REG_INT_FLAGS_CLEAR: { + i2cs_reg[REG_INT_FLAGS] &= ~i2cs_reg[REG_INT_FLAGS_CLEAR]; + i2cs_int_check(); + + break; + } + + case REG_RGB_HWEN: { + if (i2cs_reg[REG_RGB_HWEN]) GPO_RGB_HWEN_PORT->BSHR = GPO_RGB_HWEN_PIN; + else GPO_RGB_HWEN_PORT->BCR = GPO_RGB_HWEN_PIN; + break; + } + + case REG_IRDA_MODE: { + w = i2cs_reg[REG_IRDA_TIMER] * 20; + switch (i2cs_reg[trig]) { + case 0: irda_mode(IRDA_STATE_IDLE, 0); break; + case 1: irda_mode(IRDA_STATE_TX_HEADER, w); break; + case 2: irda_mode(IRDA_STATE_RX_DATA, w); break; + } + break; + } + + case REG_BTN1_HOLD_LO: + case REG_BTN2_HOLD_LO: + case REG_BTN3_HOLD_LO: + case REG_BTN4_HOLD_LO: + case REG_BTN5_HOLD_LO: { + w = (trig - REG_BTN1_HOLD_LO) >> 1; + btn[w].hold = (i2cs_reg[trig - 1] << 8) | i2cs_reg[trig]; + break; + } + + case REG_BTN1_REPEAT_LO: + case REG_BTN2_REPEAT_LO: + case REG_BTN3_REPEAT_LO: + case REG_BTN4_REPEAT_LO: + case REG_BTN5_REPEAT_LO: { + w = (trig - REG_BTN1_REPEAT_LO) >> 1; + btn[w].repeat = (i2cs_reg[trig - 1] << 8) | i2cs_reg[trig]; + break; + } + } + } +} + +// called when writing to a read-only register, +// writing past the end of the register file, +// or writing when read-only. +// reg - register written to +// data - data attempted to write to register +// error - see i2c_slave.h for error types +void i2cs_werr_cb(uint16_t reg, uint8_t data, uint8_t error) +{ + i2cs_reg[0x0d]++; + if (!i2cs_reg[0x0d]) i2cs_reg[0x0c]++; +} + +// called upon every register read +void i2cs_read_cb(uint16_t reg) +{ + +} + +void i2cs_init(uint8_t address, uint8_t read_only_mode) +{ + I2C_InitTypeDef i2c = {0}; + + i2cs_state.first_write = 1; + i2cs_state.offset = 0; + i2cs_state.position = 0; + i2cs_state.reg_file = i2cs_reg; + i2cs_state.reg_len = sizeof(i2cs_reg); + i2cs_state.write_callback = i2cs_write_cb; + i2cs_state.werr_callback = i2cs_werr_cb; + i2cs_state.read_callback = i2cs_read_cb; + i2cs_state.read_only = read_only_mode; + + i2c.I2C_ClockSpeed = 500000; + i2c.I2C_Mode = I2C_Mode_I2C; + i2c.I2C_DutyCycle = I2C_DutyCycle_2; + i2c.I2C_OwnAddress1 = address; + i2c.I2C_Ack = I2C_Ack_Enable; + i2c.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + + I2C_Init(I2C1, &i2c); + + // enable interrupts + I2C1->CTLR2 |= I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN | I2C_CTLR2_ITERREN; + + NVIC_SetPriority(I2C1_EV_IRQn, 1 << 6); + NVIC_EnableIRQ(I2C1_EV_IRQn); // Event interrupt + NVIC_SetPriority(I2C1_ER_IRQn, 3 << 6); + NVIC_EnableIRQ(I2C1_ER_IRQn); // Error interrupt + + // enable I2C + I2C_Cmd(I2C1, ENABLE); +} + +void i2cs_append_flag(uint8_t flag) +{ + if (flag) { + i2cs_reg[REG_INT_FLAGS] |= flag; + i2cs_int_check(); + } +} + +void i2cs_poll() +{ + +} + +__attribute__((interrupt("WCH-Interrupt-fast"))) +void I2C1_EV_IRQHandler(void) +{ + uint16_t STAR1; + uint16_t STAR2 __attribute__((unused)); + + STAR1 = I2C1->STAR1; + STAR2 = I2C1->STAR2; + + if (STAR1 & I2C_STAR1_ADDR) { // Start event + i2cs_state.first_write = 1; // Next write will be the offset + i2cs_state.position = i2cs_state.offset; // Reset position + } + + if (STAR1 & I2C_STAR1_RXNE) { // Write event + if (i2cs_state.first_write == 2) { // low address byte written; set the offset + i2cs_state.offset = i2cs_state.offset | I2C1->DATAR; + i2cs_state.position = i2cs_state.offset; + i2cs_state.first_write = 0; + i2cs_state.writing = 0; + } else if (i2cs_state.first_write == 1) { // high address byte written + i2cs_state.offset = I2C1->DATAR << 8; + i2cs_state.first_write++; + } else + { // Normal register write + i2cs_state.writing = 1; + + if (i2cs_state.position < i2cs_state.reg_len && !i2cs_state.read_only) { + // read only registers + if (i2cs_state.position < 16) { + if (i2cs_state.werr_callback != 0) { + i2cs_state.werr_callback(i2cs_state.position, I2C1->DATAR, I2CS_WRITE_READ_ONLY_REGISTER); + } + } else { + i2cs_state.reg_file[i2cs_state.position] = I2C1->DATAR; + } + i2cs_state.position++; + } else { + if (i2cs_state.werr_callback != 0) { + i2cs_state.werr_callback(i2cs_state.position, I2C1->DATAR, + i2cs_state.read_only ? I2CS_WRITE_WHEN_READ_ONLY : I2CS_WRITE_BEYOND_END); + } + } + } + } + + if (STAR1 & I2C_STAR1_TXE) { // Read event + i2cs_state.writing = 0; + if (i2cs_state.position < i2cs_state.reg_len) { + I2C1->DATAR = i2cs_state.reg_file[i2cs_state.position]; + if (i2cs_state.read_callback != 0) { + i2cs_state.read_callback(i2cs_state.position); + } + i2cs_state.position++; + } else { + I2C1->DATAR = 0x00; + } + } + + if (STAR1 & I2C_STAR1_STOPF) { // Stop event + I2C1->CTLR1 &= ~(I2C_CTLR1_STOP); // Clear stop + + if (i2cs_state.write_callback != 0 && i2cs_state.writing) { + i2cs_state.write_callback(i2cs_state.offset, i2cs_state.position - 1); + } + } +} + +void I2C1_ER_IRQHandler(void) +{ + uint16_t STAR1 = I2C1->STAR1; + + if (STAR1 & I2C_STAR1_BERR) { // Bus error + I2C1->STAR1 &= ~(I2C_STAR1_BERR); // Clear error + } + + if (STAR1 & I2C_STAR1_ARLO) { // Arbitration lost error + I2C1->STAR1 &= ~(I2C_STAR1_ARLO); // Clear error + } + + if (STAR1 & I2C_STAR1_AF) { // Acknowledge failure + I2C1->STAR1 &= ~(I2C_STAR1_AF); // Clear error + } +} diff --git a/nametag8_V003/user/i2c_slave.h b/nametag8_V003/user/i2c_slave.h new file mode 100644 index 0000000..8fdcfca --- /dev/null +++ b/nametag8_V003/user/i2c_slave.h @@ -0,0 +1,122 @@ +/* + * i2c_device.h + * + * Created on: Oct 12, 2024 + * Author: true + */ + +#ifndef USER_I2C_DEVICE_H_ +#define USER_I2C_DEVICE_H_ + +#include +#include + + + +enum i2cs_werr { + I2CS_WRITE_NO_ERROR, + I2CS_WRITE_WHEN_READ_ONLY, + I2CS_WRITE_READ_ONLY_REGISTER, + I2CS_WRITE_BEYOND_END +}; + +/* .... +* 0x20 btn1 +* .... +* 0x30..0x3f btn2 (see btn1 for register map) +* 0x40..0x4f btn3 (see btn1 for register map) +* 0x50..0x5f btn4 (see btn1 for register map) +* 0x60..0x6f btn5 (see btn1 for register map) +*/ + +enum i2cs_regmap { + // read-only + REG_INT_FLAGS = 0x00, + REG_RSVD_01, + REG_BTN_PUSHED_NEW, // unused + REG_BTN_PUSHED, // unused + REG_BTN_HELD, // unused + REG_BTN_RELEASED, // unused + REG_BTN1_MASK, // raw bitmask of button 1 state + REG_BTN2_MASK, // button interrupt is cleared on read of ANY button register + REG_BTN3_MASK, + REG_BTN4_MASK, + REG_BTN5_MASK, + + REG_WERR_HI = 0x0c, // write error count, high byte + REG_WERR_LO, // write error coutn, low byte + REG_IRDA_READ_HI, // IrDA read packet length, hi byte (currently always 0) + REG_IRDA_READ_LO, // IrDA read packet length, lo byte + + // read-write + REG_INT_FLAGS_CLEAR = 0x10, + REG_INT_ENABLE, // interrupt enable flags + REG_BTN_DEBOUNCE_TIME, + REG_BTN1_INT_ENABLE, // button 1 interrupt mask + REG_BTN2_INT_ENABLE, // button 2 interrupt mask + REG_BTN3_INT_ENABLE, // button 3 interrupt mask + REG_BTN4_INT_ENABLE, // button 4 interrupt mask + REG_BTN5_INT_ENABLE, // button 5 interrupt mask + + REG_RGB_HWEN, // high = RGB_HWEN hi, low = RGB_HWEN low + + REG_IRDA_TIMER = 0x1a, // IrDA read/write packet attempt time in 1/10 second increments (max ~25.5s sending time) + REG_IRDA_WRITE_RETRY, // IrDA write packet retry timeout in 1/100 second increments (max ~2.5s per retry) + REG_IRDA_MODE, // IrDA mode. 0 = idle, 1 = transmit, 2 = receive + REG_IRDA_WRITE_HI, // IrDA write packet length, hi byte (currently ignored) + REG_IRDA_WRITE_LO, // IrDA write packet length, lo byte + + REG_BTN1_HOLD_HI = 0x20, // btn initial hold time in 2ms increments, hi byte + REG_BTN1_HOLD_LO, // btn initial hold time in 2ms increments, lo byte + REG_BTN2_HOLD_HI, + REG_BTN2_HOLD_LO, + REG_BTN3_HOLD_HI, + REG_BTN3_HOLD_LO, + REG_BTN4_HOLD_HI, + REG_BTN4_HOLD_LO, + REG_BTN5_HOLD_HI, + REG_BTN5_HOLD_LO, + + REG_BTN1_REPEAT_HI = 0x30, // btn repeat time in 2ms increments, hi byte + REG_BTN1_REPEAT_LO, // btn repeat time in 2ms increments, lo byte + REG_BTN2_REPEAT_HI, + REG_BTN2_REPEAT_LO, + REG_BTN3_REPEAT_HI, + REG_BTN3_REPEAT_LO, + REG_BTN4_REPEAT_HI, + REG_BTN4_REPEAT_LO, + REG_BTN5_REPEAT_HI, + REG_BTN5_REPEAT_LO, +}; + + + +typedef void (*i2c_write_callback_t)(uint16_t reg, uint16_t length); +typedef void (*i2c_werr_callback_t)(uint16_t reg, uint8_t data, uint8_t error); +typedef void (*i2c_read_callback_t)(uint16_t reg); + +typedef struct i2c_slave_state { + uint8_t first_write; // first 2 bytes address the register file + uint16_t offset; // offset within the register file as sent by the master + uint16_t position; // current read/write position within the register file + volatile uint8_t* volatile reg_file; // register file pointer + uint16_t reg_len; // register file max length + i2c_write_callback_t write_callback; + i2c_werr_callback_t werr_callback; + i2c_read_callback_t read_callback; + uint8_t read_only; // flag to disallow writes + uint8_t writing; // flag to indicate currently writing +} i2c_slave_state; + + + +extern volatile uint8_t i2cs_reg[256*3]; + + + +void i2cs_init(uint8_t address, uint8_t read_only_mode); +void i2cs_append_flag(uint8_t flag); + + + +#endif /* USER_I2C_DEVICE_H_ */ diff --git a/nametag8_V003/user/main.c b/nametag8_V003/user/main.c new file mode 100644 index 0000000..84f62ef --- /dev/null +++ b/nametag8_V003/user/main.c @@ -0,0 +1,147 @@ +/* + * true's GAT Nametag + * Rushed SUPERCON 8 EDITION + * sub MCU firmware + * 2024 true + * + * the sub MCU is responsible for the following: + * - user buttons (complete handling / filtering) + * - rgb chip hw enable / disable + * - IrDA rx/tx and IrDA transceiver enable / disable + * - accelerometer hardware interrupt + * + * it does all this at a cost of a little less than 2mA. =( + * probably should've used PY32F which would've been 1mA, + * but oh well. wanted to stick with the same platform... + */ + + +#include + +#include "device/btn.h" +#include "device/intr_out.h" +#include "device/irda.h" + +#include "i2c_slave.h" + + + +static inline void gpio_init() +{ + GPIO_InitTypeDef gpio = {0}; + + gpio.GPIO_Speed = GPIO_Speed_2MHz; + + // unused pins; input pull high + gpio.GPIO_Mode = GPIO_Mode_IPU; + gpio.GPIO_Pin = GPIO_Pin_7; + GPIO_Init(GPIOD, &gpio); + + // BOOT button user buttons; input pull high + // note: default bootloader looks for BOOT to go HIGH to enter boot mode + // custom bootloader will instead look for BOOT to go LOW + gpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7; + GPIO_Init(GPIOC, &gpio); + + // unused pins; input pull low + gpio.GPIO_Mode = GPIO_Mode_IPD; + gpio.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4; + GPIO_Init(GPIOD, &gpio); + + // accelerometer PC3; input pull low, active high + gpio.GPIO_Pin = GPIO_Pin_3; + GPIO_Init(GPIOC, &gpio); + + // interrupt to main MCU PA1; output open drain + GPIOA->BSHR = GPIO_Pin_1 | GPIO_Pin_2; + gpio.GPIO_Mode = GPIO_Mode_Out_OD; + gpio.GPIO_Pin = GPIO_Pin_1; + GPIO_Init(GPIOA, &gpio); + + // IrDA shutdown PA2; output push/pull + gpio.GPIO_Mode = GPIO_Mode_Out_PP; + gpio.GPIO_Pin = GPIO_Pin_2; + GPIO_Init(GPIOA, &gpio); + + // AW200xx hardware enable pin PD0; output push/pull + gpio.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOD, &gpio); + + // I2C PC1, PC2; output AF open drain + gpio.GPIO_Mode = GPIO_Mode_AF_OD; + gpio.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2; + GPIO_Init(GPIOC, &gpio); + + // UART TX PD5; output AF push/pull + gpio.GPIO_Mode = GPIO_Mode_AF_PP; + gpio.GPIO_Pin = GPIO_Pin_5; + GPIO_Init(GPIOD, &gpio); + + // UART RX PD6; input pull low + gpio.GPIO_Mode = GPIO_Mode_IPD; + gpio.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOD, &gpio); +} + +static inline void exti_nvic_init() +{ + NVIC_InitTypeDef nvic = {0}; + + nvic.NVIC_IRQChannel = EXTI7_0_IRQn; + nvic.NVIC_IRQChannelPreemptionPriority = 0; + nvic.NVIC_IRQChannelSubPriority = 1; + nvic.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&nvic); +} + +void systick_init(void) +{ + SysTick->CMP = (SystemCoreClock / 200 / 8) - 1; // we want a 200Hz interrupt + SysTick->CNT = 0; // clear counter + SysTick->CTLR = 0xB; // start counter in /8 mode, enable interrupts, auto-reset counter + SysTick->SR = 0; // clear count comparison flag + + NVIC_EnableIRQ(SysTicK_IRQn); // enable interrupt +} + + + +/********************************************************************* + * @fn main + * + * @brief Main program. + * + * @return none + */ +//__attribute__((section(".data#"))) +int main(void) +{ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + SystemCoreClockUpdate(); + + // enable peripheral clocks used in this program + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); + RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR | RCC_APB1Periph_I2C1, ENABLE); + RCC_APB2PeriphClockCmd( RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA | + RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE); + + + // configure gpio + gpio_init(); + + // get i2c up and running + i2cs_init(INT_I2C_ADDR, 0); + + // configure various external peripherals + btn_init(); + irda_init(); + + // enable external interrupts + exti_nvic_init(); + + // configure systick + + while (1) { + __WFI(); + } +} diff --git a/nametag8_V003/user/system_ch32v00x.c b/nametag8_V003/user/system_ch32v00x.c new file mode 100644 index 0000000..dc01422 --- /dev/null +++ b/nametag8_V003/user/system_ch32v00x.c @@ -0,0 +1,448 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v00x.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/26 + * Description : CH32V00x Device Peripheral Access Layer System Source File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ + +#define SYSCLK_FREQ_8MHz_HSI 8000000 +//#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHZ_HSI 48000000 +//#define SYSCLK_FREQ_8MHz_HSE 8000000 +//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_8MHz_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHZ_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHZ_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHZ_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHZ_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_8MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#else + uint32_t SystemCoreClock = HSI_VALUE; +#endif + +__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_8MHz_HSI + static void SetSysClockTo_8MHz_HSI(void); +#elif defined SYSCLK_FREQ_24MHZ_HSI + static void SetSysClockTo_24MHZ_HSI(void); +#elif defined SYSCLK_FREQ_48MHZ_HSI + static void SetSysClockTo_48MHZ_HSI(void); +#elif defined SYSCLK_FREQ_8MHz_HSE + static void SetSysClockTo_8MHz_HSE(void); +#elif defined SYSCLK_FREQ_24MHz_HSE + static void SetSysClockTo_24MHz_HSE(void); +#elif defined SYSCLK_FREQ_48MHz_HSE + static void SetSysClockTo_48MHz_HSE(void); +#endif + + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; + RCC->INTR = 0x009F0000; + + RCC_AdjustHSICalibrationValue(0x10); + + SetSysClock(); +} + + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllsource = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllsource = RCC->CFGR0 & RCC_PLLSRC; + if (pllsource == 0x00) { + SystemCoreClock = HSI_VALUE * 2; + } else { + SystemCoreClock = HSE_VALUE * 2; + } + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + + if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) { + SystemCoreClock /= tmp; + } else { + SystemCoreClock >>= tmp; + } +} + + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + RCC->APB2PCENR |= RCC_APB2Periph_GPIOD; + GPIOD->CFGLR&=(~0xF0); + GPIOD->CFGLR|=0x80; + GPIOD->BSHR =0x2; + //GPIO_IPD_Unused(); + +#ifdef SYSCLK_FREQ_8MHz_HSI + SetSysClockTo_8MHz_HSI(); +#elif defined SYSCLK_FREQ_24MHZ_HSI + SetSysClockTo_24MHZ_HSI(); +#elif defined SYSCLK_FREQ_48MHZ_HSI + SetSysClockTo_48MHZ_HSI(); +#elif defined SYSCLK_FREQ_8MHz_HSE + SetSysClockTo_8MHz_HSE(); +#elif defined SYSCLK_FREQ_24MHz_HSE + SetSysClockTo_24MHz_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo_48MHz_HSE(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock. + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_8MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo_8MHz_HSI + * + * @brief Sets HSI as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_8MHz_HSI(void) +{ + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; +} + +#elif defined SYSCLK_FREQ_24MHZ_HSI + +/********************************************************************* + * @fn SetSysClockTo_24MHZ_HSI + * + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_24MHZ_HSI(void) +{ + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +} + + +#elif defined SYSCLK_FREQ_48MHZ_HSI + +/********************************************************************* + * @fn SetSysClockTo_48MHZ_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_48MHZ_HSI(void) +{ + uint8_t tmp = 0; + + tmp = *( uint8_t * )CFG0_PLL_TRIM; + + if(tmp != 0xFF) + { + RCC_AdjustHSICalibrationValue((tmp & 0x1F)); + } + + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* PLL configuration: PLLCLK = HSI * 2 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Mul2); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_8MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_8MHz_HSE + * + * @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_8MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA0-PA1 GPIO function */ + RCC->APB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<15); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_24MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_24MHz_HSE + * + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_24MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA0-PA1 GPIO function */ + RCC->APB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<15); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo_48MHz_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo_48MHz_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Close PA0-PA1 GPIO function */ + RCC->APB2PCENR |= RCC_AFIOEN; + AFIO->PCFR1 |= (1<<15); + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + + /* HCLK = SYSCLK = APB1 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* PLL configuration: PLLCLK = HSE * 2 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE_Mul2); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} +#endif + + + + diff --git a/nametag8_V003/user/system_ch32v00x.h b/nametag8_V003/user/system_ch32v00x.h new file mode 100644 index 0000000..5f681a9 --- /dev/null +++ b/nametag8_V003/user/system_ch32v00x.h @@ -0,0 +1,32 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v00x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2022/08/08 + * Description : CH32V00x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32V00x_H +#define __SYSTEM_CH32V00x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V00x_SYSTEM_H */ + + +