/*
 * ch32sub.h
 *
 *  Created on: Oct 11, 2024
 *      Author: true
 */

#ifndef USER_HW_CH32SUB_H_
#define USER_HW_CH32SUB_H_


#include "CH59x_common.h"
#include <stdint.h>

#include "../comm/i2c.h"



#define SUB_I2C_ADDR        0x5e

#define SUB_INTR_PORT       GPIOB
#define SUB_INTR_PIN        GPIO_Pin_13
#define SUB_INTR_PIN_NR     13

#define SUB_INT_BTN         (1 << 0)
#define SUB_INT_ACCEL       (1 << 1)
#define SUB_INT_UTX_DONE    (1 << 4)
#define SUB_INT_URX_RCVD    (1 << 5)

#define INT_BTN             (1 << 0)
#define INT_ACCEL           (1 << 1)
#define INT_UTX_DONE        (1 << 4)
#define INT_UTX_TIMEOUT     (1 << 5)
#define INT_UTX_ERROR       (1 << 6)
#define INT_URX_RCVD        (1 << 7)



enum ch32sub_regmap {
    // read-only
    REG_INTR_FLAGS = 0x00,
    REG_RSVD_01,
    REG_BTN_PUSHED_LATCHED,     // buttons currently pushed.
    REG_BTN_PUSHED,             // buttons pushed. reading will clear this value.
    REG_BTN_HELD,               // buttons currently being held. reading will clear this value.
    REG_BTN_RELEASED,           // buttons released. reading will clear this value.
    REG_BTN1_MASK,              // raw bitmask of button 1 state
    REG_BTN2_MASK,              // button interrupt is cleared on read of ANY REG_BTNx_MASK register
    REG_BTN3_MASK,
    REG_BTN4_MASK,
    REG_BTN5_MASK,

    REG_WERR_HI = 0x0c,         // write error count, high byte
    REG_WERR_LO,                // write error count, low byte
    REG_IRDA_READ_HI,           // IrDA read packet length, hi byte (currently always 0)
    REG_IRDA_READ_LO,           // IrDA read packet length, lo byte

    // read-write
    REG_INTR_FLAGS_CLEAR = 0x10,
    REG_INTR_ENABLE,            // interrupt enable flags
    REG_BTN_DEBOUNCE_TIME,
    REG_BTN1_INT_ENABLE,        // button 1 interrupt mask
    REG_BTN2_INT_ENABLE,        // button 2 interrupt mask
    REG_BTN3_INT_ENABLE,        // button 3 interrupt mask
    REG_BTN4_INT_ENABLE,        // button 4 interrupt mask
    REG_BTN5_INT_ENABLE,        // button 5 interrupt mask

    REG_RGB_HWEN,               // high = RGB_HWEN hi, low = RGB_HWEN low

    REG_IRDA_TIMER = 0x1a,      // IrDA read/write packet attempt time in 1/10 second increments (max ~25.5s sending time)
    REG_IRDA_WRITE_RETRY,       // IrDA write packet retry timeout in 1/100 second increments (max ~2.5s per retry)
    REG_IRDA_MODE,              // IrDA mode. 0 = idle, 1 = transmit, 2 = receive
    REG_IRDA_WRITE_HI,          // IrDA write packet length, hi byte (currently ignored)
    REG_IRDA_WRITE_LO,          // IrDA write packet length, lo byte

    REG_BTN1_HOLD_HI = 0x20,    // btn initial hold time in 2ms increments, hi byte
    REG_BTN1_HOLD_LO,           // btn initial hold time in 2ms increments, lo byte
    REG_BTN2_HOLD_HI,
    REG_BTN2_HOLD_LO,
    REG_BTN3_HOLD_HI,
    REG_BTN3_HOLD_LO,
    REG_BTN4_HOLD_HI,
    REG_BTN4_HOLD_LO,
    REG_BTN5_HOLD_HI,
    REG_BTN5_HOLD_LO,

    REG_BTN1_REPEAT_HI = 0x30,  // btn repeat time in 2ms increments, hi byte
    REG_BTN1_REPEAT_LO,         // btn repeat time in 2ms increments, lo byte
    REG_BTN2_REPEAT_HI,
    REG_BTN2_REPEAT_LO,
    REG_BTN3_REPEAT_HI,
    REG_BTN3_REPEAT_LO,
    REG_BTN4_REPEAT_HI,
    REG_BTN4_REPEAT_LO,
    REG_BTN5_REPEAT_HI,
    REG_BTN5_REPEAT_LO,
};


#define BTN_PUSH        (1 << 0)
#define BTN_HOLD        (1 << 1)
#define BTN_RELEASE     (1 << 2)
#define BTN_IGNORE      (1 << 3)



void ch32sub_init();
void ch32sub_isr();
void ch32sub_process();

void ch32sub_read(uint16_t reg, uint8_t *dat, uint8_t len);
void ch32sub_write(uint16_t reg, uint8_t *dat, uint8_t len);
void ch32sub_write_1b(uint16_t reg, uint8_t dat);

void ch32sub_intr_defaults();
void ch32sub_rgb_hwen(uint8_t en);



#endif /* USER_DEVICE_CH32SUB_H_ */
