1176 lines
39 KiB
C
1176 lines
39 KiB
C
/**
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******************************************************************************
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* @file py32f0xx_ll_spi.h
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* @author MCU Application Team
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* @brief Header file of SPI LL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef PY32F0xx_LL_SPI_H
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#define PY32F0xx_LL_SPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "py32f0xx.h"
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/** @addtogroup PY32F0xx_LL_Driver
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* @{
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*/
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#if defined (SPI1) || defined (SPI2)
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/** @defgroup SPI_LL SPI
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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#if defined(USE_FULL_LL_DRIVER)
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/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
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* @{
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*/
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/**
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* @brief SPI Init structures definition
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*/
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typedef struct
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{
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uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
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This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
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This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
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uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
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This parameter can be a value of @ref SPI_LL_EC_MODE.
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This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
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uint32_t DataWidth; /*!< Specifies the SPI data width.
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This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
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This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
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uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
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This parameter can be a value of @ref SPI_LL_EC_POLARITY.
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This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
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uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
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This parameter can be a value of @ref SPI_LL_EC_PHASE.
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This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
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uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
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This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
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This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
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uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
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This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
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@note The communication clock is derived from the master clock. The slave clock does not need to be set.
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This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
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uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
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This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
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This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
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uint32_t SlaveSpeedMode; /*!< Specifies the Slave speed mode.
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This parameter can be a value of @ref SPI_LL_EC_SLAVE_SPEED_MODE */
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} LL_SPI_InitTypeDef;
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
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* @{
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*/
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/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
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* @brief Flags defines which can be used with LL_SPI_ReadReg function
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* @{
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*/
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#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
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#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
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#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
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#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
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#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_IT IT Defines
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* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
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* @{
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*/
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#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
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#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
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#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_MODE Operation Mode
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* @{
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*/
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#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
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#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_PHASE Clock Phase
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* @{
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*/
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#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
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#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
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* @{
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*/
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#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
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#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
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* @{
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*/
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#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
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#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
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#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
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#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
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#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
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#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
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#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
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#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
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* @{
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*/
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#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
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#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
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* @{
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*/
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#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
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#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
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#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
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#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
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* @{
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*/
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#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
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#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
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#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
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* @{
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*/
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#define LL_SPI_DATAWIDTH_8BIT 0x0 /*!< Data length for SPI transfer: 8 bits */
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#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS) /*!< Data length for SPI transfer: 16 bits */
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/**
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* @}
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*/
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#if defined(USE_FULL_LL_DRIVER)
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#endif /* USE_FULL_LL_DRIVER */
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/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
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* @{
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*/
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#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
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#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
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* @{
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*/
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#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
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#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
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#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
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#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
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* @{
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*/
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#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
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#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
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#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
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#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
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#if (defined(DMA1) || defined(DMA))
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/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
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* @{
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*/
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#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
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#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
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#endif /* DMA1 or DMA */
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/**
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* @}
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*/
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/** @defgroup SPI_LL_EC_SLAVE_SPEED_MODE SLAVE SPEED MODE
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* @{
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*/
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#define LL_SPI_SLAVE_SPEED_NORMAL 0x00000000U /* Slave normal mode */
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#define LL_SPI_SLAVE_SPEED_FAST SPI_CR2_SLVFM /* Slave fast mode */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
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* @{
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*/
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/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
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* @{
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*/
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/**
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* @brief Write a value in SPI register
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* @param __INSTANCE__ SPI Instance
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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/**
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* @brief Read a value in SPI register
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* @param __INSTANCE__ SPI Instance
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
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* @{
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*/
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/** @defgroup SPI_LL_EF_Configuration Configuration
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* @{
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*/
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/**
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* @brief Enable SPI peripheral
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* @rmtoll CR1 SPE LL_SPI_Enable
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* @param SPIx SPI Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
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{
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SET_BIT(SPIx->CR1, SPI_CR1_SPE);
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}
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/**
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* @brief Disable SPI peripheral
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* @note When disabling the SPI, follow the procedure described in the Reference Manual.
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* @rmtoll CR1 SPE LL_SPI_Disable
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* @param SPIx SPI Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
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{
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CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
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}
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/**
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* @brief Check if SPI peripheral is enabled
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* @rmtoll CR1 SPE LL_SPI_IsEnabled
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* @param SPIx SPI Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
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{
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return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
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}
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/**
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* @brief Set SPI operation mode to Master or Slave
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* @note This bit should not be changed when communication is ongoing.
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* @rmtoll CR1 MSTR LL_SPI_SetMode\n
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* CR1 SSI LL_SPI_SetMode
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* @param SPIx SPI Instance
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* @param Mode This parameter can be one of the following values:
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* @arg @ref LL_SPI_MODE_MASTER
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* @arg @ref LL_SPI_MODE_SLAVE
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* @retval None
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*/
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__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
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{
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MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
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}
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/**
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* @brief Get SPI operation mode (Master or Slave)
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* @rmtoll CR1 MSTR LL_SPI_GetMode\n
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* CR1 SSI LL_SPI_GetMode
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* @param SPIx SPI Instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_SPI_MODE_MASTER
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* @arg @ref LL_SPI_MODE_SLAVE
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*/
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__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
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{
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return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
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}
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/**
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* @brief Set clock phase
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* @note This bit should not be changed when communication is ongoing.
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* This bit is not used in SPI TI mode.
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* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
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* @param SPIx SPI Instance
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* @param ClockPhase This parameter can be one of the following values:
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* @arg @ref LL_SPI_PHASE_1EDGE
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* @arg @ref LL_SPI_PHASE_2EDGE
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* @retval None
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*/
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__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
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{
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MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
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}
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/**
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* @brief Get clock phase
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* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
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* @param SPIx SPI Instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_SPI_PHASE_1EDGE
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* @arg @ref LL_SPI_PHASE_2EDGE
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*/
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__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
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{
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return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
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}
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/**
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* @brief Set clock polarity
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* @note This bit should not be changed when communication is ongoing.
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* This bit is not used in SPI TI mode.
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* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
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* @param SPIx SPI Instance
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* @param ClockPolarity This parameter can be one of the following values:
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* @arg @ref LL_SPI_POLARITY_LOW
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* @arg @ref LL_SPI_POLARITY_HIGH
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* @retval None
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*/
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__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
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{
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MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
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}
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/**
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* @brief Get clock polarity
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* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
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* @param SPIx SPI Instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_SPI_POLARITY_LOW
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* @arg @ref LL_SPI_POLARITY_HIGH
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*/
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__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
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{
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return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
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}
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/**
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* @brief Set baud rate prescaler
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* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
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* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
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* @param SPIx SPI Instance
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* @param BaudRate This parameter can be one of the following values:
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* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
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* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
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* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
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* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
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* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
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* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
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* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
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* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
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* @retval None
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*/
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__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
|
|
{
|
|
MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
|
|
}
|
|
|
|
/**
|
|
* @brief Get baud rate prescaler
|
|
* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
|
|
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
|
|
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
|
|
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
|
|
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
|
|
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
|
|
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
|
|
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
|
|
}
|
|
|
|
/**
|
|
* @brief Set transfer bit order
|
|
* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
|
|
* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
|
|
* @param SPIx SPI Instance
|
|
* @param BitOrder This parameter can be one of the following values:
|
|
* @arg @ref LL_SPI_LSB_FIRST
|
|
* @arg @ref LL_SPI_MSB_FIRST
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
|
|
{
|
|
MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
|
|
}
|
|
|
|
/**
|
|
* @brief Get transfer bit order
|
|
* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_LSB_FIRST
|
|
* @arg @ref LL_SPI_MSB_FIRST
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
|
|
}
|
|
|
|
/**
|
|
* @brief Set transfer direction mode
|
|
* @note For Half-Duplex mode, Rx Direction is set by default.
|
|
* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
|
|
* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
|
|
* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
|
|
* CR1 BIDIOE LL_SPI_SetTransferDirection
|
|
* @param SPIx SPI Instance
|
|
* @param TransferDirection This parameter can be one of the following values:
|
|
* @arg @ref LL_SPI_FULL_DUPLEX
|
|
* @arg @ref LL_SPI_SIMPLEX_RX
|
|
* @arg @ref LL_SPI_HALF_DUPLEX_RX
|
|
* @arg @ref LL_SPI_HALF_DUPLEX_TX
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
|
|
{
|
|
MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
|
|
}
|
|
|
|
/**
|
|
* @brief Get transfer direction mode
|
|
* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
|
|
* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
|
|
* CR1 BIDIOE LL_SPI_GetTransferDirection
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_FULL_DUPLEX
|
|
* @arg @ref LL_SPI_SIMPLEX_RX
|
|
* @arg @ref LL_SPI_HALF_DUPLEX_RX
|
|
* @arg @ref LL_SPI_HALF_DUPLEX_TX
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
|
|
}
|
|
|
|
/**
|
|
* @brief Set frame data width
|
|
* @rmtoll CR2 DS LL_SPI_SetDataWidth
|
|
* @param SPIx SPI Instance
|
|
* @param DataWidth This parameter can be one of the following values:
|
|
* @arg @ref LL_SPI_DATAWIDTH_8BIT
|
|
* @arg @ref LL_SPI_DATAWIDTH_16BIT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
|
|
{
|
|
MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
|
|
}
|
|
|
|
/**
|
|
* @brief Get frame data width
|
|
* @rmtoll CR2 DS LL_SPI_GetDataWidth
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_DATAWIDTH_8BIT
|
|
* @arg @ref LL_SPI_DATAWIDTH_16BIT
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
|
|
}
|
|
|
|
/**
|
|
* @brief Set threshold of RXFIFO that triggers an RXNE event
|
|
* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
|
|
* @param SPIx SPI Instance
|
|
* @param Threshold This parameter can be one of the following values:
|
|
* @arg @ref LL_SPI_RX_FIFO_TH_HALF
|
|
* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
|
|
{
|
|
MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
|
|
}
|
|
|
|
/**
|
|
* @brief Get threshold of RXFIFO that triggers an RXNE event
|
|
* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_RX_FIFO_TH_HALF
|
|
* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Set NSS mode
|
|
* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
|
|
* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
|
|
* @param SPIx SPI Instance
|
|
* @param NSS This parameter can be one of the following values:
|
|
* @arg @ref LL_SPI_NSS_SOFT
|
|
* @arg @ref LL_SPI_NSS_HARD_INPUT
|
|
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
|
|
{
|
|
MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
|
|
MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
|
|
}
|
|
|
|
/**
|
|
* @brief Get NSS mode
|
|
* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
|
|
* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_NSS_SOFT
|
|
* @arg @ref LL_SPI_NSS_HARD_INPUT
|
|
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
|
|
{
|
|
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
|
|
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
|
|
return (Ssm | Ssoe);
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Check if Rx buffer is not empty
|
|
* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Tx buffer is empty
|
|
* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Get mode fault error flag
|
|
* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get overrun error flag
|
|
* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get busy flag
|
|
* @note The BSY flag is cleared under any one of the following conditions:
|
|
* -When the SPI is correctly disabled
|
|
* -When a fault is detected in Master mode (MODF bit set to 1)
|
|
* -In Master mode, when it finishes a data transmission and no new data is ready to be
|
|
* sent
|
|
* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
|
|
* each data transfer.
|
|
* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get FIFO reception Level
|
|
* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_RX_FIFO_EMPTY
|
|
* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
|
|
* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
|
|
* @arg @ref LL_SPI_RX_FIFO_FULL
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
|
|
}
|
|
|
|
/**
|
|
* @brief Get FIFO Transmission Level
|
|
* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_TX_FIFO_EMPTY
|
|
* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
|
|
* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
|
|
* @arg @ref LL_SPI_TX_FIFO_FULL
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
|
|
}
|
|
|
|
/**
|
|
* @brief Clear mode fault error flag
|
|
* @note Clearing this flag is done by a read access to the SPIx_SR
|
|
* register followed by a write access to the SPIx_CR1 register
|
|
* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
|
|
{
|
|
__IO uint32_t tmpreg_sr;
|
|
tmpreg_sr = SPIx->SR;
|
|
(void) tmpreg_sr;
|
|
CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear overrun error flag
|
|
* @note Clearing this flag is done by a read access to the SPIx_DR
|
|
* register followed by a read access to the SPIx_SR register
|
|
* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
tmpreg = SPIx->DR;
|
|
(void) tmpreg;
|
|
tmpreg = SPIx->SR;
|
|
(void) tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable error interrupt
|
|
* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
|
|
* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
|
|
{
|
|
SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable Rx buffer not empty interrupt
|
|
* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
|
|
{
|
|
SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable Tx buffer empty interrupt
|
|
* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
|
|
{
|
|
SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable error interrupt
|
|
* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
|
|
* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
|
|
{
|
|
CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Rx buffer not empty interrupt
|
|
* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
|
|
{
|
|
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Tx buffer empty interrupt
|
|
* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
|
|
{
|
|
CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if error interrupt is enabled
|
|
* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Rx buffer not empty interrupt is enabled
|
|
* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Tx buffer empty interrupt
|
|
* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if (defined(DMA1) || defined(DMA))
|
|
/** @defgroup SPI_LL_EF_DMA_Management DMA Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable DMA Rx
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
|
|
{
|
|
SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable DMA Rx
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
|
|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
|
|
{
|
|
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if DMA Rx is enabled
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
|
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* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
|
|
}
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|
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|
/**
|
|
* @brief Enable DMA Tx
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
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* @param SPIx SPI Instance
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|
* @retval None
|
|
*/
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|
__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
|
|
{
|
|
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
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}
|
|
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|
/**
|
|
* @brief Disable DMA Tx
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|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
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|
* @param SPIx SPI Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
|
|
{
|
|
CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
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|
}
|
|
|
|
/**
|
|
* @brief Check if DMA Tx is enabled
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
|
|
* @param SPIx SPI Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
|
{
|
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Set parity of Last DMA reception
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
|
|
* @param SPIx SPI Instance
|
|
* @param Parity This parameter can be one of the following values:
|
|
* @arg @ref LL_SPI_DMA_PARITY_ODD
|
|
* @arg @ref LL_SPI_DMA_PARITY_EVEN
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
|
|
{
|
|
MODIFY_REG(SPIx->CR2, SPI_CR2_LDMA_RX, (Parity << SPI_CR2_LDMA_RX_Pos));
|
|
}
|
|
|
|
/**
|
|
* @brief Get parity configuration for Last DMA reception
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_DMA_PARITY_ODD
|
|
* @arg @ref LL_SPI_DMA_PARITY_EVEN
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMA_RX) >> SPI_CR2_LDMA_RX_Pos);
|
|
}
|
|
|
|
/**
|
|
* @brief Set parity of Last DMA transmission
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
|
|
* @param SPIx SPI Instance
|
|
* @param Parity This parameter can be one of the following values:
|
|
* @arg @ref LL_SPI_DMA_PARITY_ODD
|
|
* @arg @ref LL_SPI_DMA_PARITY_EVEN
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
|
|
{
|
|
MODIFY_REG(SPIx->CR2, SPI_CR2_LDMA_TX, (Parity << SPI_CR2_LDMA_TX_Pos));
|
|
}
|
|
|
|
/**
|
|
* @brief Get parity configuration for Last DMA transmission
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_DMA_PARITY_ODD
|
|
* @arg @ref LL_SPI_DMA_PARITY_EVEN
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMA_TX) >> SPI_CR2_LDMA_TX_Pos);
|
|
}
|
|
|
|
/**
|
|
* @brief Get the data register address used for DMA transfer
|
|
* @note Depending on devices and packages, DMA may not be available.
|
|
* Refer to device datasheet for DMA availability.
|
|
* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
|
|
* @param SPIx SPI Instance
|
|
* @retval Address of data register
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t) & (SPIx->DR);
|
|
}
|
|
#endif /* DMA1 or DMA */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SPI_LL_EF_DATA_Management DATA Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Read 8-Bits in the data register
|
|
* @rmtoll DR DR LL_SPI_ReceiveData8
|
|
* @param SPIx SPI Instance
|
|
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
|
|
*/
|
|
__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
|
|
{
|
|
return (*((__IO uint8_t *)&SPIx->DR));
|
|
}
|
|
|
|
/**
|
|
* @brief Read 16-Bits in the data register
|
|
* @rmtoll DR DR LL_SPI_ReceiveData16
|
|
* @param SPIx SPI Instance
|
|
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
|
|
*/
|
|
__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint16_t)(READ_REG(SPIx->DR));
|
|
}
|
|
|
|
/**
|
|
* @brief Write 8-Bits in the data register
|
|
* @rmtoll DR DR LL_SPI_TransmitData8
|
|
* @param SPIx SPI Instance
|
|
* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
|
|
{
|
|
#if defined (__GNUC__)
|
|
__IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
|
|
*spidr = TxData;
|
|
#else
|
|
*((__IO uint8_t *)&SPIx->DR) = TxData;
|
|
#endif /* __GNUC__ */
|
|
}
|
|
|
|
/**
|
|
* @brief Write 16-Bits in the data register
|
|
* @rmtoll DR DR LL_SPI_TransmitData16
|
|
* @param SPIx SPI Instance
|
|
* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
|
|
{
|
|
#if defined (__GNUC__)
|
|
__IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
|
|
*spidr = TxData;
|
|
#else
|
|
SPIx->DR = TxData;
|
|
#endif /* __GNUC__ */
|
|
}
|
|
|
|
/**
|
|
* @brief Set Slave Speed Mode
|
|
* @rmtoll CR2 SLVFM LL_SPI_SetSlaveSpeedMode
|
|
* @param SPIx SPI Instance
|
|
* @param SlaveSpeedMode This parameter can be one of the following values:
|
|
* @arg @ref LL_SPI_SLAVE_SPEED_NORMAL
|
|
* @arg @ref LL_SPI_SLAVE_SPEED_FAST
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_SPI_SetSlaveSpeedMode(SPI_TypeDef *SPIx, uint32_t SlaveSpeedMode)
|
|
{
|
|
MODIFY_REG(SPIx->CR2, SPI_CR2_SLVFM, SlaveSpeedMode);
|
|
}
|
|
|
|
/**
|
|
* @brief Get Slave Speed Mode
|
|
* @rmtoll CR2 SLVFM LL_SPI_GetSlaveSpeedMode
|
|
* @param SPIx SPI Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_SPI_SLAVE_SPEED_NORMAL
|
|
* @arg @ref LL_SPI_SLAVE_SPEED_FAST
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_SPI_GetSlaveSpeedMode(SPI_TypeDef *SPIx)
|
|
{
|
|
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_SLVFM));
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#if defined(USE_FULL_LL_DRIVER)
|
|
/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
|
|
* @{
|
|
*/
|
|
|
|
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
|
|
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
|
|
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* defined (SPI1) || defined (SPI2) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* PY32F0xx_LL_SPI_H */
|
|
|
|
/************************ (C) COPYRIGHT Puya *****END OF FILE****/
|