Puya Puya PY32F0xx_DFP PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x00000000 0xFFFFFFFF ADC Analog to Digital Converter ADC 0x40012400 0x0 0x400 registers ADC ADC Interrupt through EXTI Lines 17 and 18 12 ISR ISR ADC interrupt and status register 0x0 0x20 read-write 0x00000000 AWD ADC analog watchdog flag 7 1 OVR ADC group regular overrun flag 4 1 EOSEQ ADC group regular end of sequence conversions flag 3 1 EOC ADC group regular end of unitary conversion flag 2 1 EOSMP ADC group regular end of sampling flag 1 1 IER IER ADC interrupt enable register 0x4 0x20 read-write 0x00000000 AWDIE ADC analog watchdog interrupt 7 1 OVRIE ADC group regular overrun interrupt 4 1 EOSEQIE ADC group regular end of sequence conversions interrupt 3 1 EOCIE ADC group regular end of unitary conversion interrupt 2 1 EOSMPIE ADC group regular end of sampling interrupt 1 1 CR CR ADC control register 0x8 0x20 read-write 0x00000000 ADCAL ADC group regular conversion calibration 31 1 VERBUFF_SEL desc VERBUFF_SEL 6 2 VREF_BUFFERE desc VREF_BUFFERE 5 1 ADSTP ADC group regular conversion stop 4 1 ADSTART ADC group regular conversion start 2 1 ADEN ADC enable 0 1 CFGR1 CFGR1 ADC configuration register 1 0xC 0x20 read-write 0x00000000 AWDCH ADC analog watchdog monitored channel selection 26 4 AWDEN ADC analog watchdog enable on scope ADC group regular 23 1 AWDSGL ADC analog watchdog monitoring a single channel or all channels 22 1 DISCEN ADC group regular sequencer discontinuous mode 16 1 WAIT Wait conversion mode 14 1 CONT ADC group regular continuous conversion mode 13 1 OVRMOD ADC group regular overrun configuration 12 1 EXTEN ADC group regular external trigger polarity 10 2 EXTSEL ADC group regular external trigger source 6 3 ALIGN ADC data alignement 5 1 RESSEL ADC data resolution 3 2 SCANDIR Scan sequence direction 2 1 CFGR2 CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 CKMODE ADC clock mode 28 4 SMPR SMPR ADC sampling time register 0x14 0x20 read-write 0x00000000 SMP Sampling time selection 0 3 TR TR ADC analog watchdog 1 threshold register 0x20 0x20 read-write 0x0FFF0000 HT ADC analog watchdog threshold high 16 12 LT ADC analog watchdog threshold low 0 12 CHSELR CHSELR ADC group regular sequencer register 0x28 0x20 read-write 0x0FFF0000 CHSEL12 Channel-12 selection 12 1 CHSEL11 Channel-11 selection 11 1 CHSEL9 Channel-9 selection 9 1 CHSEL8 Channel-8 selection 8 1 CHSEL7 Channel-7 selection 7 1 CHSEL6 Channel-6 selection 6 1 CHSEL5 Channel-5 selection 5 1 CHSEL4 Channel-4 selection 4 1 CHSEL3 Channel-3 selection 3 1 CHSEL2 Channel-2 selection 2 1 CHSEL1 Channel-1 selection 1 1 CHSEL0 Channel-0 selection 0 1 DR DR ADC group regular data register 0x40 0x20 read-only 0x00000000 DATA ADC group regular conversion data 0 16 CCSR CCSR ADC calibration configuration and status register 0x44 0x20 read-write 0x00000000 CALON Calibration flag 31 1 read-only CALFAIL Calibration fail flag 30 1 OFFSUC desc OFFSUC 29 1 CALSET Calibration factor selection 15 1 CALBYP desc CALBYP 14 1 CALSMP Calibration sample time selection 12 2 CALSEL Calibration contents selection 11 1 CALRR1 CALRR1 ADC calibration result register 1 0x48 0x20 read-only 0x00000000 CALBOUT offset result 16 7 CALC5OUT C5 result 8 8 CALC4OUT C4 result 0 8 CALRR2 CALRR2 ADC calibration result register 2 0x4C 0x20 read-only 0x00000000 CALC3OUT C3 result 24 8 CALC2OUT C2 result 16 8 CALC1OUT C1 result 8 8 CALC0OUT C0 result 0 8 CALFIR1 CALFIR1 ADC calibration factor input register 1 0x50 0x20 read-write 0x00000000 CALBIO Calibration offset factor input 16 7 CALC5IO Calibration C5 factor input 8 8 CALC4IO Calibration C4 factor input 0 8 CALFIR2 CALFIR2 ADC calibration factor input register 2 0x54 0x20 read-write 0x00000000 CALC3IO Calibration C3 factor input 24 8 CALC2IO Calibration C2 factor input 16 8 CALC1IO Calibration C1 factor input 8 8 CALC0IO Calibration C0 factor input 0 8 CCR CCR ADC common configuration register 0x308 0x20 read-write 0x00000000 TSEN Temperature sensor enable 23 1 VREFEN VREFINT enable 22 1 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global Interrupt 4 CR CR Clock control register 0x0 0x20 read-write 0x00000100 HSIDIV HSI16 clock division factor 11 3 HSIRDY HSI16 clock ready flag 10 1 HSION HSI16 clock enable 8 1 ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x10000000 LSI_STARTUP LSI startup time 26 2 read-write LSI_TRIM LSI clock trimming 16 9 read-write HSI_FS HSI frequency selection 13 3 read-write HSI_TRIM HSI clock trimming 0 13 read-write CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-write MCOSEL Microcontroller clock output 24 3 read-write PPRE APB prescaler 12 3 read-write HPRE AHB prescaler 8 4 read-write SWS System clock switch status 3 3 read-only SW System clock switch 0 3 read-write ECSCR ECSCR External clock source control register 0x10 0x20 0x00000000 LSE_DRIVER desc LSE_DRIVER 16 2 read-write CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 HSIRDYIE HSI ready interrupt enable 3 1 LSERDYIE LSE ready interrupt enable 1 1 LSIRDYIE LSI ready interrupt enable 0 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSECSSF LSE clock secure system interrupt flag 9 1 HSIRDYF HSI ready interrupt flag 3 1 LSERDYF LSE ready interrupt flag 2 1 LSIRDYF LSI ready interrupt flag 0 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSECSSC LSE clock secure system interrupt flag clear 9 1 HSIRDYC HSI ready interrupt clear 3 1 LSERDYC LSE ready interrupt clear 1 1 LSIRDYC LSI ready interrupt clear 0 1 IOPRSTR IOPRSTR GPIO reset register 0x24 0x20 read-write 0x00000000 GPIOCRST I/O port C reset 2 1 GPIOBRST I/O port B reset 1 1 GPIOARST I/O port A reset 0 1 AHBRSTR AHBRSTR AHB peripheral reset register 0x28 0x20 read-write 0x00000000 CRCRST CRC reset 12 1 FLASHRST FLASH reset 8 1 DMARST DMA reset 0 1 APBRSTR1 APBRSTR1 APB peripheral reset register 1 0x2C 0x20 read-write 0x00000000 LPTIMRST Low Power Timer reset 31 1 PWRRST Power interface reset 28 1 DBGRST Debug support reset 27 1 I2CRST I2C reset 21 1 TIM6RST TIM6 reset 4 1 APBRSTR2 APBRSTR2 APB peripheral reset register 2 0x30 0x20 read-write 0x00000000 ADCRST ADC reset 20 1 USART1RST USART1 reset 14 1 SPI1RST SPI1 reset 12 1 TIM1RST TIM1 timer reset 11 1 SYSCFGRST SYSCFG and COMP reset 0 1 IOPENR IOPENR GPIO clock enable register 0x34 0x20 read-write 0x00000000 GPIOCEN I/O port C clock enable 2 1 GPIOBEN I/O port B clock enable 1 1 GPIOAEN I/O port A clock enable 0 1 AHBENR AHBENR AHB peripheral clock enable register 0x38 0x20 read-write 0x00000000 CRCEN CRC clock enable 12 1 SRAMEN SRAM memory interface clock enable 9 1 FLASHEN Flash memory interface clock enable 8 1 DMAEN DMA interface clock enable 0 1 APBENR1 APBENR1 APB peripheral clock enable register 1 0x3C 0x20 read-write 0x00000000 LPTIMEN LPTIM clock enable 31 1 PWREN Power interface clock enable 28 1 DBGEN Debug support clock enable 27 1 I2CEN I2C clock enable 21 1 TIM6EN TIM6 clock enable 4 1 APBENR2 APBENR2 APB peripheral clock enable register 2 0x40 0x20 read-write 0x00000000 ADCEN ADC clock enable 20 1 USART1EN USART1 clock enable 14 1 SPI1EN SPI1 clock enable 12 1 TIM1EN TIM1 timer clock enable 11 1 SYSCFGEN SYSCFG, COMP and VREFBUF clock enable 0 1 CCIPR CCIPR Peripherals independent clock configuration register 0x54 0x20 read-write 0x00000000 LPTIM1SEL LPTIM1 clock source selection 18 2 BDCR BDCR RTC domain control register 0x5C 0x20 read-write 0x00000000 LSCOSEL Low-speed clock output selection 25 1 LSCOEN Low-speed clock output (LSCO) enable 24 1 LSECSSD LSE CSS detect 6 1 LSECSSON LSE CSS enable 5 1 LSEBYP LSE oscillator bypass 2 1 LSERDY LSE oscillator ready 1 1 LSEON LSE oscillator enable 0 1 CSR CSR Control/status register 0x60 0x20 read-write 0x00000000 IWDGRSTF Independent window watchdog reset flag 29 1 SFTRSTF Software reset flag 28 1 PWRRSTF BOR or POR/PDR flag 27 1 PINRSTF Pin reset flag 26 1 OBLRSTF Option byte loader reset flag 25 1 RMVF Remove reset flags 23 1 PINRST_FLTDIS desc PINRST_FLTDIS 8 1 LSIRDY LSI oscillator ready 1 1 LSION LSI oscillator enable 0 1 PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00030000 HSION_CTRL HSI open time control 19 1 SRAM_RETV SRAM retention voltage control 16 3 LPR Low-power run 14 2 FLS_SLPTIME Flash wait time after wakeup from the stop mode 12 2 MRRDY_TIME Time selection wakeup from LP to VR 10 2 VOS Voltage scaling range selection 8 2 DBP Disable backup domain write protection 7 1 BIAS_CR_SEL MR Bias current selection 4 1 BIAS_CR MR Bias current 0 4 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000500 FLT_TIME Digital filter time configuration 9 3 FLTEN Digital filter enable 8 1 GPIOA General-purpose I/Os GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xEBFFFFFF MODE15 Port x configuration bits (y = 0..15) 30 2 MODE14 Port x configuration bits (y = 0..15) 28 2 MODE13 Port x configuration bits (y = 0..15) 26 2 MODE12 Port x configuration bits (y = 0..15) 24 2 MODE11 Port x configuration bits (y = 0..15) 22 2 MODE10 Port x configuration bits (y = 0..15) 20 2 MODE9 Port x configuration bits (y = 0..15) 18 2 MODE8 Port x configuration bits (y = 0..15) 16 2 MODE7 Port x configuration bits (y = 0..15) 14 2 MODE6 Port x configuration bits (y = 0..15) 12 2 MODE5 Port x configuration bits (y = 0..15) 10 2 MODE4 Port x configuration bits (y = 0..15) 8 2 MODE3 Port x configuration bits (y = 0..15) 6 2 MODE2 Port x configuration bits (y = 0..15) 4 2 MODE1 Port x configuration bits (y = 0..15) 2 2 MODE0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 OSPEED15 Port x configuration bits (y = 0..15) 30 2 OSPEED14 Port x configuration bits (y = 0..15) 28 2 OSPEED13 Port x configuration bits (y = 0..15) 26 2 OSPEED12 Port x configuration bits (y = 0..15) 24 2 OSPEED11 Port x configuration bits (y = 0..15) 22 2 OSPEED10 Port x configuration bits (y = 0..15) 20 2 OSPEED9 Port x configuration bits (y = 0..15) 18 2 OSPEED8 Port x configuration bits (y = 0..15) 16 2 OSPEED7 Port x configuration bits (y = 0..15) 14 2 OSPEED6 Port x configuration bits (y = 0..15) 12 2 OSPEED5 Port x configuration bits (y = 0..15) 10 2 OSPEED4 Port x configuration bits (y = 0..15) 8 2 OSPEED3 Port x configuration bits (y = 0..15) 6 2 OSPEED2 Port x configuration bits (y = 0..15) 4 2 OSPEED1 Port x configuration bits (y = 0..15) 2 2 OSPEED0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x24000000 PUPD15 Port x configuration bits (y = 0..15) 30 2 PUPD14 Port x configuration bits (y = 0..15) 28 2 PUPD13 Port x configuration bits (y = 0..15) 26 2 PUPD12 Port x configuration bits (y = 0..15) 24 2 PUPD11 Port x configuration bits (y = 0..15) 22 2 PUPD10 Port x configuration bits (y = 0..15) 20 2 PUPD9 Port x configuration bits (y = 0..15) 18 2 PUPD8 Port x configuration bits (y = 0..15) 16 2 PUPD7 Port x configuration bits (y = 0..15) 14 2 PUPD6 Port x configuration bits (y = 0..15) 12 2 PUPD5 Port x configuration bits (y = 0..15) 10 2 PUPD4 Port x configuration bits (y = 0..15) 8 2 PUPD3 Port x configuration bits (y = 0..15) 6 2 PUPD2 Port x configuration bits (y = 0..15) 4 2 PUPD1 Port x configuration bits (y = 0..15) 2 2 PUPD0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 ID15 Port input data (y = 0..15) 15 1 ID14 Port input data (y = 0..15) 14 1 ID13 Port input data (y = 0..15) 13 1 ID12 Port input data (y = 0..15) 12 1 ID11 Port input data (y = 0..15) 11 1 ID10 Port input data (y = 0..15) 10 1 ID9 Port input data (y = 0..15) 9 1 ID8 Port input data (y = 0..15) 8 1 ID7 Port input data (y = 0..15) 7 1 ID6 Port input data (y = 0..15) 6 1 ID5 Port input data (y = 0..15) 5 1 ID4 Port input data (y = 0..15) 4 1 ID3 Port input data (y = 0..15) 3 1 ID2 Port input data (y = 0..15) 2 1 ID1 Port input data (y = 0..15) 1 1 ID0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 OD15 Port output data (y = 0..15) 15 1 OD14 Port output data (y = 0..15) 14 1 OD13 Port output data (y = 0..15) 13 1 OD12 Port output data (y = 0..15) 12 1 OD11 Port output data (y = 0..15) 11 1 OD10 Port output data (y = 0..15) 10 1 OD9 Port output data (y = 0..15) 9 1 OD8 Port output data (y = 0..15) 8 1 OD7 Port output data (y = 0..15) 7 1 OD6 Port output data (y = 0..15) 6 1 OD5 Port output data (y = 0..15) 5 1 OD4 Port output data (y = 0..15) 4 1 OD3 Port output data (y = 0..15) 3 1 OD2 Port output data (y = 0..15) 2 1 OD1 Port output data (y = 0..15) 1 1 OD0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 BR15 Port Reset bit 15 1 BR14 Port Reset bit 14 1 BR13 Port Reset bit 13 1 BR12 Port Reset bit 12 1 BR11 Port Reset bit 11 1 BR10 Port Reset bit 10 1 BR9 Port Reset bit 9 1 BR8 Port Reset bit 8 1 BR7 Port Reset bit 7 1 BR6 Port Reset bit 6 1 BR5 Port Reset bit 5 1 BR4 Port Reset bit 4 1 BR3 Port Reset bit 3 1 BR2 Port Reset bit 2 1 BR1 Port Reset bit 1 1 BR0 Port Reset bit 0 1 GPIOB General-purpose I/Os GPIO 0x50000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xFFFFFFFF MODE8 Port x configuration bits (y = 0..15) 16 2 MODE7 Port x configuration bits (y = 0..15) 14 2 MODE6 Port x configuration bits (y = 0..15) 12 2 MODE5 Port x configuration bits (y = 0..15) 10 2 MODE4 Port x configuration bits (y = 0..15) 8 2 MODE3 Port x configuration bits (y = 0..15) 6 2 MODE2 Port x configuration bits (y = 0..15) 4 2 MODE1 Port x configuration bits (y = 0..15) 2 2 MODE0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEED8 Port x configuration bits (y = 0..15) 16 2 OSPEED7 Port x configuration bits (y = 0..15) 14 2 OSPEED6 Port x configuration bits (y = 0..15) 12 2 OSPEED5 Port x configuration bits (y = 0..15) 10 2 OSPEED4 Port x configuration bits (y = 0..15) 8 2 OSPEED3 Port x configuration bits (y = 0..15) 6 2 OSPEED2 Port x configuration bits (y = 0..15) 4 2 OSPEED1 Port x configuration bits (y = 0..15) 2 2 OSPEED0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPD8 Port x configuration bits (y = 0..15) 16 2 PUPD7 Port x configuration bits (y = 0..15) 14 2 PUPD6 Port x configuration bits (y = 0..15) 12 2 PUPD5 Port x configuration bits (y = 0..15) 10 2 PUPD4 Port x configuration bits (y = 0..15) 8 2 PUPD3 Port x configuration bits (y = 0..15) 6 2 PUPD2 Port x configuration bits (y = 0..15) 4 2 PUPD1 Port x configuration bits (y = 0..15) 2 2 PUPD0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 ID8 Port input data (y = 0..15) 8 1 ID7 Port input data (y = 0..15) 7 1 ID6 Port input data (y = 0..15) 6 1 ID5 Port input data (y = 0..15) 5 1 ID4 Port input data (y = 0..15) 4 1 ID3 Port input data (y = 0..15) 3 1 ID2 Port input data (y = 0..15) 2 1 ID1 Port input data (y = 0..15) 1 1 ID0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 OD8 Port output data (y = 0..15) 8 1 OD7 Port output data (y = 0..15) 7 1 OD6 Port output data (y = 0..15) 6 1 OD5 Port output data (y = 0..15) 5 1 OD4 Port output data (y = 0..15) 4 1 OD3 Port output data (y = 0..15) 3 1 OD2 Port output data (y = 0..15) 2 1 OD1 Port output data (y = 0..15) 1 1 OD0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFSEL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFSEL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFSEL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFSEL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFSEL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFSEL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFSEL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFSEL14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFSEL13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFSEL12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFSEL11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFSEL10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFSEL9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFSEL8 Alternate function selection for port x bit y (y = 8..15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 BR8 Port Reset bit 8 1 BR7 Port Reset bit 7 1 BR6 Port Reset bit 6 1 BR5 Port Reset bit 5 1 BR4 Port Reset bit 4 1 BR3 Port Reset bit 3 1 BR2 Port Reset bit 2 1 BR1 Port Reset bit 1 1 BR0 Port Reset bit 0 1 GPIOC 0x50000800 EXTI External interrupt/event controller EXTI 0x40021800 0x0 0x400 registers EXTI0_1 EXTI Line 0 and 1 Interrupt 5 EXTI2_3 EXTI Line 2 and 3 Interrupt 6 EXTI4_15 EXTI Line 4 to 15 Interrupt 7 RTSR RTSR EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 RT7 Rising trigger event configuration bit of Configurable Event input 7 1 RT6 Rising trigger event configuration bit of Configurable Event input 6 1 RT5 Rising trigger event configuration bit of Configurable Event input 5 1 RT4 Rising trigger event configuration bit of Configurable Event input 4 1 RT3 Rising trigger event configuration bit of Configurable Event input 3 1 RT2 Rising trigger event configuration bit of Configurable Event input 2 1 RT1 Rising trigger event configuration bit of Configurable Event input 1 1 RT0 Rising trigger event configuration bit of Configurable Event input 0 1 FTSR FTSR EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 FT7 Falling trigger event configuration bit of Configurable Event input 7 1 FT6 Falling trigger event configuration bit of Configurable Event input 6 1 FT5 Falling trigger event configuration bit of Configurable Event input 5 1 FT4 Falling trigger event configuration bit of Configurable Event input 4 1 FT3 Falling trigger event configuration bit of Configurable Event input 3 1 FT2 Falling trigger event configuration bit of Configurable Event input 2 1 FT1 Falling trigger event configuration bit of Configurable Event input 1 1 FT0 Falling trigger event configuration bit of Configurable Event input 0 1 SWIER SWIER EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 SWI7 Rising trigger event configuration bit of Configurable Event input 7 1 SWI6 Rising trigger event configuration bit of Configurable Event input 6 1 SWI5 Rising trigger event configuration bit of Configurable Event input 5 1 SWI4 Rising trigger event configuration bit of Configurable Event input 4 1 SWI3 Rising trigger event configuration bit of Configurable Event input 3 1 SWI2 Rising trigger event configuration bit of Configurable Event input 2 1 SWI1 Rising trigger event configuration bit of Configurable Event input 1 1 SWI0 Rising trigger event configuration bit of Configurable Event input 0 1 PR PR EXTI pending register 0xC 0x20 read-write 0x00000000 PR7 configurable event inputs x rising edge Pending bit. 7 1 PR6 configurable event inputs x rising edge Pending bit. 6 1 PR5 configurable event inputs x rising edge Pending bit. 5 1 PR4 configurable event inputs x rising edge Pending bit. 4 1 PR3 configurable event inputs x rising edge Pending bit. 3 1 PR2 configurable event inputs x rising edge Pending bit. 2 1 PR1 configurable event inputs x rising edge Pending bit. 1 1 PR0 configurable event inputs x rising edge Pending bit. 0 1 EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 read-write 0x00000000 EXTI3 GPIO port selection 24 2 EXTI2 GPIO port selection 16 2 EXTI1 GPIO port selection 8 2 EXTI0 GPIO port selection 0 2 EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 read-write 0x00000000 EXTI7 GPIO port selection 24 1 EXTI6 GPIO port selection 16 1 EXTI5 GPIO port selection 8 1 EXTI4 GPIO port selection 0 2 IMR IMR EXTI CPU wakeup with interrupt mask register 0x80 0x20 read-write 0xFFF80000 IM29 CPU wakeup with interrupt mask on event input 29 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM0 CPU wakeup with interrupt mask on event input 0 1 EMR EMR EXTI CPU wakeup with event mask register 0x84 0x20 read-write 0x00000000 EM29 CPU wakeup with event mask on event input 29 1 EM7 CPU wakeup with event mask on event input 7 1 EM6 CPU wakeup with event mask on event input 6 1 EM5 CPU wakeup with event mask on event input 5 1 EM4 CPU wakeup with event mask on event input 4 1 EM3 CPU wakeup with event mask on event input 3 1 EM2 CPU wakeup with event mask on event input 2 1 EM1 CPU wakeup with event mask on event input 1 1 EM0 CPU wakeup with event mask on event input 0 1 LPTIM1 Low power timer LPTIM1 0x40007C00 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 ARRM Autoreload match 1 1 ARROK Autoreload match update OK 4 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 ARRMCF Autoreload match Clear Flag 1 1 ARROKCF Autoreload match update OK Clear Flag 4 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 ARRMIE Autoreload matchInterrupt Enable 1 1 ARROKIE Autoreload match update OK Interrupt Enable 4 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 PRELOAD Registers update mode 22 1 PRESC Clock prescaler 9 3 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE Reset after read enable 4 1 CNTSTRT CNTSTRT 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global Interrupt 27 SR SR Status register 0x0 0x20 0x00C0 ABRRQ Automate baudrate detection requeset 12 1 write-only ABRE Automate baudrate detection error flag 11 1 read-only ABRF Automate baudrate detection flag 10 1 read-only CTS CTS flag 9 1 read-write TXE Transmit data register empty 7 1 read-only TC Transmission complete 6 1 read-write RXNE Read data register not empty 5 1 read-write IDLE IDLE line detected 4 1 read-only ORE Overrun error 3 1 read-only NE Noise error flag 2 1 read-only FE Framing error 1 1 read-only PE Parity error 0 1 read-only DR DR Data register 0x4 0x20 read-write 0x00000000 DR Data value 0 9 BRR BRR Baud rate register 0x8 0x20 read-write 0x0000 DIV_Mantissa mantissa of USARTDIV 4 12 DIV_Fraction fraction of USARTDIV 0 4 CR1 CR1 Control register 1 0xC 0x20 read-write 0x0000 UE USART enable 13 1 M Word length 12 1 WAKE Wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE TXE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 CR2 CR2 Control register 2 0x10 0x20 read-write 0x0000 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 ADD Address of the USART node 0 4 CR3 CR3 Control register 3 0x14 0x20 read-write 0x0000 ABRMOD Auto baudrate mode 13 2 ABREN Auto baudrate enable 12 1 OVER8 Oversampling mode 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 HDSEL Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 EIE Error interrupt enable 0 1 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register (IWDG_KR) 0x0 0x20 write-only 0x00000000 KEY Key value 0 16 PR PR Prescaler register (IWDG_PR) 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register (IWDG_RLR) 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register (IWDG_SR) 0xC 0x20 read-only 0x00000000 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 13 TIM1_CC TIM1 Capture Compare Interrupt 14 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write CR2 desc CR2 0x4 32 read-write 0x0 0xF8 CCDS desc CCDS 3 3 read-write MMS desc MMS 6 4 read-write TI1S desc TI1S 7 7 read-write SMCR desc SMCR 0x8 32 read-write 0x0 0xFFF7 SMS desc SMS 2 0 read-write OCCS desc OCCS 3 3 read-write TS desc TS 6 4 read-write MSM desc MSM 7 7 read-write ETF desc ETF 11 8 read-write ETPS desc ETPS 13 12 read-write ECE desc ECE 14 14 read-write ETP desc ETP 15 15 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write BIE desc BIE 7 7 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write COMIF desc COMIF 5 5 read-write TIF desc TIF 6 6 read-write BIF desc BIF 7 7 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write IC1IR desc IC1IR 16 16 read-write IC2IR desc IC2IR 17 17 read-write IC3IR desc IC3IR 18 18 read-write IC4IR desc IC3IR 19 19 read-write IC1IF desc IC1IF 20 20 read-write IC2IF desc IC2IF 21 21 read-write IC3IF desc IC3IF 22 22 read-write IC4IF desc IC3IF 23 23 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only COMG desc COMG 5 5 write-only TG desc TG 6 6 write-only BG desc BG 7 7 write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write OC1FE desc OC1FE 2 2 read-write OC1PE desc OC1PE 3 3 read-write OC1M desc OC1M 6 4 read-write OC1CE desc OC1CE 7 7 read-write CC2S desc CC2S 9 8 read-write OC2FE desc OC2FE 10 10 read-write OC2PE desc OC2PE 11 11 read-write OC2M desc OC2M 14 12 read-write OC2CE desc OC2CE 15 15 read-write CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write IC1PSC desc IC1PSC 3 2 read-write IC1F desc IC1F 7 4 read-write CC2S desc CC2S 9 8 read-write IC2PSC desc IC2PSC 11 10 read-write IC2F desc IC2F 15 12 read-write CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C 32 read-write 0x0 0xFFFF CC3S desc CC3S 1 0 read-write OC3FE desc OC3FE 2 2 read-write OC3PE desc OC3PE 3 3 read-write OC3M desc OC3M 6 4 read-write OC3CE desc OC3CE 7 7 read-write CC4S desc CC4S 9 8 read-write OC4FE desc OC4FE 10 10 read-write OC4PE desc OC4PE 11 11 read-write OC4M desc OC4M 14 12 read-write OC4CE desc OC4CE 15 15 read-write CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C 32 read-write 0x0 0xFFFF CC3S desc CC3S 1 0 read-write IC3PSC desc IC3PSC 3 2 read-write IC3F desc IC3F 7 4 read-write CC4S desc CC4S 9 8 read-write IC4PSC desc IC4PSC 11 10 read-write IC4F desc IC4F 15 12 read-write CCER desc CCER 0x20 32 read-write 0x0 0x3333 CC1E desc CC1E 0 0 read-write CC1P desc CC1P 1 1 read-write CC2E desc CC2E 4 4 read-write CC2P desc CC2P 5 5 read-write CC3E desc CC3E 8 8 read-write CC3P desc CC3P 9 9 read-write CC4E desc CC4E 12 12 read-write CC4P desc CC4P 13 13 read-write CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write RCR desc RCR 0x30 32 read-write 0xFFFF 0xFFFF REP desc REP 7 0 read-write CCR1 desc CCR1 0x34 32 read-write 0x0 0xFFFF CCR1 desc CCR1 15 0 read-write CCR2 desc CCR2 0x38 32 read-write 0x0 0xFFFF CCR2 desc CCR2 15 0 read-write CCR3 desc CCR3 0x3C 32 read-write 0x0 0xFFFF CCR3 desc CCR3 15 0 read-write CCR4 desc CCR4 0x40 32 read-write 0x0 0xFFFF CCR4 desc CCR4 15 0 read-write BDTR desc BDTR 0x44 32 read-write 0x0 0xFFFF DTG desc DTG 7 0 read-write LOCK desc LOCK 9 8 read-write OSSI desc OSSI 10 10 read-write OSSR desc OSSR 11 11 read-write BKE desc BKE 12 12 read-write BKP desc BKP 13 13 read-write AOE desc AOE 14 14 read-write MOE desc MOE 15 15 read-write DCR desc DCR 0x48 32 read-write 0x0 0x1F1F DBA desc DBA 4 0 read-write DBL desc DBL 12 8 read-write DMAR desc DMAR 0x4C 32 read-write 0x0 0xFFFF DMAB desc DMAB 15 0 read-write TIM6 desc TIM TIM 0x40001000 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write CR2 desc CR2 0x4 32 read-write 0x0 0xF8 CCDS desc CCDS 3 3 read-write MMS desc MMS 6 4 read-write TI1S desc TI1S 7 7 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write UDE desc UDE 8 8 read-write CC1DE desc CC1DE 9 9 read-write CC2DE desc CC2DE 10 10 read-write CC3DE desc CC3DE 11 11 read-write CC4DE desc CC4DE 12 12 read-write TDE desc TDE 14 14 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write COMIF desc COMIF 5 5 read-write TIF desc TIF 6 6 read-write BIF desc BIF 7 7 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write IC1IR desc IC1IR 16 16 read-write IC2IR desc IC2IR 17 17 read-write IC3IR desc IC3IR 18 18 read-write IC4IR desc IC3IR 19 19 read-write IC1IF desc IC1IF 20 20 read-write IC2IF desc IC2IF 21 21 read-write IC3IF desc IC3IF 22 22 read-write IC4IF desc IC3IF 23 23 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only TG desc TG 6 6 write-only CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x30 registers CFGR1 CFGR1 SYSCFG configuration register 1 0x0 0x20 read-write 0x00000000 I2C_PB6_FMP desc I2C_PB6_FMP 19 1 I2C_PB4_FMP desc I2C_PB4_FMP 18 1 I2C_PB3_FMP desc I2C_PB3_FMP 17 1 I2C_PA2_FMP desc I2C_PA2_FMP 16 1 MEM_MODE Memory mapping selection bits 0 2 CFGR2 CFGR2 SYSCFG configuration register 2 0x18 0x20 read-write 0x00000000 ETR_SRC_TIM1 TIM1 ETR source selection 9 2 LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit 0 1 GPIO_ENS desc GPIO_ENS 0x1C 32 read-write 0x0 PC_ENS desc PC_ENS 17 16 read-write PB_ENS desc PB_ENS 15 8 read-write PA_ENS desc PA_ENS 7 0 read-write FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 3 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 1 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEY Flash key 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEY Option byte key 0 32 SR SR Status register 0x10 0x20 read-write 0x00000000 BSY Busy 16 1 OPTVERR Option and Engineering bits loading validity error 15 1 WRPERR Write protected error 4 1 EOP End of operation 0 1 CR CR Flash control register 0x14 0x20 read-write 0xC0000000 LOCK FLASH_CR Lock 31 1 OPTLOCK Options Lock 30 1 OBL_LAUNCH Force the option byte loading 27 1 ERRIE Error interrupt enable 25 1 EOPIE End of operation interrupt enable 24 1 PGTSTRT Flash main memory program start 19 1 OPTSTRT Option byte program start 17 1 SER Sector erase 11 1 MER Mass erase 2 1 PER Page erase 1 1 PG Programming 0 1 OPTR OPTR Flash option register 0x20 0x20 read-write 0x4F55B0AA nBOOT1 Boot configuration 15 1 NRST_MODE NRST_MODE 14 1 WWDG_SW Window watchdog selection 13 1 IWDG_SW Independent watchdog selection 12 1 BORF_LEV These bits contain the VDD supply level threshold that activates the reset 9 3 BOREN BOR reset Level 8 1 RDP Read Protection 0 8 SDKR SDKR Flash SDK address register 0x24 0x20 read-write 0xFFE0001F SDK_END SDK area end address 8 4 SDK_STRT SDK area start address 0 4 BTCR SDKR FLASH boot control register 0x28 0x20 read-write 0x0 BOOT0 desc BOOT0 15 1 BOOT_SIZE desc BOOT_SIZE 0 3 WRPR WRPR Flash WRP address register 0x2C 0x20 read-write 0x0000FFFF WRP WRP address 0 6 STCR STCR Flash sleep time config register 0x90 0x20 read-write 0x00006400 SLEEP_TIME FLash sleep time configuration(counter based on HSI_10M) 8 8 SLEEP_EN FLash sleep enable 0 1 TS0 TS0 Flash TS0 register 0x100 0x20 read-write 0x000000B4 TS0 FLash TS0 register 0 8 TS1 TS1 Flash TS1 register 0x104 0x20 read-write 0x000001B0 TS1 FLash TS1 register 0 9 TS2P TS2P Flash TS2P register 0x108 0x20 read-write 0x000000B4 TS2P FLash TS2P register 0 8 TPS3 TPS3 Flash TPS3 register 0x10C 0x20 read-write 0x000006C0 TPS3 FLash TPS3 register 0 11 TS3 TS3 Flash TS3 register 0x110 0x20 read-write 0x000000B4 TS3 FLash TS3 register 0 8 PERTPE PERTPE Flash PERTPE register 0x114 0x20 read-write 0x0000EA60 PERTPE FLash PERTPE register 0 17 SMERTPE SMERTPE Flash SMERTPE register 0x118 0x20 read-write 0x0000FD20 SMERTPE FLash SMERTPE register 0 17 PRGTPE PRGTPE Flash PRGTPE register 0x11C 0x20 read-write 0x00008CA0 PRGTPE FLash PRGTPE register 0 16 PRETPE PRETPE Flash PRETPE register 0x120 0x20 read-write 0x000012C0 PRETPE FLash PRETPE register 0 13 CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data Register 0 32 IDR IDR Independent Data register 0x4 0x20 read-write 0x00000000 IDR Independent Data register 0 8 CR CR Control register 0x8 0x20 write-only 0x00000000 RESET Reset bit 0 1 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global Interrupt 25 CR1 desc CR1 0x0 32 read-write 0x0 CPHA desc CPHA 0 0 read-write CPOL desc CPOL 1 1 read-write MSTR desc MSTR 2 2 read-write BR desc BR 5 3 read-write SPE desc SPE 6 6 read-write LSBFIRST desc LSBFIRST 7 7 read-write SSI desc SSI 8 8 read-write SSM desc SSM 9 9 read-write RXONLY desc RXONLY 10 10 read-write DDF desc DDF 11 11 read-write CRCNEXT desc CRCNEXT 12 12 read-write CRCEN desc CRCEN 13 13 read-write BIDIOE desc BIDIOE 14 14 read-write BIDIMODE desc BIDIMODE 15 15 read-write CR2 desc CR2 0x4 32 read-write 0x0 RXDMAEN desc RXDMAEN 0 0 read-write TXDMAEN desc TXDMAEN 1 1 read-write SSOE desc SSOE 2 2 read-write CLRTXFIFO desc CLRTXFIFO 4 4 read-write ERRIE desc ERRIE 5 5 read-write RXNEIE desc RXNEIE 6 6 read-write TXEIE desc TXEIE 7 7 read-write FRXTH desc FRXTH 12 12 read-write LDMA_RX desc LDMA_RX 13 13 read-write LDMA_TX desc LDMA_TX 14 14 read-write SR desc SR 0x8 32 read-write 0x2 RXNE desc RXNE 0 0 read-only TXE desc TXE 1 1 read-only CHSIDE desc CHSIDE 2 2 read-only UDR desc UDR 3 3 read-only CRCERR desc CRCERR 4 4 read-write MODF desc MODF 5 5 read-only OVR desc OVR 6 6 read-only BSY desc BSY 7 7 read-only FRLVL desc FRLVL 10 9 read-only FTLVL desc FTLVL 12 11 read-only DR desc DR 0xC 32 read-write 0x0 DR desc DR 15 0 read-write CRCPR desc CRCPR 0x10 32 read-write 0x7 CRCPOLY desc CRCPOLY 15 0 read-write RXCRCR desc RXCRCR 0x14 32 read-only 0x0 RXCRC desc RXCRC 15 0 read-only TXCRCR desc TXCRCR 0x18 32 read-only 0x0 TXCRC desc TXCRC 15 0 read-only I2SCFGR desc I2SCFGR 0x1C 32 read-write 0x0 CHLEN desc CHLEN 0 0 read-write DATLEN desc DATLEN 2 1 read-write CKPOL desc CKPOL 3 3 read-write I2SSTD desc I2SSTD 5 4 read-write PCMSYNC desc PCMSYNC 7 7 read-write I2SCFG desc I2SCFG 9 8 read-write I2SE desc I2SE 10 10 read-write I2SMOD desc I2SMOD 11 11 read-write I2SPR desc I2SPR 0x20 32 read-write 0x2 I2SDIV desc I2SDIV 7 0 read-write ODD desc ODD 8 8 read-write MCKOE desc MCKOE 9 9 read-write I2C Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global Interrupt 23 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 SWRST Software reset 15 1 PEC Packet error checking 12 1 POS Acknowledge/PEC Position (for datareception) 11 1 ACK Acknowledge enable 10 1 STOP Stop generation 9 1 START Start generation 8 1 NOSTRETCH Clock stretching disable (Slavemode) 7 1 ENGC General call enable 6 1 ENPEC PEC enable 5 1 PE Peripheral enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ITBUFEN Buffer interrupt enable 10 1 ITEVTEN Event interrupt enable 9 1 ITERREN Error interrupt enable 8 1 FREQ Peripheral clock frequency 0 6 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x0000 ADD Interface address 1 7 DR DR Data register 0x10 0x20 read-write 0x0000 DR 8-bit data register 0 8 SR1 SR1 Status register 1 0x14 0x20 0x0000 PECERR PEC Error in reception 12 1 read-write OVR Overrun/Underrun 11 1 read-write AF Acknowledge failure 10 1 read-write ARLO Arbitration lost (mastermode) 9 1 read-write BERR Bus error 8 1 read-write TxE Data register empty(transmitters) 7 1 read-only RxNE Data register not empty(receivers) 6 1 read-only STOPF Stop detection (slavemode) 4 1 read-only BTF Byte transfer finished 2 1 read-only ADDR Address sent (master mode)/matched(slave mode) 1 1 read-only SB Start bit (Master mode) 0 1 read-only SR2 SR2 Status register 2 0x18 0x20 read-only 0x0000 PEC acket error checkingregister 8 8 DUALF Dual flag (Slave mode) 7 1 GENCALL General call address (Slavemode) 4 1 TRA Transmitter/receiver 2 1 BUSY Bus busy 1 1 MSL Master/slave 0 1 CCR CCR Clock control register 0x1C 0x20 read-write 0x0000 F_S I2C master mode selection 15 1 DUTY Fast mode duty cycle 14 1 CCR Clock control register in Fast/Standardmode (Master mode) 0 12 TRISE TRISE TRISE register 0x20 0x20 read-write 0x0002 TRISE Maximum rise time in Fast/Standard mode(Master mode) 0 6 DBGMCU Debug support DBGMCU 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x0 REV_ID REV_ID 0 32 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x0 DBG_SLEEP Debug Sleep Mode 0 1 DBG_STOP Debug Stop Mode 1 1 APB_FZ1 APB_FZ1 APB Freeze Register1 0x8 0x20 read-write 0x0 DBG_TIM6_STOP Debug TIM 6 stopped whenCore is halted 4 1 DBG_IWDG_STOP Debug Independent Wachdog stopped whenCore is halted 12 1 DBG_I2C1_TIMEOUT Debug I2C1 TIMEOUT stopped when Core ishalted 21 1 DBG_LPTIM_STOP Debug LPTIM stopped when Core ishalted 31 1 APB_FZ2 APB_FZ2 APB Freeze Register2 0xC 0x20 read-write 0x0 DBG_TIMER1_STOP Debug Timer 1 stopped when Core ishalted 11 1