From f110ffe1a741646f547e9d248d3133a63fc1c03f Mon Sep 17 00:00:00 2001 From: true Date: Sat, 21 Oct 2023 07:31:36 -0700 Subject: [PATCH] Add fixed SVD file for PY32F0xx series DBGMCU->IDCODE had empty tags, and file had other visual formatting errors --- misc/svd/py32f030xx.svd | 11132 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 11132 insertions(+) create mode 100644 misc/svd/py32f030xx.svd diff --git a/misc/svd/py32f030xx.svd b/misc/svd/py32f030xx.svd new file mode 100644 index 0000000..7a72303 --- /dev/null +++ b/misc/svd/py32f030xx.svd @@ -0,0 +1,11132 @@ + + + Puya + Puya + PY32F0xx_DFP + + PY32F0 + 1.0.0 + Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. + + + CM0+ + r0p1 + little + false + false + 4 + false + + 8 + + 32 + + + 32 + + read-write + + 0x00000000 + + 0xFFFFFFFF + + + + ADC + Analog to Digital Converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + ISR + ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + AWD + ADC analog watchdog flag + 7 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOSEQ + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDIE + ADC analog watchdog + interrupt + 7 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSEQIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling + interrupt + 1 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC group regular conversion + calibration + 31 + 1 + + + ADSTP + ADC group regular conversion + stop + 4 + 1 + + + ADSTART + ADC group regular conversion + start + 2 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR1 + CFGR1 + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + AWDCH + ADC analog watchdog monitored channel + selection + 26 + 4 + + + AWDEN + ADC analog watchdog enable on scope + ADC group regular + 23 + 1 + + + AWDSGL + ADC analog watchdog monitoring a + single channel or all channels + 22 + 1 + + + DISCEN + ADC group regular sequencer + discontinuous mode + 16 + 1 + + + WAIT + Wait conversion mode + 14 + 1 + + + CONT + ADC group regular continuous conversion + mode + 13 + 1 + + + OVRMOD + ADC group regular overrun + configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger + polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger + source + 6 + 3 + + + ALIGN + ADC data alignement + 5 + 1 + + + RESSEL + ADC data resolution + 3 + 2 + + + SCANDIR + Scan sequence direction + 2 + 1 + + + DMACFG + ADC DMA transfer + configuration + 1 + 1 + + + DMAEN + ADC DMA transfer enable + 0 + 1 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CKMODE + ADC clock mode + 28 + 4 + + + + + SMPR + SMPR + ADC sampling time register + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP + Sampling time selection + 0 + 3 + + + + + TR + TR + ADC analog watchdog 1 threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT + ADC analog watchdog threshold + high + 16 + 12 + + + LT + ADC analog watchdog threshold + low + 0 + 12 + + + + + CHSELR + CHSELR + ADC group regular sequencer register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + CHSEL12 + Channel-12 selection + 12 + 1 + + + CHSEL11 + Channel-11 selection + 11 + 1 + + + CHSEL9 + Channel-9 selection + 9 + 1 + + + CHSEL8 + Channel-8 selection + 8 + 1 + + + CHSEL7 + Channel-7 selection + 7 + 1 + + + CHSEL6 + Channel-6 selection + 6 + 1 + + + CHSEL5 + Channel-5 selection + 5 + 1 + + + CHSEL4 + Channel-4 selection + 4 + 1 + + + CHSEL3 + Channel-3 selection + 3 + 1 + + + CHSEL2 + Channel-2 selection + 2 + 1 + + + CHSEL1 + Channel-1 selection + 1 + 1 + + + CHSEL0 + Channel-0 selection + 0 + 1 + + + + + DR + DR + ADC group regular data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + ADC group regular conversion + data + 0 + 16 + + + + + CCSR + CCSR + ADC calibration configuration and status register + 0x44 + 0x20 + read-write + 0x00000000 + + + CALON + Calibration flag + 31 + 1 + read-only + + + CALFAIL + Calibration fail flag + 30 + 1 + + + CALSET + Calibration factor selection + 15 + 1 + + + CALSMP + Calibration sample time selection + 12 + 2 + + + CALSEL + Calibration contents selection + 11 + 1 + + + + + CALRR1 + CALRR1 + ADC calibration result register 1 + 0x48 + 0x20 + read-only + 0x00000000 + + + CALBOUT + offset result + 16 + 7 + + + CALC5OUT + C5 result + 8 + 8 + + + CALC4OUT + C4 result + 0 + 8 + + + + + CALRR2 + CALRR2 + ADC calibration result register 2 + 0x4C + 0x20 + read-only + 0x00000000 + + + CALC3OUT + C3 result + 24 + 8 + + + CALC2OUT + C2 result + 16 + 8 + + + CALC1OUT + C1 result + 8 + 8 + + + CALC0OUT + C0 result + 0 + 8 + + + + + CALFIR1 + CALFIR1 + ADC calibration factor input register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + CALBIO + Calibration offset factor input + 16 + 7 + + + CALC5IO + Calibration C5 factor input + 8 + 8 + + + CALC4IO + Calibration C4 factor input + 0 + 8 + + + + + CALFIR2 + CALFIR2 + ADC calibration factor input register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + CALC3IO + Calibration C3 factor input + 24 + 8 + + + CALC2IO + Calibration C2 factor input + 16 + 8 + + + CALC1IO + Calibration C1 factor input + 8 + 8 + + + CALC0IO + Calibration C0 factor input + 0 + 8 + + + + + CCR + CCR + ADC common configuration register + 0x308 + 0x20 + read-write + 0x00000000 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VREFEN + VREFINT enable + 22 + 1 + + + + + + + COMP1 + Comparator + COMP + 0x40010200 + + 0x0 + 0x10 + registers + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + CSR register lock + 31 + 1 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + Comparator power mode + selector + 18 + 2 + + + HYST + Comparator hysteresis enable + selector + 16 + 1 + + + POLARITY + Comparator polarity + selector + 15 + 1 + + + WINMODE + Comparator non-inverting input + selector for window mode + 11 + 1 + + + INPSEL + Comparator signal selector for + non-inverting input + 8 + 2 + + + INMSEL + Comparator signal selector for + inverting input INM + 4 + 4 + + + SCALER_EN + SCALER enable bit + 1 + 1 + + + COMP_EN + COMP enable bit + 0 + 1 + + + + + FR + FR + Comparator Filter + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT + Comparator filter and counter + 16 + 16 + + + FLTEN + Filter enable bit + 0 + 1 + + + + + + + COMP2 + Comparator + COMP + 0x40010210 + + 0x0 + 0x10 + registers + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + CSR register lock + 31 + 1 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + Comparator power mode + selector + 18 + 2 + + + POLARITY + Comparator polarity + selector + 15 + 1 + + + WINMODE + Comparator non-inverting input + selector for window mode + 11 + 1 + + + INPSEL + Comparator signal selector for + non-inverting input + 8 + 2 + + + INMSEL + Comparator signal selector for + inverting input INM + 4 + 4 + + + COMP_EN + COMP enable bit + 0 + 1 + + + + + FR + FR + Comparator Filter + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT + Comparator filter and counter + 16 + 16 + + + FLTEN + Filter enable bit + 0 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global Interrupt + 4 + + + + CR + CR + Clock control register + 0x0 + 0x20 + read-write + 0x00000100 + + + PLLRDY + PLL clock ready flag + 25 + 1 + + + PLLON + PLL enable + 24 + 1 + + + CSSON + Clock security system + enable + 19 + 1 + + + HSEBYP + HSE crystal oscillator + bypass + 18 + 1 + + + HSERDY + HSE clock ready flag + 17 + 1 + + + HSEON + HSE clock enable + 16 + 1 + + + HSIDIV + HSI16 clock division + factor + 11 + 3 + + + HSIRDY + HSI16 clock ready flag + 10 + 1 + + + HSIKERON + HSI16 always enable for peripheral + kernels + 9 + 1 + + + HSION + HSI16 clock enable + 8 + 1 + + + + + ICSCR + ICSCR + Internal clock sources calibration + register + 0x4 + 0x20 + 0x10000000 + + + LSI_STARTUP + LSI startup time + 26 + 2 + read-write + + + LSI_TRIM + LSI clock trimming + 16 + 9 + read-write + + + HSI_FS + HSI frequency selection + 13 + 3 + read-write + + + HSI_TRIM + HSI clock trimming + 0 + 13 + read-write + + + + + CFGR + CFGR + Clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output + prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock + output + 24 + 3 + read-write + + + PPRE + APB prescaler + 12 + 3 + read-write + + + HPRE + AHB prescaler + 8 + 4 + read-write + + + SWS + System clock switch status + 3 + 3 + read-only + + + SW + System clock switch + 0 + 3 + read-write + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0xC + 0x20 + 0x00000000 + + + PLLSRC + PLL clock source selection + 0 + 1 + read-write + + + + + ECSCR + ECSCR + External clock source control register + 0x10 + 0x20 + 0x00000000 + + + LSE_DRIVER + LSE clock driver selection + 16 + 2 + read-write + + + HSE_FREQ + HSE clock freqency selection + 2 + 2 + read-write + + + + + CIER + CIER + Clock interrupt enable + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PLLRDYIE + PLL ready interrupt enable + 5 + 1 + + + HSERDYIE + HSE ready interrupt enable + 4 + 1 + + + HSIRDYIE + HSI ready interrupt enable + 3 + 1 + + + LSERDYIE + LSE ready interrupt enable + 1 + 1 + + + LSIRDYIE + LSI ready interrupt enable + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + + + LSECSSF + LSE clock secure system interrupt flag + 9 + 1 + + + CSSF + HSE clock secure system interrupt flag + 8 + 1 + + + PLLRDYF + PLL ready interrupt flag + 5 + 1 + + + HSERDYF + HSE ready interrupt flag + 4 + 1 + + + HSIRDYF + HSI ready interrupt flag + 3 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + LSECSSC + LSE clock secure system interrupt flag clear + 9 + 1 + + + CSSC + clock secure system interrupt flag clear + 8 + 1 + + + PLLRDYC + PLL ready interrupt clear + 5 + 1 + + + HSERDYC + HSE ready interrupt clear + 4 + 1 + + + HSIRDYC + HSI ready interrupt clear + 3 + 1 + + + LSERDYC + LSE ready interrupt clear + 1 + 1 + + + LSIRDYC + LSI ready interrupt clear + 0 + 1 + + + + + IOPRSTR + IOPRSTR + GPIO reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + GPIOFRST + I/O port F reset + 5 + 1 + + + GPIOBRST + I/O port B reset + 1 + 1 + + + GPIOARST + I/O port A reset + 0 + 1 + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + CRCRST + CRC reset + 12 + 1 + + + DMARST + DMA reset + 0 + 1 + + + + + APBRSTR1 + APBRSTR1 + APB peripheral reset register + 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + LPTIMRST + Low Power Timer reset + 31 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DBGRST + Debug support reset + 27 + 1 + + + I2CRST + I2C reset + 21 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + TIM3RST + TIM3 timer reset + 1 + 1 + + + + + APBRSTR2 + APBRSTR2 + APB peripheral reset register + 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + LEDRST + LED reset + 23 + 1 + + + COMP2RST + COMP2 reset + 22 + 1 + + + COMP1RST + COMP1 reset + 21 + 1 + + + ADCRST + ADC reset + 20 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + TIM14RST + TIM14 timer reset + 15 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SYSCFGRST + SYSCFG and COMP + reset + 0 + 1 + + + + + IOPENR + IOPENR + GPIO clock enable register + 0x34 + 0x20 + read-write + 0x00000000 + + + GPIOFEN + I/O port F clock enable + 5 + 1 + + + GPIOBEN + I/O port B clock enable + 1 + 1 + + + GPIOAEN + I/O port A clock enable + 0 + 1 + + + + + AHBENR + AHBENR + AHB peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + CRCEN + CRC clock enable + 12 + 1 + + + SRAMEN + SRAM memory interface clock + enable + 9 + 1 + + + FLASHEN + Flash memory interface clock + enable + 8 + 1 + + + DMAEN + DMA clock enable + 0 + 1 + + + + + APBENR1 + APBENR1 + APB peripheral clock enable register + 1 + 0x3C + 0x20 + read-write + 0x00000000 + + + LPTIMEN + LPTIM clock enable + 31 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DBGEN + Debug support clock enable + 27 + 1 + + + I2CEN + I2C clock enable + 21 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + WWDGEN + WWDG clock enable + 11 + 1 + + + RTCAPBEN + RTC APB clock enable + 10 + 1 + + + TIM3EN + TIM3 timer clock enable + 1 + 1 + + + + + APBENR2 + APBENR2 + APB peripheral clock enable register + 2 + 0x40 + 0x20 + read-write + 0x00000000 + + + LEDEN + LED clock enable + 23 + 1 + + + COMP2EN + COMP2 clock enable + 22 + 1 + + + COMP1EN + COMP1 clock enable + 21 + 1 + + + ADCEN + ADC clock enable + 20 + 1 + + + TIM17EN + TIM16 timer clock enable + 18 + 1 + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + TIM14EN + TIM14 timer clock enable + 15 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TIM1EN + TIM1 timer clock enable + 11 + 1 + + + SYSCFGEN + SYSCFG, COMP and VREFBUF clock + enable + 0 + 1 + + + + + CCIPR + CCIPR + Peripherals independent clock configuration + register + 0x54 + 0x20 + read-write + 0x00000000 + + + LPTIM1SEL + LPTIM1 clock source + selection + 18 + 2 + + + COMP2SEL + COMP2 clock source + selection + 9 + 1 + + + COMP1SEL + COMP1 clock source + selection + 8 + 1 + + + PVDSEL + PVD detect clock source + selection + 7 + 1 + + + + + BDCR + BDCR + RTC domain control register + 0x5C + 0x20 + read-write + 0x00000000 + + + LSCOSEL + Low-speed clock output + selection + 25 + 1 + + + LSCOEN + Low-speed clock output (LSCO) + enable + 24 + 1 + + + BDRST + RTC domain software reset + 16 + 1 + + + RTCEN + RTC clock source enable + 15 + 1 + + + RTCSEL + RTC clock source selection + 8 + 2 + + + LSECSSD + LSE CSS detect + 6 + 1 + + + LSECSSON + LSE CSS enable + 5 + 1 + + + LSEBYP + LSE oscillator bypass + 2 + 1 + + + LSERDY + LSE oscillator ready + 1 + 1 + + + LSEON + LSE oscillator enable + 0 + 1 + + + + + CSR + CSR + Control/status register + 0x60 + 0x20 + read-write + 0x00000000 + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + + + IWDGRSTF + Independent window watchdog reset + flag + 29 + 1 + + + SFTRSTF + Software reset flag + 28 + 1 + + + PWRRSTF + BOR or POR/PDR flag + 27 + 1 + + + PINRSTF + Pin reset flag + 26 + 1 + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + + + RMVF + Remove reset flags + 23 + 1 + + + LSIRDY + LSI oscillator ready + 1 + 1 + + + LSION + LSI oscillator enable + 0 + 1 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Power control register 1 + 0x0 + 0x20 + read-write + 0x00030000 + + + HSION_CTRL + HSI open time control + 19 + 1 + + + SRAM_RETV + SRAM retention voltage control + 16 + 3 + + + LPR + Low-power run + 14 + 1 + + + FLS_SLPTIME + Flash wait time after wakeup from the stop mode + 12 + 2 + + + MRRDY_TIME + Time selection wakeup from LP to VR + 10 + 2 + + + VOS + Voltage scaling range + selection + 9 + 1 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + BIAS_CR_SEL + MR Bias current selection + 4 + 1 + + + BIAS_CR + MR Bias current + 0 + 4 + + + + + CR2 + CR2 + Power control register 2 + 0x4 + 0x20 + read-write + 0x00000500 + + + FLT_TIME + Digital filter time configuration + 9 + 3 + + + FLTEN + Digital filter enable + 8 + 1 + + + PVDT + Power voltage detector threshold + selection + 4 + 3 + + + SRCSEL + Power voltage detector volatage + selection + 2 + 1 + + + PVDE + Power voltage detector + enable + 0 + 1 + + + + + SR + SR + Power status register + 0x14 + 0x20 + read-only + 0x00000000 + + + PVDO + PVD output + 11 + 1 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x50000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xEBFFFFFF + + + MODE15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODE14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODE13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODE12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODE11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODE10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODE9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODE8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODE7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODE6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODE5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODE4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODE3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODE2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODE1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODE0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEED15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEED14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEED13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEED12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEED11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEED10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEED9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEED8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEED7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEED6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEED5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEED4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEED3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEED2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEED1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEED0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x24000000 + + + PUPD15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPD14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPD13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPD12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPD11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPD10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPD9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPD8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPD7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPD6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPD5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPD4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPD3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPD2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPD1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPD0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID15 + Port input data (y = 0..15) + 15 + 1 + + + ID14 + Port input data (y = 0..15) + 14 + 1 + + + ID13 + Port input data (y = 0..15) + 13 + 1 + + + ID12 + Port input data (y = 0..15) + 12 + 1 + + + ID11 + Port input data (y = 0..15) + 11 + 1 + + + ID10 + Port input data (y = 0..15) + 10 + 1 + + + ID9 + Port input data (y = 0..15) + 9 + 1 + + + ID8 + Port input data (y = 0..15) + 8 + 1 + + + ID7 + Port input data (y = 0..15) + 7 + 1 + + + ID6 + Port input data (y = 0..15) + 6 + 1 + + + ID5 + Port input data (y = 0..15) + 5 + 1 + + + ID4 + Port input data (y = 0..15) + 4 + 1 + + + ID3 + Port input data (y = 0..15) + 3 + 1 + + + ID2 + Port input data (y = 0..15) + 2 + 1 + + + ID1 + Port input data (y = 0..15) + 1 + 1 + + + ID0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD15 + Port output data (y = 0..15) + 15 + 1 + + + OD14 + Port output data (y = 0..15) + 14 + 1 + + + OD13 + Port output data (y = 0..15) + 13 + 1 + + + OD12 + Port output data (y = 0..15) + 12 + 1 + + + OD11 + Port output data (y = 0..15) + 11 + 1 + + + OD10 + Port output data (y = 0..15) + 10 + 1 + + + OD9 + Port output data (y = 0..15) + 9 + 1 + + + OD8 + Port output data (y = 0..15) + 8 + 1 + + + OD7 + Port output data (y = 0..15) + 7 + 1 + + + OD6 + Port output data (y = 0..15) + 6 + 1 + + + OD5 + Port output data (y = 0..15) + 5 + 1 + + + OD4 + Port output data (y = 0..15) + 4 + 1 + + + OD3 + Port output data (y = 0..15) + 3 + 1 + + + OD2 + Port output data (y = 0..15) + 2 + 1 + + + OD1 + Port output data (y = 0..15) + 1 + 1 + + + OD0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit 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Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + ARRM + Autoreload match + 1 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + PRELOAD + Registers update mode + 22 + 1 + + + PRESC + Clock prescaler + 9 + 3 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after read enable + 4 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global Interrupt + 27 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C0 + + + ABRRQ + Automate baudrate detection requeset + 12 + 1 + write-only + + + ABRE + Automate baudrate detection error flag + 11 + 1 + read-only + + + ABRF + Automate baudrate detection flag + 10 + 1 + read-only + + + CTS + CTS flag + 9 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + 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+ + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register (IWDG_KR) + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + + + PR + PR + Prescaler register (IWDG_PR) + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register (IWDG_RLR) + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value + 0 + 12 + + + + + SR + SR + Status register (IWDG_SR) + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value update + 1 + 1 + + + PVU + Watchdog prescaler value update + 0 + 1 + + + + + WINR + WINR + Window register (IWDG_SR) + 0x10 + 0x20 + read-only + 0x00000000 + + + WIN + window counter + 0 + 12 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window WatchDog Interrupt + 0 + + + + CR + CR + Control register (WWDG_CR) + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + (WWDG_CFR) + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early Wakeup Interrupt + 9 + 1 + + + WDGTB + Timer Base + 7 + 2 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register (WWDG_SR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early Wakeup Interrupt flag + 0 + 1 + + + + + + + TIM1 + Advanced timer + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 Break, Update, Trigger and Commutation Interrupt + 13 + + + TIM1_CC + TIM1 Capture Compare Interrupt + 14 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update 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Output compare 1 clear enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload enable + 3 + 1 + + + OC1FE + Output compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output Polarity + 15 + 1 + + + CC4P + Capture/Compare 4 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM14 + General purpose timer + TIM + 0x40002000 + + 0x00 + 0x400 + registers + + + TIM14 + TIM14 global Interrupt + 19 + + + + CR1 + CR1 + TIM14 control register1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Prescaler factor + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Compare/ + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Compare/capture 1 flag + 9 + 1 + + + CC1IF + Compare/capture 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Compare/capture1 event + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + OR + OR + Option register + 0x50 + 0x20 + read-write + 0x00000000 + + + TI1_RMP + TIM14 channel1 input remap + 0 + 2 + + + + + + + TIM16 + General purpose timer + TIM + 0x40014400 + + 0x00 + 0x400 + registers + + + TIM16 + TIM16 global Interrupt + 21 + + + + CR1 + CR1 + TIM16 control register1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Prescaler factor + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1DE + Compare/capture DMA requeset enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + Com interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Update interrupt flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + Com interrupt flag + 5 + 1 + + + CC1IF + Capture/Compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break event generation + 7 + 1 + + + COMG + COM evnet generation + 5 + 1 + + + CC1G + Capture/Compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM17 + 0x40014800 + + TIM17 + TIM17 global Interrupt + 22 + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x30 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register + 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + I2C_PF1_ANF + Analog filter enable control driving capability activation bits PF1 + 30 + 1 + + + I2C_PF0_ANF + Analog filter enable control driving capability activation bits PF0 + 29 + 1 + + + I2C_PB8_ANF + Analog filter enable control driving capability activation bits PB8 + 28 + 1 + + + I2C_PB7_ANF + Analog filter enable control driving capability activation bits PB7 + 27 + 1 + + + I2C_PB6_ANF + Analog filter enable control driving capability activation bits PB6 + 26 + 1 + + + I2C_PA12_ANF + Analog filter enable control driving capability activation bits PA12 + 25 + 1 + + + I2C_PA11_ANF + Analog filter enable control driving capability activation bits PA11 + 24 + 1 + + + I2C_PA10_ANF + Analog filter enable control driving capability activation bits PA10 + 23 + 1 + + + I2C_PA9_ANF + Analog filter enable control driving capability activation bits PA9 + 22 + 1 + + + I2C_PA8_ANF + Analog filter enable control driving capability activation bits PA8 + 21 + 1 + + + I2C_PA7_ANF + Analog filter enable control driving capability activation bits PA7 + 20 + 1 + + + I2C_PA3_ANF + Analog filter enable control driving capability activation bits PA3 + 19 + 1 + + + I2C_PA2_ANF + Analog filter enable control driving capability activation bits PA2 + 18 + 1 + + + MEM_MODE + Memory mapping selection bits + 0 + 2 + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + ETR_SRC_TIM1 + TIM1 ETR source selection + 9 + 2 + + + COMP2_BRK_TIM17 + COMP2 is enable to input of TIM17 break + 8 + 1 + + + COMP1_BRK_TIM17 + COMP1 is enable to input of TIM17 break + 7 + 1 + + + COMP2_BRK_TIM16 + COMP2 is enable to input of TIM16 break + 6 + 1 + + + COMP1_BRK_TIM16 + COMP1 is enable to input of TIM16 break + 5 + 1 + + + COMP2_BRK_TIM1 + COMP2 is enable to input of TIM1 break + 4 + 1 + + + COMP1_BRK_TIM1 + COMP1 is enable to input of TIM1 break + 3 + 1 + + + PVD_LOCK + PVD lock enable bit + 2 + 1 + + + LOCKUP_LOCK + Cortex-M0+ LOCKUP bit enable bit + 0 + 1 + + + + + CFGR3 + CFGR3 + SYSCFG configuration register + 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + DMA3_MAP + DMA channel3 requeset selection + 16 + 5 + + + DMA2_MAP + DMA channel2 requeset selection + 8 + 5 + + + DMA1_MAP + DMA channel1 requeset selection + 0 + 5 + + + + + + + DMA + Direct memory access + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA_Channel1 + DMA Channel 1 Interrupt + 9 + + + DMA_Channel2_3 + DMA Channel 2 and Channel 3 Interrupt + 10 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF3 + Channel 3 Transfer Error flag + 11 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete flag + 10 + 1 + + + TCIF3 + Channel 3 Transfer Complete flag + 9 + 1 + + + GIF3 + Channel 3 Global interrupt flag + 8 + 1 + + + TEIF2 + Channel 2 Transfer Error flag + 7 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete flag + 6 + 1 + + + TCIF2 + Channel 2 Transfer Complete flag + 5 + 1 + + + GIF2 + Channel 2 Global interrupt flag + 4 + 1 + + + TEIF1 + Channel 1 Transfer Error flag + 3 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete flag + 2 + 1 + + + TCIF1 + Channel 1 Transfer Complete flag + 1 + 1 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + (DMA_IFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + + + CCR1 + CCR1 + DMA channel configuration register + (DMA_CCR) + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel configuration register + (DMA_CCR) + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel configuration register + (DMA_CCR) + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global Interrupt + 3 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 1 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEY + Flash key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY + Busy + 16 + 1 + + + OPTVERR + Option and Engineering bits loading + validity error + 15 + 1 + + + WRPERR + Write protected error + 4 + 1 + + + EOP + End of operation + 0 + 1 + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + OBL_LAUNCH + Force the option byte + loading + 27 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + PGTSTRT + Flash main memory program start + 19 + 1 + + + OPTSTRT + Option byte program start + 17 + 1 + + + SER + Sector erase + 11 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0x4F55B0AA + + + nBOOT1 + Boot configuration + 15 + 1 + + + NRST_MODE + NRST_MODE + 14 + 1 + + + WWDG_SW + Window watchdog selection + 13 + 1 + + + IDWG_SW + Independent watchdog + selection + 12 + 1 + + + BORF_LEV + These bits contain the VDD supply level + threshold that activates the reset + 9 + 3 + + + BOREN + BOR reset Level + 8 + 1 + + + RDP + Read Protection + 0 + 8 + + + + + SDKR + SDKR + Flash SDK address + register + 0x24 + 0x20 + read-write + 0xFFE0001F + + + SDK_END + SDK area end address + 8 + 5 + + + SDK_STRT + SDK area start address + 0 + 5 + + + + + WRPR + WRPR + Flash WRP address + register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + WRP + WRP address + 0 + 16 + + + + + STCR + STCR + Flash sleep time config + register + 0x90 + 0x20 + read-write + 0x00006400 + + + SLEEP_TIME + FLash sleep time configuration(counter based on HSI_10M) + 8 + 8 + + + SLEEP_EN + FLash sleep enable + 0 + 1 + + + + + TS0 + TS0 + Flash TS0 + register + 0x100 + 0x20 + read-write + 0x000000B4 + + + TS0 + FLash TS0 register + 0 + 8 + + + + + TS1 + TS1 + Flash TS1 + register + 0x104 + 0x20 + read-write + 0x000001B0 + + + TS1 + FLash TS1 register + 0 + 9 + + + + + TS2P + TS2P + Flash TS2P + register + 0x108 + 0x20 + read-write + 0x000000B4 + + + TS2P + FLash TS2P register + 0 + 8 + + + + + TPS3 + TPS3 + Flash TPS3 + register + 0x10C + 0x20 + read-write + 0x000006C0 + + + TPS3 + FLash TPS3 register + 0 + 11 + + + + + TS3 + TS3 + Flash TS3 + register + 0x110 + 0x20 + read-write + 0x000000B4 + + + TS3 + FLash TS3 register + 0 + 8 + + + + + PERTPE + PERTPE + Flash PERTPE + register + 0x114 + 0x20 + read-write + 0x0000EA60 + + + PERTPE + FLash PERTPE register + 0 + 17 + + + + + SMERTPE + SMERTPE + Flash SMERTPE + register + 0x118 + 0x20 + read-write + 0x0000FD20 + + + SMERTPE + FLash SMERTPE register + 0 + 17 + + + + + PRGTPE + PRGTPE + Flash PRGTPE + register + 0x11C + 0x20 + read-write + 0x00008CA0 + + + PRGTPE + FLash PRGTPE register + 0 + 16 + + + + + PRETPE + PRETPE + Flash PRETPE + register + 0x120 + 0x20 + read-write + 0x000012C0 + + + PRETPE + FLash PRETPE register + 0 + 13 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global Interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional mode + 14 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave selection + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + SLVFM + Slave fast mode enable + 15 + 1 + + + LDMA_TX + Last DAM Transmit(TX) + 14 + 1 + + + LDMA_RX + Last DAM Transmit(RX) + 13 + 1 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + DS + Data length + 11 + 1 + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global Interrupt + 26 + + + + I2C + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global Interrupt + 23 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADD + Interface address + 1 + 7 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave mode) + 4 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + GENCALL + General call address (Slave mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode (Master mode) + 0 + 6 + + + + + + + LED + LED CONTROLLER + LED + 0x40002400 + + 0x0 + 0x400 + registers + + + LED + LED global Interrupt + 30 + + + + CR + LED_CR + Control register + 0x0 + 0x20 + read-write + 0x0000 + + + EHS + Light control + 12 + 2 + + + IE + LED interrupt enable + 3 + 1 + + + LED_COM_SEL + LED COM Selection + 1 + 2 + + + LEDON + LED enable + 0 + 1 + + + + + PR + LED_PR + Prescaler register + 0x4 + 0x20 + read-write + 0x0000 + + + PR + Prescaler control + 0 + 8 + + + + + TR + LED_TR + Time register + 0x8 + 0x20 + read-write + 0x0000 + + + T2 + Switch time + 8 + 8 + + + T1 + Light on time + 0 + 8 + + + + + DR0 + LED_DR0 + Data0 register + 0x0C + 0x20 + read-write + 0x0000 + + + DATA0_DP + 8-bit data register + 7 + 1 + + + DATA0_G + 8-bit data register + 6 + 1 + + + DATA0_F + 8-bit data register + 5 + 1 + + + DATA0_E + 8-bit data register + 4 + 1 + + + DATA0_D + 8-bit data register + 3 + 1 + + + DATA0_C + 8-bit data register + 2 + 1 + + + DATA0_B + 8-bit data register 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DATA3_DP + 8-bit data register + 7 + 1 + + + DATA3_G + 8-bit data register + 6 + 1 + + + DATA3_F + 8-bit data register + 5 + 1 + + + DATA3_E + 8-bit data register + 4 + 1 + + + DATA3_D + 8-bit data register + 3 + 1 + + + DATA3_C + 8-bit data register + 2 + 1 + + + DATA3_B + 8-bit data register + 1 + 1 + + + DATA3_A + 8-bit data register + 0 + 1 + + + + + IR + LED_IR + Interrupt register 1 + 0x1C + 0x20 + 0x0000 + + + FLAG + interrupt flag + 0 + 1 + read-write + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + CR + CR + Debug MCU Configuration Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + + + APB_FZ1 + APB_FZ1 + APB Freeze Register1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER3_STOP + Debug Timer 3 stopped when Core is halted + 1 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when Core is halted + 12 + 1 + + + DBG_LPTIM_STOP + Debug LPTIM stopped when Core is halted + 31 + 1 + + + + + APB_FZ2 + APB_FZ2 + APB Freeze Register2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER1_STOP + Debug Timer 1 stopped when Core is halted + 11 + 1 + + + DBG_TIMER14_STOP + Debug Timer 14 stopped when Core is halted + 15 + 1 + + + DBG_TIMER16_STOP + Debug Timer 16 stopped when Core is halted + 17 + 1 + + + DBG_TIMER17_STOP + Debug Timer 17 stopped when Core is halted + 18 + 1 + + + + + + +