diff --git a/misc/svd/py32f030xx.svd b/misc/svd/py32f030xx.svd
index 7a72303..8afdb39 100644
--- a/misc/svd/py32f030xx.svd
+++ b/misc/svd/py32f030xx.svd
@@ -66,8 +66,7 @@
OVR
- ADC group regular overrun
- flag
+ ADC group regular overrun flag
4
1
@@ -87,8 +86,7 @@
EOSMP
- ADC group regular end of sampling
- flag
+ ADC group regular end of sampling flag
1
1
@@ -189,29 +187,25 @@
AWDCH
- ADC analog watchdog monitored channel
- selection
+ ADC analog watchdog monitored channel selection
26
4
AWDEN
- ADC analog watchdog enable on scope
- ADC group regular
+ ADC analog watchdog enable
23
1
AWDSGL
- ADC analog watchdog monitoring a
- single channel or all channels
+ ADC analog watchdog monitoring a single channel or all channels
22
1
DISCEN
- ADC group regular sequencer
- discontinuous mode
+ ADC Discontinuous mode (sample only one channel in group per conversion start)
16
1
@@ -223,29 +217,25 @@
CONT
- ADC group regular continuous conversion
- mode
+ ADC Continuous conversion mode
13
1
OVRMOD
- ADC group regular overrun
- configuration
+ ADC continue converting when overflow is set
12
1
EXTEN
- ADC group regular external trigger
- polarity
+ ADC group regular external trigger polarity
10
2
EXTSEL
- ADC group regular external trigger
- source
+ ADC group regular external trigger source
6
3
@@ -269,8 +259,7 @@
DMACFG
- ADC DMA transfer
- configuration
+ ADC DMA transfer configuration
1
1
@@ -671,43 +660,37 @@
PWRMODE
- Comparator power mode
- selector
+ Comparator power mode selector
18
2
HYST
- Comparator hysteresis enable
- selector
+ Comparator hysteresis enable selector
16
1
POLARITY
- Comparator polarity
- selector
+ Comparator polarity selector
15
1
WINMODE
- Comparator non-inverting input
- selector for window mode
+ Comparator non-inverting input selector for window mode
11
1
INPSEL
- Comparator signal selector for
- non-inverting input
+ Comparator signal selector for non-inverting input
8
2
INMSEL
- Comparator signal selector for
- inverting input INM
+ Comparator signal selector for inverting input INM
4
4
@@ -728,8 +711,7 @@
FR
FR
- Comparator Filter
- register
+ Comparator Filter register
0x4
0x20
read-write
@@ -785,36 +767,31 @@
PWRMODE
- Comparator power mode
- selector
+ Comparator power mode selector
18
2
POLARITY
- Comparator polarity
- selector
+ Comparator polarity selector
15
1
WINMODE
- Comparator non-inverting input
- selector for window mode
+ Comparator non-inverting input selector for window mode
11
1
INPSEL
- Comparator signal selector for
- non-inverting input
+ Comparator signal selector for non-inverting input
8
2
INMSEL
- Comparator signal selector for
- inverting input INM
+ Comparator signal selector for inverting input INM
4
4
@@ -829,8 +806,7 @@
FR
FR
- Comparator Filter
- register
+ Comparator Filter register
0x4
0x20
read-write
@@ -891,15 +867,13 @@
CSSON
- Clock security system
- enable
+ Clock security system enable
19
1
HSEBYP
- HSE crystal oscillator
- bypass
+ HSE crystal oscillator bypass
18
1
@@ -917,27 +891,25 @@
HSIDIV
- HSI16 clock division
- factor
+ HSI clock division factor
11
3
HSIRDY
- HSI16 clock ready flag
+ HSI clock ready flag
10
1
HSIKERON
- HSI16 always enable for peripheral
- kernels
+ HSI always enable for peripheral kernels
9
1
HSION
- HSI16 clock enable
+ HSI clock enable
8
1
@@ -946,8 +918,7 @@
ICSCR
ICSCR
- Internal clock sources calibration
- register
+ Internal clock sources calibration register
0x4
0x20
0x10000000
@@ -992,16 +963,14 @@
MCOPRE
- Microcontroller clock output
- prescaler
+ Microcontroller clock output prescaler
28
3
read-write
MCOSEL
- Microcontroller clock
- output
+ Microcontroller clock output
24
3
read-write
@@ -1080,8 +1049,7 @@
CIER
CIER
- Clock interrupt enable
- register
+ Clock interrupt enable register
0x18
0x20
read-write
@@ -1280,8 +1248,7 @@
APBRSTR1
APBRSTR1
- APB peripheral reset register
- 1
+ APB peripheral reset register 1
0x2C
0x20
read-write
@@ -1334,8 +1301,7 @@
APBRSTR2
APBRSTR2
- APB peripheral reset register
- 2
+ APB peripheral reset register 2
0x30
0x20
read-write
@@ -1442,8 +1408,7 @@
AHBENR
AHBENR
- AHB peripheral clock enable
- register
+ AHB peripheral clock enable register
0x38
0x20
read-write
@@ -1457,15 +1422,13 @@
SRAMEN
- SRAM memory interface clock
- enable
+ SRAM memory interface clock enable
9
1
FLASHEN
- Flash memory interface clock
- enable
+ Flash memory interface clock enable
8
1
@@ -1480,8 +1443,7 @@
APBENR1
APBENR1
- APB peripheral clock enable register
- 1
+ APB peripheral clock enable register 1
0x3C
0x20
read-write
@@ -1495,8 +1457,7 @@
PWREN
- Power interface clock
- enable
+ Power interface clock enable
28
1
@@ -1547,8 +1508,7 @@
APBENR2
APBENR2
- APB peripheral clock enable register
- 2
+ APB peripheral clock enable register 2
0x40
0x20
read-write
@@ -1616,8 +1576,7 @@
SYSCFGEN
- SYSCFG, COMP and VREFBUF clock
- enable
+ SYSCFG, COMP and VREFBUF clock enable
0
1
@@ -1626,8 +1585,7 @@
CCIPR
CCIPR
- Peripherals independent clock configuration
- register
+ Peripherals independent clock configuration register
0x54
0x20
read-write
@@ -1635,29 +1593,25 @@
LPTIM1SEL
- LPTIM1 clock source
- selection
+ LPTIM1 clock source selection
18
2
COMP2SEL
- COMP2 clock source
- selection
+ COMP2 clock source selection
9
1
COMP1SEL
- COMP1 clock source
- selection
+ COMP1 clock source selection
8
1
PVDSEL
- PVD detect clock source
- selection
+ PVD detect clock source selection
7
1
@@ -1674,15 +1628,13 @@
LSCOSEL
- Low-speed clock output
- selection
+ Low-speed clock output selection
25
1
LSCOEN
- Low-speed clock output (LSCO)
- enable
+ Low-speed clock output (LSCO) enable
24
1
@@ -1753,8 +1705,7 @@
IWDGRSTF
- Independent window watchdog reset
- flag
+ Independent window watchdog reset flag
29
1
@@ -1778,8 +1729,7 @@
OBLRSTF
- Option byte loader reset
- flag
+ Option byte loader reset flag
25
1
@@ -1857,15 +1807,13 @@
VOS
- Voltage scaling range
- selection
+ Voltage scaling range selection
9
1
DBP
- Disable backup domain write
- protection
+ Disable backup domain write protection
8
1
@@ -1906,22 +1854,19 @@
PVDT
- Power voltage detector threshold
- selection
+ Power voltage detector threshold selection
4
3
SRCSEL
- Power voltage detector volatage
- selection
+ Power voltage detector volatage selection
2
1
PVDE
- Power voltage detector
- enable
+ Power voltage detector enable
0
1
@@ -2174,8 +2119,7 @@
OSPEEDR
OSPEEDR
- GPIO port output speed
- register
+ GPIO port output speed register
0x8
0x20
read-write
@@ -2282,8 +2226,7 @@
PUPDR
PUPDR
- GPIO port pull-up/pull-down
- register
+ GPIO port pull-up/pull-down register
0xC
0x20
read-write
@@ -2604,8 +2547,7 @@
BSRR
BSRR
- GPIO port bit set/reset
- register
+ GPIO port bit set/reset register
0x18
0x20
write-only
@@ -2808,8 +2750,7 @@
LCKR
LCKR
- GPIO port configuration lock
- register
+ GPIO port configuration lock register
0x1C
0x20
read-write
@@ -2922,8 +2863,7 @@
AFRL
AFRL
- GPIO alternate function low
- register
+ GPIO alternate function low register
0x20
0x20
read-write
@@ -2931,57 +2871,49 @@
AFSEL7
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
28
4
AFSEL6
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
24
4
AFSEL5
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
20
4
AFSEL4
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
16
4
AFSEL3
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
12
4
AFSEL2
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
8
4
AFSEL1
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
4
4
AFSEL0
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
0
4
@@ -2990,8 +2922,7 @@
AFRH
AFRH
- GPIO alternate function high
- register
+ GPIO alternate function high register
0x24
0x20
read-write
@@ -2999,57 +2930,49 @@
AFSEL15
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
28
4
AFSEL14
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
24
4
AFSEL13
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
20
4
AFSEL12
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
16
4
AFSEL11
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
12
4
AFSEL10
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
8
4
AFSEL9
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
4
4
AFSEL8
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
0
4
@@ -3308,8 +3231,7 @@
OSPEEDR
OSPEEDR
- GPIO port output speed
- register
+ GPIO port output speed register
0x8
0x20
read-write
@@ -3374,8 +3296,7 @@
PUPDR
PUPDR
- GPIO port pull-up/pull-down
- register
+ GPIO port pull-up/pull-down register
0xC
0x20
read-write
@@ -3570,8 +3491,7 @@
BSRR
BSRR
- GPIO port bit set/reset
- register
+ GPIO port bit set/reset register
0x18
0x20
write-only
@@ -3690,8 +3610,7 @@
LCKR
LCKR
- GPIO port configuration lock
- register
+ GPIO port configuration lock register
0x1C
0x20
read-write
@@ -3762,8 +3681,7 @@
AFRL
AFRL
- GPIO alternate function low
- register
+ GPIO alternate function low register
0x20
0x20
read-write
@@ -3771,57 +3689,49 @@
AFSEL7
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
28
4
AFSEL6
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
24
4
AFSEL5
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
20
4
AFSEL4
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
16
4
AFSEL3
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
12
4
AFSEL2
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
8
4
AFSEL1
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
4
4
AFSEL0
- Alternate function selection for port x
- bit y (y = 0..7)
+ Alternate function selection for port x bit y (y = 0..7)
0
4
@@ -3830,8 +3740,7 @@
AFRH
AFRH
- GPIO alternate function high
- register
+ GPIO alternate function high register
0x24
0x20
read-write
@@ -3839,57 +3748,49 @@
AFSEL15
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
28
4
AFSEL14
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
24
4
AFSEL13
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
20
4
AFSEL12
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
16
4
AFSEL11
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
12
4
AFSEL10
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
8
4
AFSEL9
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
4
4
AFSEL8
- Alternate function selection for port x
- bit y (y = 8..15)
+ Alternate function selection for port x bit y (y = 8..15)
0
4
@@ -3968,8 +3869,7 @@
EXTI
- External interrupt/event
- controller
+ External interrupt/event controller
EXTI
0x40021800
@@ -4001,8 +3901,7 @@
RTSR
RTSR
- EXTI rising trigger selection
- register
+ EXTI rising trigger selection register
0x0
0x20
read-write
@@ -4010,134 +3909,115 @@
RT18
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
18
1
RT17
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
17
1
RT16
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
16
1
RT15
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
15
1
RT14
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
14
1
RT13
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
13
1
RT12
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
12
1
RT11
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
11
1
RT10
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
10
1
RT9
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
9
1
RT8
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
8
1
RT7
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
7
1
RT6
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
6
1
RT5
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
5
1
RT4
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
4
1
RT3
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
3
1
RT2
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
2
1
RT1
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
1
1
RT0
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
0
1
@@ -4146,8 +4026,7 @@
FTSR
FTSR
- EXTI falling trigger selection
- register
+ EXTI falling trigger selection register
0x4
0x20
read-write
@@ -4155,134 +4034,115 @@
FT18
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
18
1
FT17
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
17
1
FT16
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
16
1
FT15
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
15
1
FT14
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
14
1
FT13
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
13
1
FT12
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
12
1
FT11
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
11
1
FT10
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
10
1
FT9
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
9
1
FT8
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
8
1
FT7
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
7
1
FT6
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
6
1
FT5
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
5
1
FT4
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
4
1
FT3
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
3
1
FT2
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
2
1
FT1
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
1
1
FT0
- Falling trigger event configuration bit
- of Configurable Event input
+ Falling trigger event configuration bit of Configurable Event input
0
1
@@ -4291,8 +4151,7 @@
SWIER
SWIER
- EXTI software interrupt event
- register
+ EXTI software interrupt event register
0x8
0x20
read-write
@@ -4300,134 +4159,115 @@
SWI18
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
18
1
SWI17
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
17
1
SWI16
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
16
1
SWI15
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
15
1
SWI14
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
14
1
SWI13
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
13
1
SWI12
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
12
1
SWI11
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
11
1
SWI10
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
10
1
SWI9
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
9
1
SWI8
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
8
1
SWI7
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
7
1
SWI6
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
6
1
SWI5
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
5
1
SWI4
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
4
1
SWI3
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
3
1
SWI2
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
2
1
SWI1
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
1
1
SWI0
- Rising trigger event configuration bit
- of Configurable Event input
+ Rising trigger event configuration bit of Configurable Event input
0
1
@@ -4436,8 +4276,7 @@
PR
PR
- EXTI pending
- register
+ EXTI pending register
0xC
0x20
read-write
@@ -4445,134 +4284,115 @@
PR18
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
18
1
PR17
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
17
1
PR16
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
16
1
PR15
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
15
1
PR14
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
14
1
PR13
- configurable event inputs x rising edge
- Pending bit
+ configurable event inputs x rising edge pending bit
13
1
PR12
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
12
1
PR11
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
11
1
PR10
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
10
1
PR9
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
9
1
PR8
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
8
1
PR7
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
7
1
PR6
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
6
1
PR5
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
5
1
PR4
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
4
1
PR3
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
3
1
PR2
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
2
1
PR1
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
1
1
PR0
- configurable event inputs x rising edge
- Pending bit.
+ configurable event inputs x rising edge pending bit
0
1
@@ -4581,8 +4401,7 @@
EXTICR1
EXTICR1
- EXTI external interrupt selection
- register
+ EXTI external interrupt selection register
0x60
0x20
read-write
@@ -4617,8 +4436,7 @@
EXTICR2
EXTICR2
- EXTI external interrupt selection
- register
+ EXTI external interrupt selection register
0x64
0x20
read-write
@@ -4653,8 +4471,7 @@
EXTICR3
EXTICR3
- EXTI external interrupt selection
- register
+ EXTI external interrupt selection register
0x68
0x20
read-write
@@ -4671,8 +4488,7 @@
IMR
IMR
- EXTI CPU wakeup with interrupt mask
- register
+ EXTI CPU wakeup with interrupt mask register
0x80
0x20
read-write
@@ -4680,148 +4496,127 @@
IM29
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
29
1
IM19
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
19
1
IM18
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
18
1
IM17
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
17
1
IM16
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
16
1
IM15
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
15
1
IM14
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
14
1
IM13
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
13
1
IM12
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
12
1
IM11
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
11
1
IM10
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
10
1
IM9
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
9
1
IM8
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
8
1
IM7
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
7
1
IM6
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
6
1
IM5
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
5
1
IM4
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
4
1
IM3
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
3
1
IM2
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
2
1
IM1
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
1
1
IM0
- CPU wakeup with interrupt mask on event
- input
+ CPU wakeup with interrupt mask on event input
0
1
@@ -4830,8 +4625,7 @@
EMR
EMR
- EXTI CPU wakeup with event mask
- register
+ EXTI CPU wakeup with event mask register
0x84
0x20
read-write
@@ -4839,148 +4633,127 @@
EM29
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
29
1
EM19
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
19
1
EM18
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
18
1
EM17
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
17
1
EM16
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
16
1
EM15
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
15
1
EM14
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
14
1
EM13
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
13
1
EM12
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
12
1
EM11
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
11
1
EM10
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
10
1
EM9
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
9
1
EM8
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
8
1
EM7
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
7
1
EM6
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
6
1
EM5
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
5
1
EM4
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
4
1
EM3
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
3
1
EM2
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
2
1
EM1
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
1
1
EM0
- CPU wakeup with event mask on event
- input
+ CPU wakeup with event mask on event input
0
1
@@ -5027,8 +4800,7 @@
ARRMCF
- Autoreload match Clear
- Flag
+ Autoreload match Clear flag
1
1
@@ -5045,8 +4817,7 @@
ARRMIE
- Autoreload match Interrupt
- Enable
+ Autoreload match Interrupt enable
1
1
@@ -5142,8 +4913,7 @@
USART1
- Universal synchronous asynchronous receiver
- transmitter
+ Universal synchronous asynchronous receiver transmitter
USART
0x40013800
@@ -5346,8 +5116,7 @@
TCIE
- Transmission complete interrupt
- enable
+ Transmission complete interrupt enable
6
1
@@ -5599,8 +5368,7 @@
RSF
- Registers Synchronized
- Flag
+ Registers Synchronized Flag
3
1
read-write
@@ -5631,8 +5399,7 @@
PRLH
PRLH
- RTC Prescaler Load Register
- High
+ RTC Prescaler Load Register High
0x8
0x20
write-only
@@ -5640,8 +5407,7 @@
PRLH
- RTC Prescaler Load Register
- High
+ RTC Prescaler Load Register High
0
4
@@ -5650,8 +5416,7 @@
PRLL
PRLL
- RTC Prescaler Load Register
- Low
+ RTC Prescaler Load Register Low
0xC
0x20
write-only
@@ -5659,8 +5424,7 @@
PRLL
- RTC Prescaler Divider Register
- Low
+ RTC Prescaler Divider Register Low
0
16
@@ -5669,8 +5433,7 @@
DIVH
DIVH
- RTC Prescaler Divider Register
- High
+ RTC Prescaler Divider Register High
0x10
0x20
read-only
@@ -5678,8 +5441,7 @@
DIVH
- RTC prescaler divider register
- high
+ RTC Prescaler Divider Register High
0
4
@@ -5688,8 +5450,7 @@
DIVL
DIVL
- RTC Prescaler Divider Register
- Low
+ RTC Prescaler Divider Register Low
0x14
0x20
read-only
@@ -5697,8 +5458,7 @@
DIVL
- RTC prescaler divider register
- Low
+ RTC Prescaler Divider Register Low
0
16
@@ -5961,8 +5721,7 @@
CFR
CFR
- Configuration register
- (WWDG_CFR)
+ Configuration register (WWDG_CFR)
0x4
0x20
read-write
@@ -7624,8 +7383,7 @@
CCER
CCER
- capture/compare enable
- register
+ capture/compare enable register
0x20
0x20
read-write
@@ -8926,8 +8684,7 @@
ISR
ISR
- DMA interrupt status register
- (DMA_ISR)
+ DMA interrupt status register (DMA_ISR)
0x0
0x20
read-only
@@ -9011,8 +8768,7 @@
IFCR
IFCR
- DMA interrupt flag clear register
- (DMA_IFCR)
+ DMA interrupt flag clear register (DMA_IFCR)
0x4
0x20
write-only
@@ -9020,85 +8776,73 @@
CTEIF3
- Channel 3 Transfer Error
- clear
+ Channel 3 Transfer Error clear
11
1
CHTIF3
- Channel 3 Half Transfer
- clear
+ Channel 3 Half Transfer clear
10
1
CTCIF3
- Channel 3 Transfer Complete
- clear
+ Channel 3 Transfer Complete clear
9
1
CGIF3
- Channel 3 Global interrupt
- clear
+ Channel 3 Global interrupt clear
8
1
CTEIF2
- Channel 2 Transfer Error
- clear
+ Channel 2 Transfer Error clear
7
1
CHTIF2
- Channel 2 Half Transfer
- clear
+ Channel 2 Half Transfer clear
6
1
CTCIF2
- Channel 2 Transfer Complete
- clear
+ Channel 2 Transfer Complete clear
5
1
CGIF2
- Channel 2 Global interrupt
- clear
+ Channel 2 Global interrupt clear
4
1
CTEIF1
- Channel 1 Transfer Error
- clear
+ Channel 1 Transfer Error clear
3
1
CHTIF1
- Channel 1 Half Transfer
- clear
+ Channel 1 Half Transfer clear
2
1
CTCIF1
- Channel 1 Transfer Complete
- clear
+ Channel 1 Transfer Complete clear
1
1
CGIF1
- Channel 1 Global interrupt
- clear
+ Channel 1 Global interrupt clear
0
1
@@ -9107,8 +8851,7 @@
CCR1
CCR1
- DMA channel configuration register
- (DMA_CCR)
+ DMA channel configuration register (DMA_CCR)
0x8
0x20
read-write
@@ -9164,22 +8907,19 @@
TEIE
- Transfer error interrupt
- enable
+ Transfer error interrupt enable
3
1
HTIE
- Half Transfer interrupt
- enable
+ Half Transfer interrupt enable
2
1
TCIE
- Transfer complete interrupt
- enable
+ Transfer complete interrupt enable
1
1
@@ -9194,8 +8934,7 @@
CNDTR1
CNDTR1
- DMA channel 1 number of data
- register
+ DMA channel 1 number of data register
0xC
0x20
read-write
@@ -9212,8 +8951,7 @@
CPAR1
CPAR1
- DMA channel 1 peripheral address
- register
+ DMA channel 1 peripheral address register
0x10
0x20
read-write
@@ -9230,8 +8968,7 @@
CMAR1
CMAR1
- DMA channel 1 memory address
- register
+ DMA channel 1 memory address register
0x14
0x20
read-write
@@ -9248,8 +8985,7 @@
CCR2
CCR2
- DMA channel configuration register
- (DMA_CCR)
+ DMA channel configuration register (DMA_CCR)
0x1C
0x20
read-write
@@ -9305,22 +9041,19 @@
TEIE
- Transfer error interrupt
- enable
+ Transfer error interrupt enable
3
1
HTIE
- Half Transfer interrupt
- enable
+ Half Transfer interrupt enable
2
1
TCIE
- Transfer complete interrupt
- enable
+ Transfer complete interrupt enable
1
1
@@ -9335,8 +9068,7 @@
CNDTR2
CNDTR2
- DMA channel 2 number of data
- register
+ DMA channel 2 number of data register
0x20
0x20
read-write
@@ -9353,8 +9085,7 @@
CPAR2
CPAR2
- DMA channel 2 peripheral address
- register
+ DMA channel 2 peripheral address register
0x24
0x20
read-write
@@ -9371,8 +9102,7 @@
CMAR2
CMAR2
- DMA channel 2 memory address
- register
+ DMA channel 2 memory address register
0x28
0x20
read-write
@@ -9389,8 +9119,7 @@
CCR3
CCR3
- DMA channel configuration register
- (DMA_CCR)
+ DMA channel configuration register (DMA_CCR)
0x30
0x20
read-write
@@ -9446,22 +9175,19 @@
TEIE
- Transfer error interrupt
- enable
+ Transfer error interrupt enable
3
1
HTIE
- Half Transfer interrupt
- enable
+ Half Transfer interrupt enable
2
1
TCIE
- Transfer complete interrupt
- enable
+ Transfer complete interrupt enable
1
1
@@ -9476,8 +9202,7 @@
CNDTR3
CNDTR3
- DMA channel 3 number of data
- register
+ DMA channel 3 number of data register
0x34
0x20
read-write
@@ -9494,8 +9219,7 @@
CPAR3
CPAR3
- DMA channel 3 peripheral address
- register
+ DMA channel 3 peripheral address register
0x38
0x20
read-write
@@ -9512,8 +9236,7 @@
CMAR3
CMAR3
- DMA channel 3 memory address
- register
+ DMA channel 3 memory address register
0x3C
0x20
read-write
@@ -9668,8 +9391,7 @@
EOPIE
- End of operation interrupt
- enable
+ End of operation interrupt enable
24
1
@@ -9740,8 +9462,7 @@
IDWG_SW
- Independent watchdog
- selection
+ Independent watchdog selection
12
1
@@ -9769,8 +9490,7 @@
SDKR
SDKR
- Flash SDK address
- register
+ Flash SDK address register
0x24
0x20
read-write
@@ -9793,8 +9513,7 @@
WRPR
WRPR
- Flash WRP address
- register
+ Flash WRP address register
0x2C
0x20
read-write
@@ -9811,8 +9530,7 @@
STCR
STCR
- Flash sleep time config
- register
+ Flash sleep time config register
0x90
0x20
read-write
@@ -9835,8 +9553,7 @@
TS0
TS0
- Flash TS0
- register
+ Flash TS0 register
0x100
0x20
read-write
@@ -9853,8 +9570,7 @@
TS1
TS1
- Flash TS1
- register
+ Flash TS1 register
0x104
0x20
read-write
@@ -9871,8 +9587,7 @@
TS2P
TS2P
- Flash TS2P
- register
+ Flash TS2P register
0x108
0x20
read-write
@@ -9889,8 +9604,7 @@
TPS3
TPS3
- Flash TPS3
- register
+ Flash TPS3 register
0x10C
0x20
read-write
@@ -9907,8 +9621,7 @@
TS3
TS3
- Flash TS3
- register
+ Flash TS3 register
0x110
0x20
read-write
@@ -9925,8 +9638,7 @@
PERTPE
PERTPE
- Flash PERTPE
- register
+ Flash PERTPE register
0x114
0x20
read-write
@@ -9943,8 +9655,7 @@
SMERTPE
SMERTPE
- Flash SMERTPE
- register
+ Flash SMERTPE register
0x118
0x20
read-write
@@ -9961,8 +9672,7 @@
PRGTPE
PRGTPE
- Flash PRGTPE
- register
+ Flash PRGTPE register
0x11C
0x20
read-write
@@ -9979,8 +9689,7 @@
PRETPE
PRETPE
- Flash PRETPE
- register
+ Flash PRETPE register
0x120
0x20
read-write