d95af918fa
lots of code copied over, things filled in to hopefully get the LED matrix lighting up. untested.
102 lines
3.1 KiB
C
102 lines
3.1 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : system_ch32x035.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2023/04/06
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* Description : CH32X035 Device Peripheral Access Layer System Source File.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32x035.h"
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/*
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
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* reset the HSI is used as SYSCLK source).
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*/
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//#define SYSCLK_FREQ_8MHz_HSI 8000000
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//#define SYSCLK_FREQ_12MHz_HSI 12000000
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//#define SYSCLK_FREQ_16MHz_HSI 16000000
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//#define SYSCLK_FREQ_24MHz_HSI 24000000
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//#define SYSCLK_FREQ_48MHz_HSI HSI_VALUE
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/* Clock Definitions */
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uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
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__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
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/*********************************************************************
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* @fn SystemInit
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*
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
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* update the SystemCoreClock variable.
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*
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* @return none
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*/
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void SystemInit(void)
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{
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RCC->CTLR |= (uint32_t)0x00000001;
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RCC->CFGR0 |= (uint32_t)0x00000050;
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RCC->CFGR0 &= (uint32_t)0xF8FFFF5F;
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SetSysClock_HSI(HCLK_24MHZ);
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}
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/*********************************************************************
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* @fn SystemCoreClockUpdate
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*
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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*
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* @return none
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0;
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SystemCoreClock = HSI_VALUE;
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tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
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if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8)
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{
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SystemCoreClock /= tmp;
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}
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else
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{
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SystemCoreClock >>= tmp;
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}
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}
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/*********************************************************************
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* @fn SetSysClock_HSI
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*
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* @brief Sets System clock frequency to specified and configure HCLK prescalers.
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*
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* @return none
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*/
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void SetSysClock_HSI(uint32_t divider)
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{
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uint32_t actlr;
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/* Flash 2 wait state */
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actlr = FLASH->ACTLR & ((uint32_t)~FLASH_ACTLR_LATENCY);
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FLASH->ACTLR = actlr | (uint32_t)FLASH_ACTLR_LATENCY_2;
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/* HCLK = SYSCLK = APB1 */
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RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
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RCC->CFGR0 |= (uint32_t)divider;
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// set wait states depending on speed
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if (divider > RCC_HPRE_DIV1) { // 48MHz is already set to 2 cycles
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if (divider >= RCC_HPRE_DIV1) { // 24MHz is 1 cycle
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actlr |= (uint32_t)FLASH_ACTLR_LATENCY_0;
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} else { // all others are 0 cycle
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actlr |= (uint32_t)FLASH_ACTLR_LATENCY_1;
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}
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FLASH->ACTLR = actlr;
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}
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}
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