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initial commit of "complete" codebase

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everything is completely untested. I'm sure most of this shit doesn't work and will be fixed when and if I get hardware.
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2024-07-28 15:28:03 -07:00
commit a675f6d19b
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40
code/ch32v003_bootloader/user/ch32v00x_conf.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_conf.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/08/08
* Description : Library configuration file.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_CONF_H
#define __CH32V00x_CONF_H
#include <ch32v00x_adc.h>
#include <ch32v00x_dbgmcu.h>
#include <ch32v00x_dma.h>
#include <ch32v00x_exti.h>
#include <ch32v00x_flash.h>
#include <ch32v00x_gpio.h>
#include <ch32v00x_i2c.h>
#include <ch32v00x_it.h>
#include <ch32v00x_iwdg.h>
#include <ch32v00x_misc.h>
#include <ch32v00x_pwr.h>
#include <ch32v00x_rcc.h>
#include <ch32v00x_spi.h>
#include <ch32v00x_tim.h>
#include <ch32v00x_usart.h>
#include <ch32v00x_wwdg.h>
#include <ch32v00x_opa.h>
#endif /* __CH32V00x_CONF_H */

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code/ch32v003_bootloader/user/ch32v00x_it.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_it.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/12/25
* Description : Main Interrupt Service Routines.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_it.h>
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
/*********************************************************************
* @fn NMI_Handler
*
* @brief This function handles NMI exception.
*
* @return none
*/
void NMI_Handler(void)
{
while (1)
{
}
}
/*********************************************************************
* @fn HardFault_Handler
*
* @brief This function handles Hard Fault exception.
*
* @return none
*/
void HardFault_Handler(void)
{
while (1)
{
}
}

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code/ch32v003_bootloader/user/ch32v00x_it.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_it.h
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file contains the headers of the interrupt handlers.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_IT_H
#define __CH32V00x_IT_H
#include "debug.h"
#endif /* __CH32V00x_IT_H */

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code/ch32v003_bootloader/user/flash.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : iap.c
* Author : WCH
* Version : V1.0.0
* Date : 2022/11/21
* Description : CH32V003 fast program
*******************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "flash.h"
#include "string.h"
u32 Verity_buf[32];
/*********************************************************************
* @fn CH32_IAP_Program
*
* @brief adr - 64Byte stand
* buf - 64Byte stand
*
* @return none
*/
void CH32_IAP_Program(u32 adr, u32* buf)
{
adr &= 0xFFFFFFC0;
FLASH_BufReset();
for(int j=0;j<16;j++)
{
FLASH_BufLoad(adr+4*j, buf[j]);
}
FLASH_ProgramPage_Fast(adr);
}

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code/ch32v003_bootloader/user/flash.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : falsh.h
* Author : WCH
* Version : V1.0.0
* Date : 2022/11/21
* Description :
*******************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __FLASH_H
#define __FLASH_H
#include "ch32v00x_it.h"
#include "stdio.h"
u8 CH32_IAP_Verity(u32 adr, u32* buf);
void CH32_IAP_Program(u32 adr, u32* buf);
void CH32_IAP_ERASE(u32 Start_adr, u32 End_adr);
#endif

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code/ch32v003_bootloader/user/iap.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : iap.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/12/21
* Description : IAP
*******************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "iap.h"
#include "string.h"
#include "flash.h"
#include "core_riscv.h"
/******************************************************************************/
#define FLASH_Base 0x08000000
#define USBD_DATA_SIZE 64
u32 Program_addr = FLASH_Base;
u32 Verity_addr = FLASH_Base;
u8 Verity_Star_flag = 0;
u8 Fast_Program_Buf[128];
u16 CodeLen = 0;
u8 End_Flag = 0;
u8 EP2_Rx_Buffer[USBD_DATA_SIZE];
#define isp_cmd_t ((isp_cmd *)EP2_Rx_Buffer)
/*********************************************************************
* @fn USART1_CFG
*
* @brief GPIOD-USART1 init
*
* @return
*/
void USART1_CFG(u32 baudrate)
{
// configure GPIO pins for USART mode
GPIOD->CFGLR = 0x48B44444; // Set GPIOD Mode, Speed
GPIOD->BCR = (((uint32_t)0x01) << 6);
// configure USART
USART1->CTLR2 |= USART_StopBits_1;
USART1->CTLR1 = USART_Parity_No | USART_Mode_Rx | USART_Mode_Tx; // Set USART mode, Parity
USART1->CTLR3 |= USART_HardwareFlowControl_None;
USART1->BRR = (8 << 4) | 11; // 115200; use 0x34 for 460800
USART1->CTLR1 |= ((uint16_t)0x2000); // enable USART
}
/*********************************************************************
* @fn RecData_Deal
*
* @brief UART-USB
*
* @return ERR_ERROR - ERROR
* ERR_SCUESS - SCUESS
* ERR_End - End
*/
u8 RecData_Deal(void)
{
u8 i, s, Lenth;
Lenth = isp_cmd_t->Len;
switch ( isp_cmd_t->Cmd) {
case CMD_IAP_ERASE:
FLASH_Unlock_Fast();
FLASH_EraseAllPages();
s = ERR_SCUESS;
break;
case CMD_IAP_PROM:
for (i = 0; i < Lenth; i++) {
Fast_Program_Buf[CodeLen + i] = isp_cmd_t->data[i];
}
CodeLen += Lenth;
if (CodeLen >= 64) {
CH32_IAP_Program(Program_addr, (u32*) Fast_Program_Buf);
CodeLen -= 64;
for (i = 0; i < CodeLen; i++) {
Fast_Program_Buf[i] = Fast_Program_Buf[64 + i];
}
Program_addr += 0x40;
}
s = ERR_SCUESS;
break;
case CMD_IAP_VERIFY:
if (Verity_Star_flag == 0) {
Verity_Star_flag = 1;
for (i = 0; i < (64 - CodeLen); i++) {
Fast_Program_Buf[CodeLen + i] = 0xFF;
}
CH32_IAP_Program(Program_addr, (u32*) Fast_Program_Buf);
CodeLen = 0;
}
s = ERR_SCUESS;
for (i = 0; i < Lenth; i++) {
if (isp_cmd_t->data[i] != *(u8*) (Verity_addr + i)) {
s = ERR_ERROR;
break;
}
}
Verity_addr += Lenth;
break;
case CMD_IAP_END:
Verity_Star_flag = 0;
End_Flag = 1;
Program_addr = FLASH_Base;
Verity_addr = FLASH_Base;
s = ERR_End;
FLASH->CTLR |= ((uint32_t)0x00008000);
FLASH->CTLR |= ((uint32_t)0x00000080);
break;
default:
s = ERR_ERROR;
break;
}
return s;
}
/*********************************************************************
* @fn GPIO_Cfg_init
*
* @brief GPIOC init
*
* @return none
*/
void GPIO_Cfg_init(void)
{
}
/*********************************************************************
* @fn PC0_Check
*
* @brief Check PC0 state
*
* @return 1 - IAP
* 0 - APP
*/
u8 btn2_pushed(void)
{
// configure GPIOC
GPIOC->BCR = GPIO_Pin_4; // configure pull-down
GPIOC->CFGLR &= ~(0x04 << (4 * 4)); // clear PC4 config
GPIOC->CFGLR |= 0x08 << (4 * 4); // configure PC4 as pullup/down input
// GPIOC->BSHR = ((uint32_t)0x01);
// is button pushed (active high)?
return (GPIOC->INDR & GPIO_Pin_4); // ^ GPIO_Pin_4;
}
/*********************************************************************
* @fn UART3_SendMultiyData
*
* @brief Deal device Endpoint 3 OUT.
*
* @param l: Data length.
*
* @return none
*/
void UART1_SendMultiyData(u8* pbuf, u8 num)
{
u8 i = 0;
while(i<num)
{
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
USART_SendData(USART1, pbuf[i]);
i++;
}
}
/*********************************************************************
* @fn UART1_SendMultiyData
*
* @brief USART3 send data
*
* @param pbuf - Packet to be sent
* num - Number of data sent
*
* @return none
*/
void UART1_SendData(u8 data)
{
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
USART_SendData(USART1, data);
}
/*********************************************************************
* @fn Uart1_Rx
*
* @brief Uart3 receive date
*
* @return none
*/
u8 Uart1_Rx(void)
{
while( USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == RESET);
return USART_ReceiveData( USART1);
}
/*********************************************************************
* @fn UART_Rx_Deal
*
* @brief UART Rx data deal
*
* @return none
*/
void UART_Rx_Deal(void)
{
u8 i, s;
u8 Data_add = 0;
if (Uart1_Rx() == Uart_Sync_Head1)
{
if (Uart1_Rx() == Uart_Sync_Head2)
{
isp_cmd_t->Cmd = Uart1_Rx();
Data_add += isp_cmd_t->Cmd;
isp_cmd_t->Len = Uart1_Rx();
Data_add += isp_cmd_t->Len;
isp_cmd_t->Rev[0] = Uart1_Rx();
Data_add += isp_cmd_t->Rev[0];
isp_cmd_t->Rev[1] = Uart1_Rx();
Data_add += isp_cmd_t->Rev[1];
if ((isp_cmd_t->Cmd == CMD_IAP_PROM)
|| (isp_cmd_t->Cmd == CMD_IAP_VERIFY))
{
for (i = 0; i < isp_cmd_t->Len; i++) {
isp_cmd_t->data[i] = Uart1_Rx();
Data_add += isp_cmd_t->data[i];
}
}
if (Uart1_Rx() == Data_add)
{
s = RecData_Deal();
if (s != ERR_End)
{
UART1_SendData(0x00);
if (s == ERR_ERROR)
{
UART1_SendData(0x01);
}
else
{
UART1_SendData(0x00);
}
}
}
}
}
}

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code/ch32v003_bootloader/user/iap.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : iap.h
* Author : WCH
* Version : V1.0.0
* Date : 2020/12/16
* Description : IAP
*******************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __IAP_H
#define __IAP_H
#include "ch32v00x.h"
#include "stdio.h"
#define USBD_DATA_SIZE 64
#define BUILD_UINT16(loByte, hiByte) ((UINT16)(((loByte) & 0x00FF) | (((hiByte) & 0x00FF) << 8)))
#define BUILD_UINT32(Byte0, Byte1, Byte2, Byte3) \
((UINT32)((UINT32)((Byte0) & 0x00FF) \
+ ((((UINT32)Byte1) & 0x00FF) << 8) \
+ ((((UINT32)Byte2) & 0x00FF) << 16) \
+ ((((UINT32)Byte3) & 0x00FF) << 24)))
#define Uart_Sync_Head1 0x57
#define Uart_Sync_Head2 0xab
#define CMD_IAP_PROM 0x80
#define CMD_IAP_ERASE 0x81
#define CMD_IAP_VERIFY 0x82
#define CMD_IAP_END 0x83
#define ERR_SCUESS 0x00
#define ERR_ERROR 0x01
#define ERR_End 0x02
typedef struct __attribute__ ((aligned(4)))_ISP_CMD {
u8 Cmd;
u8 Len;
u8 Rev[2];
u8 data[60];
} isp_cmd;
typedef void (*iapfun)(void);
extern u8 EP2_Rx_Buffer[USBD_DATA_SIZE];
u8 RecData_Deal(void);
void GPIO_Cfg_init(void);
void USART1_CFG(u32 baudrate);
void UART_Rx_Deal(void);
u8 btn2_pushed(void);
#endif

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code/ch32v003_bootloader/user/main.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/12/25
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
/*
*@Note
*IAP upgrade routine:
*Support serial port for FLASH burning
*
*1. Use the IAP download tool to realize the download PC0 floating (default pull-up input)
*2. After downloading the APP, connect PC0 to ground (low level input), and press the
*reset button to run the APP program.
*3. use WCH-LinkUtility.exe download to BOOT(adr-0x1FFFF000)
*
*/
#include "debug.h"
#include "string.h"
#include "iap.h"
/*********************************************************************
* @fn IAP_2_APP
*
* @brief IAP_2_APP program.
*
* @return none
*/
void IAP_2_APP(void)
{
RCC_ClearFlag();
SystemReset_StartMode(Start_Mode_USER);
NVIC_SystemReset();
}
/*********************************************************************
* @fn main
*
* @brief Main program.
*
* @return none
*/
int main(void)
{
// Enable GPIOD,USART1, GPIOC clock
RCC->APB2PCENR |= (RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1|RCC_APB2Periph_GPIOC);
USART1_CFG(115200);
if(!btn2_pushed()) {
IAP_2_APP();
while(1);
}
while(1) {
if(USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == RESET) {
UART_Rx_Deal();
}
}
}

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code/ch32v003_bootloader/user/system_ch32v00x.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v00x.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/12/21
* Description : CH32V00x Device Peripheral Access Layer System Source File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x.h>
/*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source).
* If none of the define below is enabled, the HSI is used as System clock source.
*/
//#define SYSCLK_FREQ_8MHz_HSI 8000000
#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE
//#define SYSCLK_FREQ_48MHZ_HSI 48000000
//#define SYSCLK_FREQ_8MHz_HSE 8000000
//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE
//#define SYSCLK_FREQ_48MHz_HSE 48000000
/* Clock Definitions */
#ifdef SYSCLK_FREQ_8MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_24MHZ_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHZ_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHZ_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHZ_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_8MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_24MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
#else
uint32_t SystemCoreClock = HSI_VALUE;
#endif
__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
/* system_private_function_proto_types */
static void SetSysClock(void);
#ifdef SYSCLK_FREQ_8MHz_HSI
static void SetSysClockTo_8MHz_HSI(void);
#elif defined SYSCLK_FREQ_24MHZ_HSI
static void SetSysClockTo_24MHZ_HSI(void);
#elif defined SYSCLK_FREQ_48MHZ_HSI
static void SetSysClockTo_48MHZ_HSI(void);
#elif defined SYSCLK_FREQ_8MHz_HSE
static void SetSysClockTo_8MHz_HSE(void);
#elif defined SYSCLK_FREQ_24MHz_HSE
static void SetSysClockTo_24MHz_HSE(void);
#elif defined SYSCLK_FREQ_48MHz_HSE
static void SetSysClockTo_48MHz_HSE(void);
#endif
/*********************************************************************
* @fn SystemInit
*
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
* the PLL and update the SystemCoreClock variable.
*
* @return none
*/
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFFFEFFFF;
RCC->INTR = 0x009F0000;
RCC_AdjustHSICalibrationValue(0x10);
SetSysClock();
}
/*********************************************************************
* @fn SystemCoreClockUpdate
*
* @brief Update SystemCoreClock variable according to Clock Register Values.
*
* @return none
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllsource = 0;
tmp = RCC->CFGR0 & RCC_SWS;
switch (tmp)
{
case 0x00:
SystemCoreClock = HSI_VALUE;
break;
case 0x04:
SystemCoreClock = HSE_VALUE;
break;
case 0x08:
pllsource = RCC->CFGR0 & RCC_PLLSRC;
if (pllsource == 0x00)
{
SystemCoreClock = HSI_VALUE * 2;
}
else
{
SystemCoreClock = HSE_VALUE * 2;
}
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8)
{
SystemCoreClock /= tmp;
}
else
{
SystemCoreClock >>= tmp;
}
}
/*********************************************************************
* @fn SetSysClock
*
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClock(void)
{
RCC->APB2PCENR |= RCC_APB2Periph_GPIOD;
GPIOD->CFGLR&=(~0xF0);
GPIOD->CFGLR|=0x80;
GPIOD->BSHR =0x2;
//GPIO_IPD_Unused();
#ifdef SYSCLK_FREQ_8MHz_HSI
SetSysClockTo_8MHz_HSI();
#elif defined SYSCLK_FREQ_24MHZ_HSI
SetSysClockTo_24MHZ_HSI();
#elif defined SYSCLK_FREQ_48MHZ_HSI
SetSysClockTo_48MHZ_HSI();
#elif defined SYSCLK_FREQ_8MHz_HSE
SetSysClockTo_8MHz_HSE();
#elif defined SYSCLK_FREQ_24MHz_HSE
SetSysClockTo_24MHz_HSE();
#elif defined SYSCLK_FREQ_48MHz_HSE
SetSysClockTo_48MHz_HSE();
#endif
/* If none of the define above is enabled, the HSI is used as System clock.
* source (default after reset)
*/
}
#ifdef SYSCLK_FREQ_8MHz_HSI
/*********************************************************************
* @fn SetSysClockTo_8MHz_HSI
*
* @brief Sets HSI as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo_8MHz_HSI(void)
{
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
/* HCLK = SYSCLK = APB1 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3;
}
#elif defined SYSCLK_FREQ_24MHZ_HSI
/*********************************************************************
* @fn SetSysClockTo_24MHZ_HSI
*
* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo_24MHZ_HSI(void)
{
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
/* HCLK = SYSCLK = APB1 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
}
#elif defined SYSCLK_FREQ_48MHZ_HSI
/*********************************************************************
* @fn SetSysClockTo_48MHZ_HSI
*
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo_48MHZ_HSI(void)
{
uint8_t tmp = 0;
tmp = *( uint8_t * )CFG0_PLL_TRIM;
if(tmp != 0xFF)
{
RCC_AdjustHSICalibrationValue((tmp & 0x1F));
}
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
/* HCLK = SYSCLK = APB1 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PLL configuration: PLLCLK = HSI * 2 = 48 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Mul2);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_8MHz_HSE
/*********************************************************************
* @fn SetSysClockTo_8MHz_HSE
*
* @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo_8MHz_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Close PA0-PA1 GPIO function */
RCC->APB2PCENR |= RCC_AFIOEN;
AFIO->PCFR1 |= (1<<15);
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
/* HCLK = SYSCLK = APB1 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3;
/* Select HSE as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_24MHz_HSE
/*********************************************************************
* @fn SetSysClockTo_24MHz_HSE
*
* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo_24MHz_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Close PA0-PA1 GPIO function */
RCC->APB2PCENR |= RCC_AFIOEN;
AFIO->PCFR1 |= (1<<15);
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
/* HCLK = SYSCLK = APB1 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* Select HSE as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_48MHz_HSE
/*********************************************************************
* @fn SetSysClockTo_48MHz_HSE
*
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo_48MHz_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Close PA0-PA1 GPIO function */
RCC->APB2PCENR |= RCC_AFIOEN;
AFIO->PCFR1 |= (1<<15);
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
/* HCLK = SYSCLK = APB1 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PLL configuration: PLLCLK = HSE * 2 = 48 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE_Mul2);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#endif

32
code/ch32v003_bootloader/user/system_ch32v00x.h Normal file
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@@ -0,0 +1,32 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v00x.h
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Description : CH32V00x Device Peripheral Access Layer System Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __SYSTEM_CH32V00x_H
#define __SYSTEM_CH32V00x_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
/* System_Exported_Functions */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V00x_SYSTEM_H */