276 lines
10 KiB
ArmAsm
276 lines
10 KiB
ArmAsm
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;/********************************** (C) COPYRIGHT *******************************
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;* File Name : startup_ch32v20x_D8W.s
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;* Author : WCH
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;* Version : V1.0.1
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;* Date : 2023/11/11
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;* Description : CH32V208x
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;* vector table for eclipse toolchain.
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;*********************************************************************************
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;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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;* Attention: This software (modified or not) and binary are used for
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;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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.section .init,"ax",@progbits
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.global _start
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.align 1
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_start:
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j handle_reset
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.section .vector,"ax",@progbits
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.align 1
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_vector_base:
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.option norvc;
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.word _start
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.word 0
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.word NMI_Handler /* NMI */
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.word HardFault_Handler /* Hard Fault */
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.word 0
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.word Ecall_M_Mode_Handler /* Ecall M Mode */
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.word 0
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.word 0
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.word Ecall_U_Mode_Handler /* Ecall U Mode */
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.word Break_Point_Handler /* Break Point */
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.word 0
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.word 0
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.word SysTick_Handler /* SysTick */
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.word 0
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.word SW_Handler /* SW */
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.word 0
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/* External Interrupts */
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.word WWDG_IRQHandler /* Window Watchdog */
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.word PVD_IRQHandler /* PVD through EXTI Line detect */
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.word TAMPER_IRQHandler /* TAMPER */
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.word RTC_IRQHandler /* RTC */
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.word FLASH_IRQHandler /* Flash */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line 0 */
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.word EXTI1_IRQHandler /* EXTI Line 1 */
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.word EXTI2_IRQHandler /* EXTI Line 2 */
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.word EXTI3_IRQHandler /* EXTI Line 3 */
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.word EXTI4_IRQHandler /* EXTI Line 4 */
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.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
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.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
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.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
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.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
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.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
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.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
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.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
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.word ADC1_2_IRQHandler /* ADC1_2 */
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.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
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.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
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.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
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.word CAN1_SCE_IRQHandler /* CAN1 SCE */
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.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
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.word TIM1_BRK_IRQHandler /* TIM1 Break */
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.word TIM1_UP_IRQHandler /* TIM1 Update */
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.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM4_IRQHandler /* TIM4 */
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.word I2C1_EV_IRQHandler /* I2C1 Event */
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.word I2C1_ER_IRQHandler /* I2C1 Error */
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.word I2C2_EV_IRQHandler /* I2C2 Event */
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.word I2C2_ER_IRQHandler /* I2C2 Error */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word USART3_IRQHandler /* USART3 */
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.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
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.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
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.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
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.word USBFS_IRQHandler /* USBFS Break */
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.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
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.word ETH_IRQHandler /* ETH global */
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.word ETHWakeUp_IRQHandler /* ETH Wake up */
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.word BB_IRQHandler /* BLE BB */
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.word LLE_IRQHandler /* BLE LLE */
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.word TIM5_IRQHandler /* TIM5 */
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.word UART4_IRQHandler /* UART4 */
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.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
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.word OSC32KCal_IRQHandler /* OSC32KCal */
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.word OSCWakeUp_IRQHandler /* OSC Wake Up */
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.option rvc;
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.section .text.vector_handler, "ax", @progbits
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.weak NMI_Handler /* NMI */
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.weak HardFault_Handler /* Hard Fault */
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.weak Ecall_M_Mode_Handler /* Ecall M Mode */
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.weak Ecall_U_Mode_Handler /* Ecall U Mode */
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.weak Break_Point_Handler /* Break Point */
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.weak SysTick_Handler /* SysTick */
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.weak SW_Handler /* SW */
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.weak WWDG_IRQHandler /* Window Watchdog */
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.weak PVD_IRQHandler /* PVD through EXTI Line detect */
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.weak TAMPER_IRQHandler /* TAMPER */
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.weak RTC_IRQHandler /* RTC */
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.weak FLASH_IRQHandler /* Flash */
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.weak RCC_IRQHandler /* RCC */
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.weak EXTI0_IRQHandler /* EXTI Line 0 */
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.weak EXTI1_IRQHandler /* EXTI Line 1 */
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.weak EXTI2_IRQHandler /* EXTI Line 2 */
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.weak EXTI3_IRQHandler /* EXTI Line 3 */
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.weak EXTI4_IRQHandler /* EXTI Line 4 */
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.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
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.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
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.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
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.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
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.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
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.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
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.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
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.weak ADC1_2_IRQHandler /* ADC1_2 */
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.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
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.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
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.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
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.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
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.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
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.weak TIM1_BRK_IRQHandler /* TIM1 Break */
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.weak TIM1_UP_IRQHandler /* TIM1 Update */
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.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
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.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.weak TIM2_IRQHandler /* TIM2 */
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.weak TIM3_IRQHandler /* TIM3 */
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.weak TIM4_IRQHandler /* TIM4 */
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.weak I2C1_EV_IRQHandler /* I2C1 Event */
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.weak I2C1_ER_IRQHandler /* I2C1 Error */
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.weak I2C2_EV_IRQHandler /* I2C2 Event */
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.weak I2C2_ER_IRQHandler /* I2C2 Error */
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.weak SPI1_IRQHandler /* SPI1 */
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.weak SPI2_IRQHandler /* SPI2 */
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.weak USART1_IRQHandler /* USART1 */
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.weak USART2_IRQHandler /* USART2 */
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.weak USART3_IRQHandler /* USART3 */
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.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
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.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
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.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
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.weak USBFS_IRQHandler /* USBFS */
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.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
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.weak ETH_IRQHandler /* ETH global */
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.weak ETHWakeUp_IRQHandler /* ETHWakeUp */
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.weak BB_IRQHandler /* BLE BB */
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.weak LLE_IRQHandler /* BLE LLE */
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.weak TIM5_IRQHandler /* TIM5 */
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.weak UART4_IRQHandler /* UART4 */
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.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
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.weak OSC32KCal_IRQHandler /* OSC32 KCal */
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.weak OSCWakeUp_IRQHandler /* OSC Wake Up */
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NMI_Handler:
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HardFault_Handler:
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Ecall_M_Mode_Handler:
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Ecall_U_Mode_Handler:
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Break_Point_Handler:
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SysTick_Handler:
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SW_Handler:
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WWDG_IRQHandler:
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PVD_IRQHandler:
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TAMPER_IRQHandler:
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RTC_IRQHandler:
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FLASH_IRQHandler:
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RCC_IRQHandler:
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EXTI0_IRQHandler:
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EXTI1_IRQHandler:
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EXTI2_IRQHandler:
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EXTI3_IRQHandler:
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EXTI4_IRQHandler:
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DMA1_Channel1_IRQHandler:
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DMA1_Channel2_IRQHandler:
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DMA1_Channel3_IRQHandler:
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DMA1_Channel4_IRQHandler:
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DMA1_Channel5_IRQHandler:
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DMA1_Channel6_IRQHandler:
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DMA1_Channel7_IRQHandler:
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ADC1_2_IRQHandler:
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USB_HP_CAN1_TX_IRQHandler:
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USB_LP_CAN1_RX0_IRQHandler:
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CAN1_RX1_IRQHandler:
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CAN1_SCE_IRQHandler:
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EXTI9_5_IRQHandler:
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TIM1_BRK_IRQHandler:
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TIM1_UP_IRQHandler:
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TIM1_TRG_COM_IRQHandler:
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TIM1_CC_IRQHandler:
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TIM2_IRQHandler:
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TIM3_IRQHandler:
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TIM4_IRQHandler:
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I2C1_EV_IRQHandler:
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I2C1_ER_IRQHandler:
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I2C2_EV_IRQHandler:
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I2C2_ER_IRQHandler:
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SPI1_IRQHandler:
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SPI2_IRQHandler:
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USART1_IRQHandler:
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USART2_IRQHandler:
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USART3_IRQHandler:
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EXTI15_10_IRQHandler:
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RTCAlarm_IRQHandler:
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USBWakeUp_IRQHandler:
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USBFS_IRQHandler:
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USBFSWakeUp_IRQHandler:
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ETH_IRQHandler:
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ETHWakeUp_IRQHandler:
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BB_IRQHandler:
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LLE_IRQHandler:
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TIM5_IRQHandler:
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UART4_IRQHandler:
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DMA1_Channel8_IRQHandler:
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OSC32KCal_IRQHandler:
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OSCWakeUp_IRQHandler:
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1:
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j 1b
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.section .text.handle_reset,"ax",@progbits
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.weak handle_reset
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.align 1
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handle_reset:
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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1:
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la sp, _eusrstack
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2:
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/* Load data section from flash to RAM */
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la a0, _data_lma
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la a1, _data_vma
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* Clear bss section */
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la a0, _sbss
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la a1, _ebss
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/* Configure pipelining and instruction prediction */
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li t0, 0x1f
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csrw 0xbc0, t0
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/* Enable interrupt nesting and hardware stack */
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li t0, 0x3
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csrw 0x804, t0
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/* Enable global interrupt and configure privileged mode */
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li t0, 0x88
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csrw mstatus, t0
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/* Configure the interrupt vector table recognition mode and entry address mode */
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la t0, _vector_base
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ori t0, t0, 3
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csrw mtvec, t0
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jal SystemInit
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la t0, main
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csrw mepc, t0
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mret
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