Initial bootloader implementation
Took a publicly available XMODEM bootloader and made it work on HK32F. Known issues: - Erase is super slow on this MCU. The upload routine erases all flash before loading, which means the first packet seems to hang. This also erases possibly persistent data stored in unused pages on flash.
This commit is contained in:
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,37 @@
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/**
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******************************************************************************
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* @file system_hk32f030m.h
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* @author Rakan.Z/laura.C
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* @version V1.0
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* @brief API file of system clk config
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* @changelist
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******************************************************************************
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*/
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#ifndef __SYSTEM_HK32F030M_H
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#define __SYSTEM_HK32F030M_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** hk32f030m_System_Exported_types */
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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extern const uint16_t AHBPrescTable[16]; /*!< AHB prescalers table values */
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extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
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extern void SystemInit(void);
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extern void SystemCoreClockUpdate(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__SYSTEM_HK32F030M_H */
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@@ -0,0 +1,246 @@
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/**
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******************************************************************************
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* @file startup_hk32f030mf4p6.s
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* @brief HK32F030MF4P6 devices vector table for GCC toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually calls main()).
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* After Reset the Cortex-M0 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m0
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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ldr r0, =_sdata
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ldr r1, =_edata
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ldr r2, =_sidata
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movs r3, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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LoopCopyDataInit:
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adds r4, r0, r3
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cmp r4, r1
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bcc CopyDataInit
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/* Zero fill the bss segment. */
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ldr r2, =_sbss
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ldr r4, =_ebss
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movs r3, #0
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b LoopFillZerobss
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FillZerobss:
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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cmp r2, r4
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bcc FillZerobss
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SystemStartup:
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors. Remove this line if compile with `-nostartfiles` reports error */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M0. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word 0
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler /* Window WatchDog */
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.word 0 /* Reserved */
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.word EXTI11_IRQHandler /* EXTI Line 11 interrupt(AWU_WKP) */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line 0 */
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.word EXTI1_IRQHandler /* EXTI Line 1 */
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.word EXTI2_IRQHandler /* EXTI Line 2 */
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.word EXTI3_IRQHandler /* EXTI Line 3 */
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.word EXTI4_IRQHandler /* EXTI Line 4 */
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.word EXTI5_IRQHandler /* EXTI Line 5 */
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.word TIM1_BRK_IRQHandler /* TIM1 break interrupt */
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.word ADC1_IRQHandler /* ADC1 interrupt, combined with EXTI line 8 */
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.word TIM1_UP_TRG_COM_IRQHandler /* TIM1 Update, Trigger and Commutation */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word 0 /* Reserved */
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.word TIM6_IRQHandler /* TIM6 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word EXTI6_IRQHandler /* EXTI Line 6 */
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.word EXTI7_IRQHandler /* EXTI Line 7 */
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.word I2C1_IRQHandler /* I2C1 global interrupt, combined with EXTI Line 10 */
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.word 0 /* Reserved */
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.word SPI1_IRQHandler /* SPI1 */
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.word 0 /* Reserved */
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.word USART1_IRQHandler /* USART1 global interrupt, combined with EXTI Line 9 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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.weak EXTI11_IRQHandler
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.thumb_set EXTI11_IRQHandler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_IRQHandler
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.thumb_set RCC_IRQHandler,Default_Handler
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.weak EXTI0_IRQHandler
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.thumb_set EXTI0_IRQHandler,Default_Handler
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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.weak EXTI2_IRQHandler
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.thumb_set EXTI2_IRQHandler,Default_Handler
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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.weak EXTI4_IRQHandler
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.thumb_set EXTI4_IRQHandler,Default_Handler
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.weak EXTI5_IRQHandler
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.thumb_set EXTI5_IRQHandler,Default_Handler
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.weak TIM1_BRK_IRQHandler
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.thumb_set TIM1_BRK_IRQHandler,Default_Handler
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.weak ADC1_IRQHandler
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.thumb_set ADC1_IRQHandler,Default_Handler
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.weak TIM1_UP_TRG_COM_IRQHandler
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.thumb_set TIM1_UP_TRG_COM_IRQHandler,Default_Handler
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler,Default_Handler
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.weak TIM2_IRQHandler
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.thumb_set TIM2_IRQHandler,Default_Handler
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.weak TIM6_IRQHandler
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.thumb_set TIM6_IRQHandler,Default_Handler
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.weak EXTI6_IRQHandler
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.thumb_set EXTI6_IRQHandler,Default_Handler
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.weak EXTI7_IRQHandler
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.thumb_set EXTI7_IRQHandler,Default_Handler
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.weak I2C1_IRQHandler
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.thumb_set I2C1_IRQHandler,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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.weak USART1_IRQHandler
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.thumb_set USART1_IRQHandler,Default_Handler
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@@ -0,0 +1,418 @@
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/**
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******************************************************************************
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* @file system_hk32f030m.c
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* @author laura.C
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* @version V1.0
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* @brief API file of system clk config
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* @changelist
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******************************************************************************
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*/
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/*
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This file configures the system clock as follows:
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*=============================================================================
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* Supported hk32f030m device
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*-----------------------------------------------------------------------------
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* System Clock source | HSI32M
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 32000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 32000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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*/
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#include "hk32f030m.h"
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/* system clock source */
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#define SYSCLK_SRC_HSI8M 0x2
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#define SYSCLK_SRC_HSI16M 0x3
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#define SYSCLK_SRC_HSI32M 0x4
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#define SYSCLK_SRC_LSI 0x5
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#define SYSCLK_SCR_EXTCLK_IO 0x6
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#define SYSCLK_SOURCE SYSCLK_SRC_HSI8M
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/* vector table location */
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// #define VECT_TAB_SRAM
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#ifndef VECT_TAB_OFFSET
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#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
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#endif
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uint32_t System_SysClk; // SYSCLK which feeds AHB, ADC, USART, etc. System clock.
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uint32_t System_HClk; // HCLK which feeds core, AHB bus, memory. CPU clock.
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#if(SYSCLK_SOURCE==SYSCLK_SRC_HSI8M)
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#define SYSCLK_FREQ_HSI 32000000
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#define HCLK_FREQ 8000000
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#define SET_FLASH_LATENCY FLASH_Latency_0
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#define SET_HPRE_DIV RCC_CFGR_HPRE_DIV4
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static void SetSysClockToHSI(void);
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI16M)
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#define SYSCLK_FREQ_HSI 32000000
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#define HCLK_FREQ 16000000
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#define SET_FLASH_LATENCY FLASH_Latency_0
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#define SET_HPRE_DIV RCC_CFGR_HPRE_DIV2
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static void SetSysClockToHSI(void);
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI32M)
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#define SYSCLK_FREQ_HSI 32000000
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#define HCLK_FREQ 32000000
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#define SET_FLASH_LATENCY FLASH_Latency_1
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#define SET_HPRE_DIV RCC_CFGR_HPRE_DIV1
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static void SetSysClockToHSI(void);
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_LSI)
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#define SYSCLK_FREQ_LSI LSI_VALUE
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uint32_t SystemCoreClock = SYSCLK_FREQ_LSI;
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static void SetSysClockToLSI(void);
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#elif(SYSCLK_SOURCE == SYSCLK_SCR_EXTCLK_IO)
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#define SYSCLK_FREQ_EXTCLK EXTCLK_VALUE
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uint32_t SystemCoreClock = SYSCLK_FREQ_EXTCLK;
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static void SetSysClockToEXTCLK(void);
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#endif
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static void SetSysClock(void);
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/**
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* @brief Setup the microcontroller system.
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* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FFB81C;
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/* Reset USARTSW[1:0], I2CSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFFEC;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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SetSysClock();
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#ifdef VECT_TAB_SRAM
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SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE; /* Vector Table Relocation in Internal SRAM. */
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#else
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FLASH->INT_VEC_OFFSET = VECT_TAB_OFFSET ; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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* @brief Configures the System clock frequency, HCLK, PCLK prescalers.
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* @param None
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* @retval None
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*/
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static void SetSysClock(void)
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{
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/*reload the hsi trimming value to the bit3~bit13 of RCC_CR register */
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uint32_t u32HSIFLASH = 0;
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uint32_t u32RCC_CR = 0;
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uint32_t u32HSITemp = 0;
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uint16_t u16HSITempH = 0;
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uint16_t u16HSITempL = 0;
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u32HSIFLASH = *(uint32_t *) 0x1FFFF820;
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u16HSITempH = (uint16_t)(u32HSIFLASH>>16);
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u16HSITempL = (uint16_t)(u32HSIFLASH);
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if(!(u16HSITempH & u16HSITempL))
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{
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u32HSITemp = RCC->CR;
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u32HSITemp &= (uint32_t)((uint32_t)~(RCC_CR_HSITRIM|RCC_CR_HSICAL));
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u32RCC_CR = (uint32_t)(((u16HSITempL & 0x001F) <<3) | (((u16HSITempL>>5) & 0x003F)<<8));
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RCC->CR |= u32RCC_CR;
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}
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/*end*/
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#if(SYSCLK_SOURCE==SYSCLK_SRC_HSI8M)
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SetSysClockToHSI();
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI16M)
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SetSysClockToHSI();
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI32M)
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SetSysClockToHSI();
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_LSI)
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SetSysClockToLSI();
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#elif(SYSCLK_SOURCE == SYSCLK_SCR_EXTCLK_IO)
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SetSysClockToEXTCLK();
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#endif
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/* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */
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}
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#ifdef SYSCLK_FREQ_HSI
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static void SetSysClockToHSI(void)
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{
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__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
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__IO uint32_t ACRreg = 0;
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__IO uint32_t RCCHCLKReg = 0;
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__IO uint32_t RCCPCLKReg = 0;
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/* Enable HSI */
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RCC->CR |= RCC_CR_HSION;
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/* Set flash programming clock to 2MHz using HSI32M directly
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* Datasheet and RM was updated in 2023 which derated flash programming from 4MHz
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* 0x07 = 4MHz, 0x08 = 2MHz. change as you see fit */
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RCC->CFGR4 &= ~(RCC_RCC_CFGR4_FLITFCLK_PRE | RCC_RCC_CFGR4_FLITFCLK_SE);
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RCC->CFGR4 |= (((uint32_t)0x07) << RCC_RCC_CFGR4_FLITFCLK_PRE_Pos);
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/* Wait until HSI is ready; if timeout is reached, then exit */
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do {
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HSIStatus = RCC->CR & RCC_CR_HSIRDY;
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StartUpCounter++;
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} while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_HSIRDY) != RESET) {
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HSIStatus = (uint32_t)0x01;
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} else {
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HSIStatus = (uint32_t)0x00;
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}
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if (HSIStatus == (uint32_t)0x01) {
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/* Flash wait state */
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ACRreg = FLASH->ACR;
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ACRreg &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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FLASH->ACR = (uint32_t)(SET_FLASH_LATENCY | ACRreg);
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||||
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/* HCLK = configured divided value from SYSCLK (which will later be set to HSI32M) */
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RCCHCLKReg = RCC->CFGR;
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||||
RCCHCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_HPRE_Msk);
|
||||
RCC->CFGR = (uint32_t)(SET_HPRE_DIV | RCCHCLKReg);
|
||||
|
||||
/* PCLK = HCLK */
|
||||
RCCPCLKReg = RCC->CFGR;
|
||||
RCCPCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_PPRE_Msk);
|
||||
RCC->CFGR = (uint32_t)(RCC_CFGR_PPRE_DIV1|RCCPCLKReg);
|
||||
|
||||
/* Select HSI32M as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
|
||||
|
||||
/* Wait until HSI is active as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);
|
||||
} else {
|
||||
/* If clock fails to start, the application will have wrong clock configuration.
|
||||
* User can add some code here to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif (SYSCLK_SOURCE == SYSCLK_SRC_LSI)
|
||||
static void SetSysClockToLSI(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, LSIStatus = 0;
|
||||
|
||||
/* Enable LSI */
|
||||
RCC->CSR |= RCC_CSR_LSION;
|
||||
|
||||
/* Wait till LSI is ready and if Time out is reached exit */
|
||||
do{
|
||||
LSIStatus = RCC->CSR & RCC_CSR_LSIRDY;
|
||||
StartUpCounter++;
|
||||
} while((LSIStatus == 0) && (StartUpCounter != STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CSR & RCC_CSR_LSIRDY) != RESET)
|
||||
{
|
||||
LSIStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
LSIStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (LSIStatus == (uint32_t)0x01)
|
||||
{
|
||||
|
||||
/* Flash wait state */
|
||||
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
||||
FLASH->ACR |= (uint32_t)FLASH_Latency_0;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK = HCLK */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
|
||||
|
||||
/* Select HSI as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_LSI;
|
||||
|
||||
/* Wait till LSI is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_LSI)
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{ /* If fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
};
|
||||
|
||||
#elif (SYSCLK_SOURCE == SYSCLK_SCR_EXTCLK_IO)
|
||||
static void SetSysClockToEXTCLK(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, EXTCLKStatus = 0;
|
||||
__IO uint32_t ACRreg = 0;
|
||||
__IO uint32_t RCCHCLKReg = 0;
|
||||
__IO uint32_t RCCPCLKReg = 0;
|
||||
//enable EXTIO PA1/PD7/PB5/PC5
|
||||
|
||||
/* Configure PA1 as CLOCK input */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
|
||||
// RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
|
||||
// GPIO_InitTypeDef GPIO_InitStructure;
|
||||
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
|
||||
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
|
||||
// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
// GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
|
||||
|
||||
// RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
|
||||
// GPIO_InitTypeDef GPIO_InitStructure;
|
||||
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
|
||||
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
|
||||
// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
// GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
// RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
|
||||
// GPIO_InitTypeDef GPIO_InitStructure;
|
||||
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
|
||||
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
|
||||
// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
// GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
/*CLOCK select */
|
||||
RCC->CFGR4 &= (uint32_t)~(RCC_RCC_CFGR4_EXTCLK_SEL);
|
||||
RCC->CFGR4 |= (uint32_t)RCC_CFGR4_EXTCLK_SEL_PA1;
|
||||
// RCC->CFGR4 |= (uint32_t)RCC_CFGR4_EXTCLK_SEL_PB5;
|
||||
// RCC->CFGR4 |= (uint32_t)RCC_CFGR4_EXTCLK_SEL_PC5;
|
||||
// RCC->CFGR4 |= (uint32_t)RCC_CFGR4_EXTCLK_SEL_PD7;
|
||||
/* Enable EXTCLK */
|
||||
RCC->CR |= RCC_CR_EXTCLKON;
|
||||
|
||||
/* Wait till LSI is ready and if Time out is reached exit */
|
||||
do{
|
||||
EXTCLKStatus = RCC->CR & RCC_CR_EXTCLKRDY;
|
||||
StartUpCounter++;
|
||||
} while((EXTCLKStatus == 0) && (StartUpCounter != STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_EXTCLKRDY) != RESET)
|
||||
{
|
||||
EXTCLKStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTCLKStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (EXTCLKStatus == (uint32_t)0x01)
|
||||
{
|
||||
|
||||
/* Flash wait state */
|
||||
ACRreg= FLASH->ACR;
|
||||
ACRreg &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
||||
|
||||
if (SystemCoreClock <= 16000000)
|
||||
FLASH->ACR = (uint32_t)(FLASH_Latency_0|ACRreg);
|
||||
else if(SystemCoreClock <= 32000000)
|
||||
FLASH->ACR = (uint32_t)(FLASH_Latency_1|ACRreg);
|
||||
else
|
||||
FLASH->ACR = (uint32_t)(FLASH_Latency_2|ACRreg);
|
||||
|
||||
|
||||
RCCHCLKReg = RCC->CFGR;
|
||||
RCCHCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_HPRE_Msk);
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR = (uint32_t)(RCC_CFGR_HPRE_DIV1|RCCHCLKReg);
|
||||
|
||||
RCCPCLKReg = RCC->CFGR;
|
||||
RCCPCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_PPRE_Msk);
|
||||
/* PCLK = HCLK */
|
||||
RCC->CFGR = (uint32_t)(RCC_CFGR_PPRE_DIV1|RCCPCLKReg);
|
||||
|
||||
|
||||
/* Select EXTCLK as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_EXTCLK;
|
||||
|
||||
/* Wait till EXTCLK is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_EXTCLK)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, presc = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
|
||||
SystemCoreClock = HCLK_FREQ;
|
||||
break;
|
||||
case RCC_CFGR_SWS_EXTCLK: /* EXTCLK used as system clock */
|
||||
SystemCoreClock = EXTCLK_VALUE;
|
||||
break;
|
||||
case RCC_CFGR_SWS_LSI: /* LSI used as system clock */
|
||||
SystemCoreClock = LSI_VALUE;
|
||||
break;
|
||||
|
||||
default: /* HSI used as system clock */
|
||||
SystemCoreClock = HCLK_FREQ;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = RCC->CFGR & RCC_CFGR_HPRE;
|
||||
tmp = tmp >> 4;
|
||||
presc = AHBPrescTable[tmp];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock = SystemCoreClock/presc;
|
||||
}
|
||||
Reference in New Issue
Block a user