main firmware: WIP
very rough WIP of main badge code. some LED programs are here, and it will build if the btn code is excluded.
This commit is contained in:
true
359
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_adc.h
Normal file
359
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_adc.h
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@@ -0,0 +1,359 @@
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/**
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******************************************************************************
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* @file hk32f030m_adc.h
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* @version V1.0.0
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* @date 2019-08-05
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* @author Rakan.Z/Jane.li
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __HK32F030M_ADC_H
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#define __HK32F030M_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "hk32f030m.h"
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/** @addtogroup ADC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief ADC Init structure definition
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*/
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typedef struct
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{
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FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
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Continuous or Single mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
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trigger of a regular group. This parameter can be a value
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of @ref ADC_external_trigger_edge_conversion */
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uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
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to digital conversion of regular channels. This parameter
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can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */
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uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
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This parameter can be a value of @ref ADC_data_align */
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uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned
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in the sequence.
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This parameter can be a value of @ref ADC_Scan_Direction */
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}ADC_InitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup ADC_Exported_Constants
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* @{
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*/
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#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
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/** @defgroup ADC_JitterOff
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* @{
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*/
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/* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */
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#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2
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#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4
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#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)
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/**
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* @}
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*/
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/** @defgroup ADC_ClockMode
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* @{
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*/
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#define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
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#define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */
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#define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */
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#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\
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((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\
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((CLOCK) == ADC_ClockMode_SynClkDiv4))
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/**
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* @}
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*/
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/** @defgroup ADC_external_trigger_edge_conversion
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* @{
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*/
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#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
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#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0
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#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1
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#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN
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#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
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((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
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((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
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((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
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/**
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* @}
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*/
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/** @defgroup ADC_external_trigger_sources_for_channels_conversion
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* @{
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*/
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/* TIM1 */
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#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) //0
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#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0 //1
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#define ADC_ExternalTrigConv_T1_CC1 ADC_CFGR1_EXTSEL_2 //4
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#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0) //5
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#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1) //6
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/* TIM2 */
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#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1 //2
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/* TIM6 */
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#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1)) //3
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/* IO Trig */
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#define ADC_ExternalTrigConv_IO_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1)| ADC_CFGR1_EXTSEL_2) //7
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#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \
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((CONV) == ADC_ExternalTrigConv_T1_CC4) || \
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((CONV) == ADC_ExternalTrigConv_T1_CC1) || \
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((CONV) == ADC_ExternalTrigConv_T1_CC2) || \
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((CONV) == ADC_ExternalTrigConv_T1_CC3) || \
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((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \
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((CONV) == ADC_ExternalTrigConv_T6_TRGO) || \
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((CONV) == ADC_ExternalTrigConv_IO_TRGO))
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/**
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* @}
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*/
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/** @defgroup ADC_data_align
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* @{
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*/
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#define ADC_DataAlign_Right ((uint32_t)0x00000000)
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#define ADC_DataAlign_Left ADC_CFGR1_ALIGN
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#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
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((ALIGN) == ADC_DataAlign_Left))
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/**
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* @}
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*/
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/** @defgroup ADC_Scan_Direction
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* @{
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*/
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#define ADC_ScanDirection_Upward ((uint32_t)0x00000000)
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#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR
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#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \
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((DIRECTION) == ADC_ScanDirection_Backward))
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/**
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* @}
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*/
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/** @defgroup ADC_analog_watchdog_selection
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* @{
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*/
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#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000)
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#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000)
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#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000)
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#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000)
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#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000)
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#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000)
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#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \
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((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \
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((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \
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((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \
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((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \
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((CHANNEL) == ADC_AnalogWatchdog_Channel_5))
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/**
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* @}
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*/
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/** @defgroup ADC_sampling_times
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* @{
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*/
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#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000)
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#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001)
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#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002)
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#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003)
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#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004)
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#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005)
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#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006)
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#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007)
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#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \
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((TIME) == ADC_SampleTime_7_5Cycles) || \
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((TIME) == ADC_SampleTime_13_5Cycles) || \
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((TIME) == ADC_SampleTime_28_5Cycles) || \
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((TIME) == ADC_SampleTime_41_5Cycles) || \
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((TIME) == ADC_SampleTime_55_5Cycles) || \
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((TIME) == ADC_SampleTime_71_5Cycles) || \
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((TIME) == ADC_SampleTime_239_5Cycles))
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/**
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* @}
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*/
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/** @defgroup ADC_thresholds
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* @{
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*/
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#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
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/**
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* @}
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*/
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/** @defgroup ADC_channels
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* @{
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*/
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#define ADC_Channel_0 ADC_CHSELR_CHSEL0
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#define ADC_Channel_1 ADC_CHSELR_CHSEL1
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#define ADC_Channel_2 ADC_CHSELR_CHSEL2
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#define ADC_Channel_3 ADC_CHSELR_CHSEL3
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#define ADC_Channel_4 ADC_CHSELR_CHSEL4
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#define ADC_Channel_5 ADC_CHSELR_CHSEL5
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#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_5)
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#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFFFFFC0) == (uint32_t)RESET))
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/**
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* @}
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*/
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/** @defgroup ADC_interrupts_definition
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* @{
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*/
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#define ADC_IT_ADRDY ADC_IER_ADRDYIE
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#define ADC_IT_EOSMP ADC_IER_EOSMPIE
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#define ADC_IT_EOC ADC_IER_EOCIE
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#define ADC_IT_EOSEQ ADC_IER_EOSEQIE
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#define ADC_IT_OVR ADC_IER_OVRIE
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#define ADC_IT_AWD ADC_IER_AWDIE
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#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
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#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \
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((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \
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((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD))
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#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
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/**
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* @}
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*/
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/** @defgroup ADC_flags_definition
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* @{
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*/
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#define ADC_FLAG_ADRDY ADC_ISR_ADRDY
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#define ADC_FLAG_EOSMP ADC_ISR_EOSMP
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#define ADC_FLAG_EOC ADC_ISR_EOC
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#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ
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#define ADC_FLAG_OVR ADC_ISR_OVR
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#define ADC_FLAG_AWD ADC_ISR_AWD
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#define ADC_FLAG_ADEN ((uint32_t)0x01000001)
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#define ADC_FLAG_ADDIS ((uint32_t)0x01000002)
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#define ADC_FLAG_ADSTART ((uint32_t)0x01000004)
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#define ADC_FLAG_ADSTP ((uint32_t)0x01000010)
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#define ADC_FLAG_ADCAL ((uint32_t)0x81000000)
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#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET))
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#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
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((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \
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((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \
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((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \
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((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \
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((FLAG) == ADC_FLAG_ADCAL))
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||||
|
||||
|
||||
/**
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||||
* @}
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||||
*/
|
||||
|
||||
/**
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||||
* @}
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||||
*/
|
||||
|
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/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
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||||
void ADC_DeInit(ADC_TypeDef* ADCx);
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||||
|
||||
/* Initialization and Configuration functions *********************************/
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void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
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||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
/* This Function is obsolete and maintained for legacy purpose only.
|
||||
ADC_ClockModeConfig() function should be used instead */
|
||||
void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);
|
||||
|
||||
/* Power saving functions *****************************************************/
|
||||
void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);
|
||||
void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Temperature Sensor , Vrefint and Vbat management function ******************/
|
||||
void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Channels Configuration functions *******************************************/
|
||||
void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);
|
||||
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);
|
||||
void ADC_StopOfConversion(ADC_TypeDef* ADCx);
|
||||
void ADC_StartOfConversion(ADC_TypeDef* ADCx);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
|
||||
void ADC_AWDWakeup_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_Diff_Func(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InterDelay_Func(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__HK32F030M_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
59
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_awu.h
Normal file
59
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_awu.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_awu.h
|
||||
* @author Rakan.zhang
|
||||
* @version V1.0
|
||||
* @brief This file contains all functions prototype and macros for the AWU peripheral.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_AWU_H
|
||||
#define __HK32F030M_AWU_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup AWU_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define AWU_CR_RESET_VALUE 0x00000000U
|
||||
#define AWU_SR_RESET_VALUE 0x00000000U
|
||||
#define AWU_SR_BUSY 0x00000001U
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AWU_CLK_LSI128,
|
||||
AWU_CLK_HSE,
|
||||
}AWU_CLK_TYPE;
|
||||
|
||||
#define IS_AWU_CLK(AWU_CLK) \
|
||||
(((AWU_CLK) == AWU_CLK_LSI128) || \
|
||||
((AWU_CLK) == AWU_CLK_HSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/** @addtogroup AWU_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void AWU_DeInit(void);
|
||||
void AWU_CLKConfig(AWU_CLK_TYPE eAWU_CLK);
|
||||
ErrorStatus AWU_TimerCounterAndStart(uint32_t TimerCounter);
|
||||
FlagStatus AWU_GetFlagStatus(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __HK32F030M_AWU_H */
|
||||
|
||||
74
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_beep.h
Normal file
74
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_beep.h
Normal file
@@ -0,0 +1,74 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_beep.h
|
||||
* @author Rakan.Z/Wing.W
|
||||
* @version V1.0
|
||||
* @brief This file contains all functions prototype and macros for the BEEP peripheral.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __HK32F030M_BEEP_H
|
||||
#define __HK32F030M_BEEP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "hk32f030m.h"
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t BEEP_Prescaler;
|
||||
uint8_t BEEP_Clock;
|
||||
uint8_t BEEP_TRGOPrescaler;
|
||||
FunctionalState BEEP_TRGOCmd;
|
||||
}BEEP_InitTypeDef;
|
||||
|
||||
#define BEEP_BUSY_FLAG ((uint32_t)0x80000000U)
|
||||
#define BEEP_CFGR_Value ((uint32_t)0x0000000AU)
|
||||
#define BEEP_CR_Value ((uint32_t)0x00000003U)
|
||||
#define BEEP_CR_BEEP_Mask ((uint32_t)0xFFFFFFF9U)
|
||||
#define BEEP_CR_TRGO_Mask ((uint32_t)0xFFFFFFE7U)
|
||||
|
||||
#define BEEP_Prescaler_16 ((uint32_t)0x00000006U)
|
||||
#define BEEP_Prescaler_32 ((uint32_t)0x00000004U)
|
||||
#define BEEP_Prescaler_64 ((uint32_t)0x00000002U)
|
||||
#define BEEP_Prescaler_128 ((uint32_t)0x00000000U)
|
||||
#define IS_BEEP_PRESCALER(PRESCALER) (((PRESCALER)==BEEP_Prescaler_16) ||\
|
||||
((PRESCALER)==BEEP_Prescaler_32) ||\
|
||||
((PRESCALER)==BEEP_Prescaler_64) ||\
|
||||
((PRESCALER)==BEEP_Prescaler_128))
|
||||
|
||||
|
||||
#define BEEP_CLOCK_HSE ((uint32_t)0x00000001U)
|
||||
#define BEEP_CLOCK_LSI ((uint32_t)0x00000000U)
|
||||
|
||||
#define IS_BEEP_CLOCK(CLOCK) ((CLOCK==(BEEP_CLOCK_HSE))||\
|
||||
CLOCK==(BEEP_CLOCK_LSI))
|
||||
|
||||
|
||||
#define BEEP_TRGO_Prescaler_32 ((uint32_t)0x00000010U)
|
||||
#define BEEP_TRGO_Prescaler_64 ((uint32_t)0x00000008U)
|
||||
#define BEEP_TRGO_Prescaler_128 ((uint32_t)0x00000000U)
|
||||
#define IS_BEEP_TRGO_PRESCALER(PRESCALER) (((PRESCALER)==BEEP_TRGO_Prescaler_32) ||\
|
||||
((PRESCALER)==BEEP_TRGO_Prescaler_64) ||\
|
||||
((PRESCALER)==BEEP_TRGO_Prescaler_128))
|
||||
|
||||
|
||||
|
||||
void BEEP_DeInit(void);
|
||||
void BEEP_Init(BEEP_InitTypeDef * BEEP_InitStruct);
|
||||
void BEEP_Cmd(FunctionalState NewState);
|
||||
void BEEP_ClockSelect(uint8_t BEEP_CLOCK);
|
||||
void BEEP_SetPrescaler(uint8_t BEEP_Prescaler);
|
||||
void BEEP_SetTRGOPrescaler(uint8_t BEEP_TGRO_Prescaler);
|
||||
FlagStatus BEEP_ReadBeepStatus(void);
|
||||
void BEEP_TRGOCmd(FunctionalState NewState);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,135 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_conf_Template.h
|
||||
* @brief hk32f030m configuration file of backup.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
* Users can refer to this file for custom configuration
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_CONF_H
|
||||
#define __HK32F030M_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
|
||||
|
||||
#define EXTCLK_VALUE ((uint32_t)32000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
|
||||
#define HSI_VALUE ((uint32_t)32000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
|
||||
* Timeout value
|
||||
*/
|
||||
|
||||
#define STARTUP_TIMEOUT ((uint32_t)0xFFFF) /*!< Time out for start up */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
|
||||
#define LSI_VALUE ((uint32_t)114000)
|
||||
/*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#include "hk32f030m_rcc.h"
|
||||
|
||||
#include "hk32f030m_crc.h"
|
||||
|
||||
#include "hk32f030m_exti.h"
|
||||
|
||||
#include "hk32f030m_flash.h"
|
||||
|
||||
#include "hk32f030m_gpio.h"
|
||||
|
||||
#include "hk32f030m_misc.h"
|
||||
|
||||
#include "hk32f030m_adc.h"
|
||||
|
||||
#include "hk32f030m_syscfg.h"
|
||||
|
||||
#include "hk32f030m_def.h"
|
||||
|
||||
#include "hk32f030m_i2c.h"
|
||||
|
||||
#include "hk32f030m_iwdg.h"
|
||||
|
||||
#include "hk32f030m_pwr.h"
|
||||
|
||||
#include "hk32f030m_spi.h"
|
||||
|
||||
#include "hk32f030m_tim.h"
|
||||
|
||||
#include "hk32f030m_usart.h"
|
||||
|
||||
#include "hk32f030m_iwdg.h"
|
||||
|
||||
#include "hk32f030m_wwdg.h"
|
||||
|
||||
#include "hk32f030m_awu.h"
|
||||
|
||||
#include "hk32f030m_beep.h"
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* drivers code
|
||||
*/
|
||||
//#define USE_FULL_ASSERT (1U)
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(char* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT MKMcircoChuip *****END OF FILE****/
|
||||
74
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_crc.h
Normal file
74
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_crc.h
Normal file
@@ -0,0 +1,74 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_crc.h
|
||||
* @author Thomas.W
|
||||
* @version V1.0
|
||||
* @brief Header file of CRC module
|
||||
* @changelist
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_CRC_H
|
||||
#define __HK32F030M_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ----------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/** @defgroup CRC_ReverseInputData
|
||||
* @{
|
||||
*/
|
||||
#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
|
||||
#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
|
||||
#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
|
||||
#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
|
||||
|
||||
#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
|
||||
((DATA) == CRC_ReverseInputData_8bits) || \
|
||||
((DATA) == CRC_ReverseInputData_16bits) || \
|
||||
((DATA) == CRC_ReverseInputData_32bits))
|
||||
|
||||
/** @defgroup CRC_PolynomialSize
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
|
||||
|
||||
#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
|
||||
((SIZE) == CRC_PolSize_8) || \
|
||||
((SIZE) == CRC_PolSize_16) || \
|
||||
((SIZE) == CRC_PolSize_32))
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Configuration of the CRC computation unit **********************************/
|
||||
void CRC_DeInit(void);
|
||||
void CRC_ResetDR(void);
|
||||
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
|
||||
void CRC_ReverseOutputDataCmd(FunctionalState NewState);
|
||||
void CRC_SetInitRegister(uint32_t CRC_InitValue);
|
||||
|
||||
/* CRC computation ************************************************************/
|
||||
uint32_t CRC_CalcCRC(uint32_t CRC_Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
|
||||
/* Independent register (IDR) access (write/read) *****************************/
|
||||
void CRC_SetIDRegister(uint8_t CRC_IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_CRC_H */
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,55 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_dbgmcu.h
|
||||
* @author Felix.z
|
||||
* @version V1.0
|
||||
* @brief API file of DBGMCU module
|
||||
* @changelist
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __HK32F030M_DBGMCU_H
|
||||
#define __HK32F030M_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DBGMCU_STOP DBGMCU_CR_DBG_STOP
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM1_STOP DBGMCU_APB1_FZ_DBG_TIM1_STOP
|
||||
#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP
|
||||
#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
|
||||
#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
|
||||
#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
|
||||
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Device and Revision ID management functions ********************************/
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
|
||||
/* Peripherals Configuration functions ****************************************/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_DBGMCU_H */
|
||||
|
||||
111
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_def.h
Normal file
111
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_def.h
Normal file
@@ -0,0 +1,111 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_def.h
|
||||
* @author Rakan.Z
|
||||
* @version V1.0
|
||||
* @changelist
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_DEF_H
|
||||
#define __HK32F030M_DEF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
#include <stdio.h>
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
|
||||
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
|
||||
/* ARM & GNUCompiler
|
||||
----------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___HK32F030M_DEF_H */
|
||||
|
||||
|
||||
107
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_exti.h
Normal file
107
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_exti.h
Normal file
@@ -0,0 +1,107 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_exti.h
|
||||
* @author Rakan.zhang
|
||||
* @version V1.0
|
||||
* @brief Header file of EXTI module
|
||||
* This file contains all the functions prototypes for the EXTI firmware library
|
||||
* @changelist
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_EXTI_H
|
||||
#define __HK32F030M_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 Connected to the ADC AWD event */
|
||||
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 Connected to the USART wakeup event */
|
||||
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 Connected to the IIC wakeup event */
|
||||
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 Connected to the AWU Wakeup event */
|
||||
|
||||
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFFFF000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) )
|
||||
/** @defgroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
261
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_flash.h
Normal file
261
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_flash.h
Normal file
@@ -0,0 +1,261 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_flash.h
|
||||
* @author Rakan.Z/laura.C
|
||||
* @version V1.0
|
||||
* @brief API file of flash module
|
||||
* @changelist
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_FLASH_H
|
||||
#define __HK32F030M_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** FLASH Status */
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_ERROR_PROGRAM,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** FLASH_Latency */
|
||||
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*HCLK=16Mhz*/
|
||||
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*16Mhz<HCLK<=32Mhz*/
|
||||
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*32Mhz<HCLK<=48Mhz*/
|
||||
#define FLASH_Latency_3 ((uint32_t)0x00000003)
|
||||
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2) || \
|
||||
((LATENCY) == FLASH_Latency_3))
|
||||
|
||||
|
||||
|
||||
/** FLASH_Interrupts */
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
|
||||
|
||||
/* FLASH_Address 16K devices */
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x08003FFF))
|
||||
|
||||
#define FLASH_OB_RDP_ADDRESS 0x1FFFF800
|
||||
#define FLASH_OB_USER_ADDRESS 0x1FFFF802
|
||||
#define FLASH_OB_DATA0_ADDRESS 0x1FFFF804
|
||||
#define FLASH_OB_DATA1_ADDRESS 0x1FFFF806
|
||||
#define FLASH_OB_WRP_ADDRESS 0x1FFFF808
|
||||
#define FLASH_OB_IWDG_ADDRESS 0x1FFFF810
|
||||
#define FLASH_OB_LSI_LP_ADDRESS 0x1FFFF814
|
||||
#define FLASH_OB_DBG_CLK_ADDRESS 0x1FFFF816
|
||||
|
||||
/* EEPROM_Address 16K devices */
|
||||
#define IS_EEPROM_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x0C000000) && ((ADDRESS) <= 0x0C0001C0))
|
||||
|
||||
/** FLASH_Option_Bytes_Write_Protection */
|
||||
#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
|
||||
#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
|
||||
#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
|
||||
#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
|
||||
#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
|
||||
#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
|
||||
#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
|
||||
#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
|
||||
#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
|
||||
#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
|
||||
#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
|
||||
#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
|
||||
#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
|
||||
#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
|
||||
#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
|
||||
#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
|
||||
#define OB_WRP_Pages64to67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */
|
||||
#define OB_WRP_Pages68to71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */
|
||||
#define OB_WRP_Pages72to75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */
|
||||
#define OB_WRP_Pages76to79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */
|
||||
#define OB_WRP_Pages80to83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */
|
||||
#define OB_WRP_Pages84to87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */
|
||||
#define OB_WRP_Pages88to91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */
|
||||
#define OB_WRP_Pages92to95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */
|
||||
#define OB_WRP_Pages96to99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */
|
||||
#define OB_WRP_Pages100to103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */
|
||||
#define OB_WRP_Pages104to107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */
|
||||
#define OB_WRP_Pages108to111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */
|
||||
#define OB_WRP_Pages112to115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */
|
||||
#define OB_WRP_Pages116to119 ((uint32_t)0x20000000) /* Write protection of page 116 to 119 */
|
||||
#define OB_WRP_Pages120to123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */
|
||||
#define OB_WRP_Pages124to127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */
|
||||
|
||||
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
||||
#define OB_WRP_None ((uint32_t)0x00000000) /*!< Write protection of none */
|
||||
|
||||
|
||||
/** FLASH_Option_Bytes_Read_Protection */
|
||||
|
||||
/** FLASH_Read Protection Level */
|
||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_Level_1 ((uint8_t)0xBB)
|
||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
|
||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
||||
((LEVEL) == OB_RDP_Level_2))*/
|
||||
|
||||
/** FLASH_Option_Bytes_IWatchdog */
|
||||
|
||||
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* defgroup FLASH_Option_Bytes_nRST_STOP */
|
||||
|
||||
#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the option bytes Address
|
||||
*/
|
||||
|
||||
#define OPTION_BYTE_START_DATA1_ADDRESS ((uint32_t)0x1FFFF804)
|
||||
#define OPTION_BYTE_END_DATA1_ADDRESS ((uint32_t)0x1FFFF806)
|
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= OPTION_BYTE_START_DATA1_ADDRESS) && \
|
||||
((ADDRESS) <= OPTION_BYTE_END_DATA1_ADDRESS))
|
||||
|
||||
|
||||
|
||||
/** FLASH_Flags */
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
|
||||
|
||||
/** FLASH_Timeout_definition */
|
||||
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
|
||||
|
||||
|
||||
|
||||
/** FLASH_Legacy */
|
||||
#define FLASH_WRProt_Pages0to3 OB_WRP_Pages0to3
|
||||
#define FLASH_WRProt_Pages4to7 OB_WRP_Pages4to7
|
||||
#define FLASH_WRProt_Pages8to11 OB_WRP_Pages8to11
|
||||
#define FLASH_WRProt_Pages12to15 OB_WRP_Pages12to15
|
||||
#define FLASH_WRProt_Pages16to19 OB_WRP_Pages16to19
|
||||
#define FLASH_WRProt_Pages20to23 OB_WRP_Pages20to23
|
||||
#define FLASH_WRProt_Pages24to27 OB_WRP_Pages24to27
|
||||
#define FLASH_WRProt_Pages28to31 OB_WRP_Pages28to31
|
||||
#define FLASH_WRProt_Pages32to35 OB_WRP_Pages32to35
|
||||
#define FLASH_WRProt_Pages36to39 OB_WRP_Pages36to39
|
||||
#define FLASH_WRProt_Pages40to43 OB_WRP_Pages40to43
|
||||
#define FLASH_WRProt_Pages44to47 OB_WRP_Pages44to47
|
||||
#define FLASH_WRProt_Pages48to51 OB_WRP_Pages48to51
|
||||
#define FLASH_WRProt_Pages52to55 OB_WRP_Pages52to55
|
||||
#define FLASH_WRProt_Pages56to59 OB_WRP_Pages56to59
|
||||
#define FLASH_WRProt_Pages60to63 OB_WRP_Pages60to63
|
||||
#define FLASH_WRProt_Pages64to67 OB_WRP_Pages64to67
|
||||
#define FLASH_WRProt_Pages68to71 OB_WRP_Pages68to71
|
||||
#define FLASH_WRProt_Pages72to75 OB_WRP_Pages72to75
|
||||
#define FLASH_WRProt_Pages76to79 OB_WRP_Pages76to79
|
||||
#define FLASH_WRProt_Pages80to83 OB_WRP_Pages80to83
|
||||
#define FLASH_WRProt_Pages84to87 OB_WRP_Pages84to87
|
||||
#define FLASH_WRProt_Pages88to91 OB_WRP_Pages88to91
|
||||
#define FLASH_WRProt_Pages92to95 OB_WRP_Pages92to95
|
||||
#define FLASH_WRProt_Pages96to99 OB_WRP_Pages96to99
|
||||
#define FLASH_WRProt_Pages100to103 OB_WRP_Pages100to103
|
||||
#define FLASH_WRProt_Pages104to107 OB_WRP_Pages104to107
|
||||
#define FLASH_WRProt_Pages108to111 OB_WRP_Pages108to111
|
||||
#define FLASH_WRProt_Pages112to115 OB_WRP_Pages112to115
|
||||
#define FLASH_WRProt_Pages116to119 OB_WRP_Pages116to119
|
||||
#define FLASH_WRProt_Pages120to123 OB_WRP_Pages120to123
|
||||
#define FLASH_WRProt_Pages124to127 OB_WRP_Pages124to127
|
||||
|
||||
|
||||
#define FLASH_WRProt_AllPages OB_WRP_AllPages
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
|
||||
/* FLASH Interface configuration functions ************************************/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
|
||||
|
||||
/* FLASH Memory Programming functions *****************************************/
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
|
||||
|
||||
/* FLASH Option Bytes Programming functions *****************************************/
|
||||
void FLASH_OB_Unlock(void);
|
||||
void FLASH_OB_Lock(void);
|
||||
FLASH_Status FLASH_OB_EraseByte(uint32_t Address);
|
||||
|
||||
FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP);
|
||||
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
||||
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP );
|
||||
FLASH_Status FLASH_OB_IWDG_RLRConfig(uint16_t OB_IWDG_RLR, FunctionalState NewState);
|
||||
FLASH_Status FLASH_OB_LSILPConfig(FunctionalState NewState);
|
||||
FLASH_Status FLASH_OB_DBGCLKConfig(FunctionalState NewState);
|
||||
FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
|
||||
FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint16_t Data);
|
||||
uint8_t FLASH_OB_GetUser(void);
|
||||
uint32_t FLASH_OB_GetWRP(void);
|
||||
FlagStatus FLASH_OB_GetRDP(void);
|
||||
|
||||
/* FLASH Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
|
||||
FLASH_Status EEPROM_EraseByte(uint32_t Address);
|
||||
FLASH_Status EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
|
||||
|
||||
|
||||
void Sys_GetDevice64BitUID(uint32_t *UID);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_FLASH_H */
|
||||
|
||||
|
||||
449
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_gpio.h
Normal file
449
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_gpio.h
Normal file
@@ -0,0 +1,449 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_gpio.h
|
||||
* @version V1.0.1
|
||||
* @date 2019-08-15
|
||||
* author Rakan.Z
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_GPIO_H
|
||||
#define __HK32F030M_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) )
|
||||
|
||||
#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB))
|
||||
|
||||
/** @defgroup Configuration_Mode_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_type_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_Maximum_frequency_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_Level_1 = 0x00, /*!< I/O output speed: Low 2 MHz */
|
||||
GPIO_Speed_Level_2 = 0x01, /*!< I/O output speed: Medium 10 MHz */
|
||||
}GPIOSpeed_TypeDef;
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* @brief Configuration Schmit */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Schmit_Disable = 0x0,
|
||||
GPIO_Schmit_Enable = 0x1,
|
||||
}GPIOSchmit_TypeDef;
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
|
||||
GPIOSchmit_TypeDef GPIO_Schmit; /*!<GPIO Schmitt>*/
|
||||
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
|
||||
#define GPIO_AF_0 ((uint8_t)0x00) /* (I2C1_SWD)I2C1_SMBA, I2C1_SCL, SWCLK_I2C1_SDA, I2C1_SDA, SWDIO*/
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_1 ((uint8_t)0x01) /* (USART1)USART1_TX, USART1_RX, USART1_CK */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_2 ((uint8_t)0x02) /* (SPI)SPI1_SCK, SPI1_NSS, SPI1_MISO, SPI1_NSS, SPI1_MOSI*/
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_3 ((uint8_t)0x03) /* (TIM1)TIM1_BKIN, TIM1_CH1N, TIM1_CH2N, TIM1_CH3N,TIM1_CH3_CH1N,TIM1_CH4_CH2N, TIM1_ETR,TIM1_CH1,TIM1_CH2,TIM1_CH4,TIM1_ETR */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_4 ((uint8_t)0x04) /* (TIM2)TIM2_CH3, TIM2_ETR, TIM2_CH4, TIM2_CH2, TIM2_CH1*/
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_5 ((uint8_t)0x05) /* (RCC)RCC_MCO */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_6 ((uint8_t)0x06) /*(BEEPER)BEEP */
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_7 ((uint8_t)0x07) /*(ADC1)ADC1_ETR */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
|
||||
((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
|
||||
((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
|
||||
((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7) )
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief IOMUX PIN selection
|
||||
*/
|
||||
#define GPIOMUX_AF3_TIM1CH3 ((uint8_t)0x01) /* PC3_AF3_TIM1CH3 */ // PC3 AS AF3
|
||||
#define GPIOMUX_AF3_TIM1CH1N ((uint8_t)0x06) /* PC3_AF3_TIM1CH1N */ // PC3 AS AF3
|
||||
#define GPIOMUX_AF3_TIM1CH4 ((uint8_t)0x02) /* PC4_AF3_TIM1CH4 */ // PC4 AS AF3
|
||||
#define GPIOMUX_AF3_TIM1CH2N ((uint8_t)0x05) /* PC4_AF3_TIM1CH2N */ // PC4 AS AF3
|
||||
#define GPIOMUX_AF0_SWCLK ((uint8_t)0x04) /* PB5_AF0_SWCLK */ // PB5 AS AF0
|
||||
#define GPIOMUX_AF0_I2C_SDA ((uint8_t)0x03) /* PB5_AF0_I2C_SDA */ // PB5 AS AF0
|
||||
|
||||
#define GPIO_IOMUX_AF(IOMUX_AF) (((IOMUX_AF) == GPIOMUX_AF_3_TIM1CH3) || ((IOMUX_AF) == GPIOMUX_AF_3_TIM1CH1N) || \
|
||||
((IOMUX_AF) == GPIOMUX_AF_3_TIM1CH4) || ((IOMUX_AF) == GPIOMUX_AF_3_TIM1CH2N)|| \
|
||||
((IOMUX_AF) == GPIOMUX_AF_0_SWCLK)|| ((IOMUX_AF) == GPIOMUX_AF_0_I2C_SDA) )
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Speed_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Speed_2MHz GPIO_Speed_Level_1 /*!< I/O output speed: Low 2 MHz */
|
||||
#define GPIO_Speed_10MHz GPIO_Speed_Level_2 /*!< I/O output speed: Medium 10 MHz */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_IOMUX
|
||||
* @{
|
||||
*/
|
||||
#define IOMUX_PC3_TIM1CH3 0x00000001
|
||||
#define IOMUX_PC3_TIM1CH1N 0xFFFFFFFE
|
||||
#define IOMUX_PC4_TIM1CH4 0x00000002
|
||||
#define IOMUX_PC4_TIM1CH2N 0xFFFFFFFD
|
||||
#define IOMUX_PB5_SWCLK 0x00000004
|
||||
#define IOMUX_PB5_I2C_SDA 0xFFFFFFFB
|
||||
|
||||
|
||||
/** @defgroup GPIO_IOMUX_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
// SO8N PIN
|
||||
IOMUX_PIN1,
|
||||
//IOMUX_PIN4, only HK32F0301Mxx
|
||||
IOMUX_PIN5,
|
||||
IOMUX_PIN6,
|
||||
IOMUX_PIN7,
|
||||
IOMUX_PIN8,
|
||||
// TSSOP16 PIN
|
||||
IOMUX_PIN9,
|
||||
IOMUX_PIN12,
|
||||
IOMUX_PIN15,
|
||||
// TSSOP20/UFQFN20 PIN
|
||||
IOMUX_PIN2,
|
||||
IOMUX_PIN11
|
||||
|
||||
}IOMUX_PIN;
|
||||
|
||||
/// list of IOMUX_FuncPin
|
||||
|
||||
#define IOMUX_PD6_SEL_PD6 ((uint32_t)0x00000000)
|
||||
#define IOMUX_PD6_SEL_PA1 ((uint32_t)0x00000080)
|
||||
#define IOMUX_PD6_SEL_PD4 ((uint32_t)0x00000100)
|
||||
#define IOMUX_PD6_SEL_PA2 ((uint32_t)0x00000180)
|
||||
#define IOMUX_PD6_SEL_MASK ((uint32_t)0xFFFFFE7F)
|
||||
|
||||
#define IOMUX_PB5_SEL_PB5 ((uint32_t)0x00000000)
|
||||
#define IOMUX_PB5_SEL_PA3 ((uint32_t)0x00000002)
|
||||
#define IOMUX_PB5_SEL_PD2 ((uint32_t)0x00000004)
|
||||
#define IOMUX_PB5_SEL_MASK ((uint32_t)0xFFFFFFF9)
|
||||
|
||||
#define IOMUX_NRST_SEL_NRST ((uint32_t)0x00000002)
|
||||
#define IOMUX_NRST_SEL_PA0 ((uint32_t)0x00000000)
|
||||
#define IOMUX_NRST_SEL_PB4 ((uint32_t)0x00000001)
|
||||
#define IOMUX_NRST_SEL_MASK ((uint32_t)0xFFFFFFFE)
|
||||
|
||||
#define IOMUX_PC4_SEL_PC4 ((uint32_t)0x00000000)
|
||||
#define IOMUX_PC4_SEL_PC5 ((uint32_t)0x00000008)
|
||||
#define IOMUX_PC4_SEL_PC3 ((uint32_t)0x00000010)
|
||||
#define IOMUX_PC4_SEL_PC7 ((uint32_t)0x00000018)
|
||||
#define IOMUX_PC4_SEL_MASK ((uint32_t)0xFFFFFFE7)
|
||||
|
||||
#define IOMUX_PD5_SEL_PD5 ((uint32_t)0x00000000)
|
||||
#define IOMUX_PD5_SEL_PD3 ((uint32_t)0x00000020)
|
||||
#define IOMUX_PD5_SEL_PD1 ((uint32_t)0x00000040)
|
||||
#define IOMUX_PD5_SEL_PC6 ((uint32_t)0x00000060)
|
||||
#define IOMUX_PD5_SEL_MASK ((uint32_t)0xFFFFFF9F)
|
||||
|
||||
#define NRST_PINKEY (uint32_t)(0x00005AE1)
|
||||
|
||||
#define IS_IOMUX_PIN(IOMUX_PIN) (((IOMUX_PIN) == IOMUX_PIN1) ||((IOMUX_PIN) == IOMUX_PIN2) ||\
|
||||
((IOMUX_PIN) == IOMUX_PIN5) || ((IOMUX_PIN) == IOMUX_PIN6) ||\
|
||||
((IOMUX_PIN) == IOMUX_PIN7) || ((IOMUX_PIN) == IOMUX_PIN8) ||\
|
||||
((IOMUX_PIN) == IOMUX_PIN9) || ((IOMUX_PIN) == IOMUX_PIN11)||\
|
||||
((IOMUX_PIN) == IOMUX_PIN12) || ((IOMUX_PIN) == IOMUX_PIN15) )
|
||||
|
||||
|
||||
#define IS_IOMUX_PINFNC(IOMUX_PINFNC) (((IOMUX_PINFNC) == IOMUX_PD6_SEL_PD6) || ((IOMUX_PINFNC) == IOMUX_PD6_SEL_PA1) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PD6_SEL_PD4) || ((IOMUX_PINFNC) == IOMUX_PD6_SEL_PA2) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PD6_SEL_MASK) || ((IOMUX_PINFNC) == IOMUX_PB5_SEL_PB5) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PB5_SEL_PA3) || ((IOMUX_PINFNC) == IOMUX_PB5_SEL_PD2) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PB5_SEL_MASK) || ((IOMUX_PINFNC) == IOMUX_NRST_SEL_NRST) || \
|
||||
((IOMUX_PINFNC) == IOMUX_NRST_SEL_PB4) || ((IOMUX_PINFNC) == IOMUX_NRST_SEL_MASK) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PC4_SEL_PC4) || ((IOMUX_PINFNC) == IOMUX_PC4_SEL_PC5) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PC4_SEL_PC3) || ((IOMUX_PINFNC) == IOMUX_PC4_SEL_PC7) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PC4_SEL_MASK) || ((IOMUX_PINFNC) == IOMUX_PD5_SEL_PD5) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PD5_SEL_PD3) || ((IOMUX_PINFNC) == IOMUX_PD5_SEL_PD1) || \
|
||||
((IOMUX_PINFNC) == IOMUX_PD5_SEL_PC6) || ((IOMUX_PINFNC) == IOMUX_PD5_SEL_MASK) || \
|
||||
((IOMUX_PINFNC) == NRST_PINKEY) || ((IOMUX_PINFNC) == IOMUX_NRST_SEL_PA0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
TIM2_CN1_EXTERNAL = 0,
|
||||
TIM2_CN1_HSIDIV,
|
||||
TIM2_CN1_LSI_128,
|
||||
TIM2_CN1_EXTERNAL_MAX
|
||||
}TIM2_SOURCE;
|
||||
|
||||
#define IS_TIM2_SOURCE(TIM2_SOURCE) (((TIM2_SOURCE) == TIM2_CN1_EXTERNAL) || ((TIM2_SOURCE) == TIM2_CN1_HSIDIV) || \
|
||||
((TIM2_SOURCE) == TIM2_CN1_LSI_128) || ((TIM2_SOURCE) == TIM2_CN1_EXTERNAL_MAX))
|
||||
|
||||
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the GPIO configuration to the default reset state *****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_Toggle(GPIO_TypeDef* GPIOx , uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Alternate functions configuration functions ***************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
/* GPIO IOMUX*/
|
||||
void GPIO_IOMUX_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t IOMUX_AF);
|
||||
void GPIO_IOMUX_ChangePin(IOMUX_PIN eIOMUX_Pinx, uint32_t eIOMUX_FuncPin);
|
||||
|
||||
void GPIO_IOMUX_SetTIM2CN1_Source(TIM2_SOURCE TIM2CN1Source);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_GPIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
449
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_i2c.h
Normal file
449
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_i2c.h
Normal file
@@ -0,0 +1,449 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_i2c.h
|
||||
* @version V1.0.1
|
||||
* @date 2019-12-16
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_I2C_H
|
||||
#define __HK32F030M_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter must be set by referring to I2C_Timing_Config_Tool*/
|
||||
|
||||
uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
|
||||
This parameter can be a value of @ref I2C_Analog_Filter*/
|
||||
|
||||
uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
|
||||
This parameter can be a number between 0x00 and 0x0F*/
|
||||
|
||||
uint32_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode*/
|
||||
|
||||
uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
|
||||
This parameter can be a 7-bit or 10-bit address*/
|
||||
|
||||
uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement*/
|
||||
|
||||
uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address*/
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) ((PERIPH) == I2C1)
|
||||
|
||||
#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1)
|
||||
|
||||
/** @defgroup I2C_Analog_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
|
||||
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
|
||||
((FILTER) == I2C_AnalogFilter_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Digital_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint32_t)0x00000000)
|
||||
#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
|
||||
#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
|
||||
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_Ack_Disable I2C_CR2_NACK
|
||||
|
||||
#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
|
||||
((ACK) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
|
||||
#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
|
||||
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint16_t)0x0000)
|
||||
#define I2C_Direction_Receiver ((uint16_t)0x0400)
|
||||
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
|
||||
#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
|
||||
|
||||
#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_slave_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_own_address2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address2_mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_OA2_NoMask ((uint8_t)0x00)
|
||||
#define I2C_OA2_Mask01 ((uint8_t)0x01)
|
||||
#define I2C_OA2_Mask02 ((uint8_t)0x02)
|
||||
#define I2C_OA2_Mask03 ((uint8_t)0x03)
|
||||
#define I2C_OA2_Mask04 ((uint8_t)0x04)
|
||||
#define I2C_OA2_Mask05 ((uint8_t)0x05)
|
||||
#define I2C_OA2_Mask06 ((uint8_t)0x06)
|
||||
#define I2C_OA2_Mask07 ((uint8_t)0x07)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
|
||||
((MASK) == I2C_OA2_Mask01) || \
|
||||
((MASK) == I2C_OA2_Mask02) || \
|
||||
((MASK) == I2C_OA2_Mask03) || \
|
||||
((MASK) == I2C_OA2_Mask04) || \
|
||||
((MASK) == I2C_OA2_Mask05) || \
|
||||
((MASK) == I2C_OA2_Mask06) || \
|
||||
((MASK) == I2C_OA2_Mask07))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_timeout
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_TIMINGR ((uint8_t)0x10)
|
||||
#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
|
||||
#define I2C_Register_ISR ((uint8_t)0x18)
|
||||
#define I2C_Register_ICR ((uint8_t)0x1C)
|
||||
#define I2C_Register_PECR ((uint8_t)0x20)
|
||||
#define I2C_Register_RXDR ((uint8_t)0x24)
|
||||
#define I2C_Register_TXDR ((uint8_t)0x28)
|
||||
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_TIMINGR) || \
|
||||
((REGISTER) == I2C_Register_TIMEOUTR) || \
|
||||
((REGISTER) == I2C_Register_ISR) || \
|
||||
((REGISTER) == I2C_Register_ICR) || \
|
||||
((REGISTER) == I2C_Register_PECR) || \
|
||||
((REGISTER) == I2C_Register_RXDR) || \
|
||||
((REGISTER) == I2C_Register_TXDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_NACKF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
|
||||
((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
|
||||
((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
|
||||
((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
|
||||
((FLAG) == I2C_FLAG_BUSY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_TXIS I2C_ISR_TXIS
|
||||
#define I2C_IT_RXNE I2C_ISR_RXNE
|
||||
#define I2C_IT_ADDR I2C_ISR_ADDR
|
||||
#define I2C_IT_NACKF I2C_ISR_NACKF
|
||||
#define I2C_IT_STOPF I2C_ISR_STOPF
|
||||
#define I2C_IT_TC I2C_ISR_TC
|
||||
#define I2C_IT_TCR I2C_ISR_TCR
|
||||
#define I2C_IT_BERR I2C_ISR_BERR
|
||||
#define I2C_IT_ARLO I2C_ISR_ARLO
|
||||
#define I2C_IT_OVR I2C_ISR_OVR
|
||||
#define I2C_IT_PECERR I2C_ISR_PECERR
|
||||
#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_IT_ALERT I2C_ISR_ALERT
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
|
||||
((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
|
||||
((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
|
||||
((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_ALERT))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ReloadEndMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Reload_Mode I2C_CR2_RELOAD
|
||||
#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
|
||||
#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
|
||||
|
||||
|
||||
#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
|
||||
((MODE) == I2C_AutoEnd_Mode) || \
|
||||
((MODE) == I2C_SoftEnd_Mode))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_StartStopMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_No_StartStop ((uint32_t)0x00000000)
|
||||
#define I2C_Generate_Stop I2C_CR2_STOP
|
||||
#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_Generate_Start_Write I2C_CR2_START
|
||||
|
||||
|
||||
#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
|
||||
((MODE) == I2C_Generate_Start_Read) || \
|
||||
((MODE) == I2C_Generate_Start_Write) || \
|
||||
((MODE) == I2C_No_StartStop))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
|
||||
void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* Communications handling functions ******************************************/
|
||||
void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
|
||||
void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
|
||||
uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
|
||||
void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
|
||||
|
||||
/* SMBUS management functions ************************************************/
|
||||
void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* I2C registers management functions *****************************************/
|
||||
uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
|
||||
/* Data transfers management functions ****************************************/
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__HK32F030M_I2C_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
112
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_iwdg.h
Normal file
112
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_iwdg.h
Normal file
@@ -0,0 +1,112 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_iwdg.h
|
||||
* @version V1.0.0
|
||||
* author Rakan.Z/wing.w
|
||||
* @date 2019-08-15
|
||||
******************************************************************************
|
||||
/
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_IWDG_H
|
||||
#define __HK32F030M_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||
((PRESCALER) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_FLAG_PVU IWDG_SR_PVU
|
||||
#define IWDG_FLAG_RVU IWDG_SR_RVU
|
||||
#define IWDG_FLAG_WVU IWDG_SR_WVU
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
|
||||
((FLAG) == IWDG_FLAG_WVU))
|
||||
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
|
||||
#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Prescaler and Counter configuration functions ******************************/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_SetWindowValue(uint16_t WindowValue);
|
||||
|
||||
/* IWDG activation function ***************************************************/
|
||||
void IWDG_Enable(void);
|
||||
|
||||
/* Flag management function ***************************************************/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_IWDG_H */
|
||||
|
||||
|
||||
|
||||
|
||||
117
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_misc.h
Normal file
117
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_misc.h
Normal file
@@ -0,0 +1,117 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_misc.h
|
||||
* @version V1.0.1
|
||||
* @date 2019-08-15
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_MISC_H
|
||||
#define __HK32F030M_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type
|
||||
(For the complete HK32 Devices IRQ Channels list,
|
||||
please refer to hk32f030m.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 3. */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/**
|
||||
*
|
||||
@verbatim
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_MISC_H */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
68
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_pwr.h
Normal file
68
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_pwr.h
Normal file
@@ -0,0 +1,68 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_pwr.h
|
||||
* @author Rakan.z
|
||||
* @version V1.0
|
||||
* @brief Header file of PWR module
|
||||
* @changelist
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_PWR_H
|
||||
#define __HK32F030M_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/* ------------------ PWR registers bit mask ------------------------ */
|
||||
|
||||
/* CR register bit mask */
|
||||
#define CR_DS_MASK ((uint32_t)0xFFFFFFFE)
|
||||
|
||||
|
||||
/** @defgroup Regulator_state_is_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
|
||||
#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR) == PWR_Regulator_LowPower)
|
||||
|
||||
/** @defgroup PWR_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Entry_WFI ((uint8_t)0x01)
|
||||
#define PWR_Entry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_ENTRY(ENTRY) (((ENTRY) == PWR_Entry_WFI) || ((ENTRY) == PWR_Entry_WFE))
|
||||
|
||||
/** @defgroup PWR_LDO_VREF
|
||||
* @{
|
||||
*/
|
||||
#define ADC_VREF_0D8 ((uint16_t)0x0008)
|
||||
#define ADC_VREF_LDO ((uint16_t)0x000C)
|
||||
#define VTEST_SET_MASK ((uint16_t)0x3FFF)
|
||||
#define IS_PWR_VTEST_SET(VTEST_SET) (((VTEST_SET) == ADC_VREF_0D8) || ((VTEST_SET) == ADC_VREF_LDO))
|
||||
|
||||
|
||||
|
||||
|
||||
void PWR_DeInit(void);
|
||||
|
||||
void PWR_EnterSleepMode(uint8_t PWR_Entry);
|
||||
void PWR_EnterDeepSleepMode(uint8_t PWR_Entry);
|
||||
void PWR_EnterStopMode(uint32_t PWR_Regulator, uint8_t PWR_Entry);
|
||||
|
||||
void PWR_SetLDO_RefVolToADC(uint16_t Vref_Set);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
288
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_rcc.h
Normal file
288
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_rcc.h
Normal file
@@ -0,0 +1,288 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_rcc.h
|
||||
* @author laura.C
|
||||
* @version V1.0
|
||||
* @brief API file of RCC module
|
||||
* @changelist
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_RCC_H
|
||||
#define __HK32F030M_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency;
|
||||
uint32_t HCLK_Frequency;
|
||||
uint32_t PCLK_Frequency;
|
||||
uint32_t ADCCLK_Frequency;
|
||||
uint32_t I2C1CLK_Frequency;
|
||||
uint32_t USART1CLK_Frequency;
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
/** RCC_System_Clock_Source */
|
||||
|
||||
#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
|
||||
#define RCC_SYSCLKSource_EXTCLK RCC_CFGR_SW_EXTCLK
|
||||
#define RCC_SYSCLKSource_LSI RCC_CFGR_SW_LSI
|
||||
|
||||
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_EXTCLK) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_LSI))
|
||||
|
||||
/** RCC_AHB_Clock_Source */
|
||||
|
||||
#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
|
||||
#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
|
||||
#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
|
||||
#define RCC_SYSCLK_Div6 RCC_CFGR_HPRE_DIV6
|
||||
#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
|
||||
#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
|
||||
#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
|
||||
#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
|
||||
#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
|
||||
#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) ||((HCLK) == RCC_SYSCLK_Div6))
|
||||
|
||||
|
||||
/** RCC_APB_Clock_Source */
|
||||
|
||||
#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1
|
||||
#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2
|
||||
#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4
|
||||
#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8
|
||||
#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
|
||||
/** RCC_ADC_clock_source */
|
||||
#define RCC_ADCCLK_HSI32M_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div1_5 ((uint32_t)0x04000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div2 ((uint32_t)0x08000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div2_5 ((uint32_t)0x0C000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div3 ((uint32_t)0x10000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div3_5 ((uint32_t)0x14000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div4 ((uint32_t)0x18000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div4_5 ((uint32_t)0x1C000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div5 ((uint32_t)0x20000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div5_5 ((uint32_t)0x24000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div6 ((uint32_t)0x28000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div6_5 ((uint32_t)0x2C000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div7 ((uint32_t)0x30000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div7_5 ((uint32_t)0x34000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div8 ((uint32_t)0x38000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div8_5 ((uint32_t)0x3C000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div9 ((uint32_t)0x40000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div9_5 ((uint32_t)0x44000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div10 ((uint32_t)0x48000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div10_5 ((uint32_t)0x4C000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div11 ((uint32_t)0x50000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div11_5 ((uint32_t)0x54000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div12 ((uint32_t)0x58000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div12_5 ((uint32_t)0x5C000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div13 ((uint32_t)0x60000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div13_5 ((uint32_t)0x64000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div14 ((uint32_t)0x68000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div14_5 ((uint32_t)0x6C000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div15 ((uint32_t)0x70000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div15_5 ((uint32_t)0x74000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div16 ((uint32_t)0x78000000)
|
||||
#define RCC_ADCCLK_HSI32M_Div16_5 ((uint32_t)0x7C000000)
|
||||
|
||||
#define RCC_CFGR4_ADCHSIPRE ((uint32_t)0x7C000000)
|
||||
|
||||
#define RCC_ADCCLK_PCLK_DIV2 ADC_CFGR2_CKMODE_0
|
||||
#define RCC_ADCCLK_PCLK_DIV4 ADC_CFGR2_CKMODE_1
|
||||
|
||||
/** RCC_I2C_clock_source */
|
||||
|
||||
#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
|
||||
|
||||
#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
|
||||
|
||||
|
||||
/** RCC_USART_clock_source */
|
||||
#define RCC_USART1CLK_PCLK ((uint32_t)0x00000000)
|
||||
#define RCC_USART1CLK_SYSCLK ((uint32_t)0x00000001)
|
||||
#define RCC_USART1CLK_HSI ((uint32_t)0x00000003)
|
||||
|
||||
#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \
|
||||
((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_USART1CLK_HSI))
|
||||
|
||||
/** RCC_Interrupt_Source */
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_EXTRDY ((uint8_t)0x08)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_HSIRDY) || \
|
||||
((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_EXTRDY))
|
||||
|
||||
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
|
||||
|
||||
|
||||
/** RCC_AHB_Peripherals */
|
||||
#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
|
||||
#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
|
||||
#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
|
||||
#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
|
||||
#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
|
||||
#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
|
||||
#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
|
||||
|
||||
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFE1FFAB) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFFE1FFAB) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
|
||||
|
||||
/** RCC_APB2_Peripherals */
|
||||
|
||||
#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
|
||||
#define RCC_APB2Periph_ADC RCC_APB2ENR_ADCEN
|
||||
#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
|
||||
#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
|
||||
#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
|
||||
#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A51E) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
|
||||
/** RCC_APB1_Peripherals */
|
||||
#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
|
||||
#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
|
||||
#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
|
||||
#define RCC_APB1Periph_AWU RCC_APB1ENR_AWUEN
|
||||
#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
|
||||
#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
|
||||
#define RCC_APB1Periph_BEEPER RCC_APB1ENR_BEEPEREN
|
||||
#define RCC_APB1Periph_IOMUX RCC_APB1ENR_IOMUXEN
|
||||
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8FDEF7EE) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/** RCC_MCO_Clock_Source */
|
||||
|
||||
#define RCC_MCOSource_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCOSource_LSI ((uint8_t)0x02)
|
||||
#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCOSource_HSI ((uint8_t)0x05)
|
||||
|
||||
|
||||
#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) ||\
|
||||
((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_LSI))
|
||||
|
||||
|
||||
/** RCC_MCOPrescaler */
|
||||
|
||||
#define RCC_MCOPrescaler_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCOPrescaler_2 ((uint32_t)0x10000000)
|
||||
#define RCC_MCOPrescaler_4 ((uint32_t)0x20000000)
|
||||
#define RCC_MCOPrescaler_8 ((uint32_t)0x30000000)
|
||||
#define RCC_MCOPrescaler_16 ((uint32_t)0x40000000)
|
||||
#define RCC_MCOPrescaler_32 ((uint32_t)0x50000000)
|
||||
#define RCC_MCOPrescaler_64 ((uint32_t)0x60000000)
|
||||
#define RCC_MCOPrescaler_128 ((uint32_t)0x70000000)
|
||||
|
||||
#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_2) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_4) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_8) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_16) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_32) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_64) || \
|
||||
((PRESCALER) == RCC_MCOPrescaler_128))
|
||||
|
||||
/** @defgroup RCC_Flag */
|
||||
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_EXTCLKDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_EXTCLKDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
|
||||
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_PINRST) || \
|
||||
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST))
|
||||
|
||||
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal clocks, CSS and MCO configuration functions *********/
|
||||
ErrorStatus RCC_WaitForStartUp(uint8_t RCC_FLAG);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_EXTCmd(FunctionalState NewState, uint32_t EXTCKL_SEL);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
|
||||
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLKConfig(uint32_t RCC_HCLK);
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK);
|
||||
void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
|
||||
void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_RCC_H */
|
||||
|
||||
|
||||
561
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_spi.h
Normal file
561
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_spi.h
Normal file
@@ -0,0 +1,561 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_spi.h
|
||||
* @version V1.0.1
|
||||
* @date 2019-12-16
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_SPI_H
|
||||
#define __HK32F030M_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref SPI_I2S_Mode */
|
||||
|
||||
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Standard */
|
||||
|
||||
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Data_Format */
|
||||
|
||||
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref SPI_I2S_MCLK_Output */
|
||||
|
||||
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
|
||||
|
||||
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_ALL_PERIPH(PERIPH) ((PERIPH) == SPI1)
|
||||
|
||||
#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
|
||||
|
||||
/** @defgroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||
((MODE) == SPI_Direction_1Line_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||
((MODE) == SPI_Mode_Slave))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DataSize_4b ((uint16_t)0x0300)
|
||||
#define SPI_DataSize_5b ((uint16_t)0x0400)
|
||||
#define SPI_DataSize_6b ((uint16_t)0x0500)
|
||||
#define SPI_DataSize_7b ((uint16_t)0x0600)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0700)
|
||||
#define SPI_DataSize_9b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_10b ((uint16_t)0x0900)
|
||||
#define SPI_DataSize_11b ((uint16_t)0x0A00)
|
||||
#define SPI_DataSize_12b ((uint16_t)0x0B00)
|
||||
#define SPI_DataSize_13b ((uint16_t)0x0C00)
|
||||
#define SPI_DataSize_14b ((uint16_t)0x0D00)
|
||||
#define SPI_DataSize_15b ((uint16_t)0x0E00)
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0F00)
|
||||
#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
|
||||
((SIZE) == SPI_DataSize_5b) || \
|
||||
((SIZE) == SPI_DataSize_6b) || \
|
||||
((SIZE) == SPI_DataSize_7b) || \
|
||||
((SIZE) == SPI_DataSize_8b) || \
|
||||
((SIZE) == SPI_DataSize_9b) || \
|
||||
((SIZE) == SPI_DataSize_10b) || \
|
||||
((SIZE) == SPI_DataSize_11b) || \
|
||||
((SIZE) == SPI_DataSize_12b) || \
|
||||
((SIZE) == SPI_DataSize_13b) || \
|
||||
((SIZE) == SPI_DataSize_14b) || \
|
||||
((SIZE) == SPI_DataSize_15b) || \
|
||||
((SIZE) == SPI_DataSize_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRCLength_8b ((uint16_t)0x0000)
|
||||
#define SPI_CRCLength_16b SPI_CR1_CRCL
|
||||
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
|
||||
((LENGTH) == SPI_CRCLength_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High SPI_CR1_CPOL
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||
((CPOL) == SPI_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge SPI_CR1_CPHA
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||
((CPHA) == SPI_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_Soft SPI_CR1_SSM
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||
((BIT) == SPI_FirstBit_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||
((MODE) == I2S_Mode_SlaveRx) || \
|
||||
((MODE) == I2S_Mode_MasterTx)|| \
|
||||
((MODE) == I2S_Mode_MasterRx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||
((STANDARD) == I2S_Standard_MSB) || \
|
||||
((STANDARD) == I2S_Standard_LSB) || \
|
||||
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||
((STANDARD) == I2S_Standard_PCMLong))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||
((FORMAT) == I2S_DataFormat_24b) || \
|
||||
((FORMAT) == I2S_DataFormat_32b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE
|
||||
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||
#define I2S_CPOL_High SPI_I2SCFGR_CKPOL
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||
((CPOL) == I2S_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_FIFO_reception_threshold
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
|
||||
#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH
|
||||
#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
|
||||
((THRESHOLD) == SPI_RxFIFOThreshold_QF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN
|
||||
#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN
|
||||
#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_last_DMA_transfers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
|
||||
#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
|
||||
#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
|
||||
#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
|
||||
#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSSInternalSoft_Set SPI_CR1_SSI
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||
((DIRECTION) == SPI_Direction_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
|
||||
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_RXNE) || \
|
||||
((IT) == SPI_I2S_IT_ERR))
|
||||
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_I2S_IT_FRE ((uint8_t)0x58)
|
||||
|
||||
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
|
||||
((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_transmission_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
|
||||
#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
|
||||
#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
|
||||
#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_reception_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
|
||||
#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
|
||||
#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
|
||||
#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
#define SPI_I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR
|
||||
#define SPI_FLAG_MODF SPI_SR_MODF
|
||||
#define SPI_I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define SPI_I2S_FLAG_BSY SPI_SR_BSY
|
||||
#define SPI_I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
|
||||
|
||||
#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
|
||||
((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
|
||||
((FLAG) == I2S_FLAG_UDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
|
||||
void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
|
||||
uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Hardware CRC Calculation functions *****************************************/
|
||||
void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
|
||||
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__HK32F030M_SPI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
130
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_syscfg.h
Normal file
130
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_syscfg.h
Normal file
@@ -0,0 +1,130 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_syscfg.h
|
||||
* @author Rakan.z
|
||||
* @version V1.0
|
||||
* @brief API file of PWR module
|
||||
* @changelist
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_SYSCFG_H
|
||||
#define __HK32F030M_SYSCFG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
|
||||
/** @addtogroup SYSCFG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
|
||||
|
||||
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOD) )
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Pin_Sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PinSource0 ((uint8_t)0x00)
|
||||
#define EXTI_PinSource1 ((uint8_t)0x01)
|
||||
#define EXTI_PinSource2 ((uint8_t)0x02)
|
||||
#define EXTI_PinSource3 ((uint8_t)0x03)
|
||||
#define EXTI_PinSource4 ((uint8_t)0x04)
|
||||
#define EXTI_PinSource5 ((uint8_t)0x05)
|
||||
#define EXTI_PinSource6 ((uint8_t)0x06)
|
||||
#define EXTI_PinSource7 ((uint8_t)0x07)
|
||||
#define EXTI_PinSource8 ((uint8_t)0x08)
|
||||
#define EXTI_PinSource9 ((uint8_t)0x09)
|
||||
#define EXTI_PinSource10 ((uint8_t)0x0A)
|
||||
#define EXTI_PinSource11 ((uint8_t)0x0B)
|
||||
#define EXTI_PinSource12 ((uint8_t)0x0C)
|
||||
#define EXTI_PinSource13 ((uint8_t)0x0D)
|
||||
#define EXTI_PinSource14 ((uint8_t)0x0E)
|
||||
#define EXTI_PinSource15 ((uint8_t)0x0F)
|
||||
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
|
||||
((PINSOURCE) == EXTI_PinSource1) || \
|
||||
((PINSOURCE) == EXTI_PinSource2) || \
|
||||
((PINSOURCE) == EXTI_PinSource3) || \
|
||||
((PINSOURCE) == EXTI_PinSource4) || \
|
||||
((PINSOURCE) == EXTI_PinSource5) || \
|
||||
((PINSOURCE) == EXTI_PinSource6) || \
|
||||
((PINSOURCE) == EXTI_PinSource7) || \
|
||||
((PINSOURCE) == EXTI_PinSource8) || \
|
||||
((PINSOURCE) == EXTI_PinSource9) || \
|
||||
((PINSOURCE) == EXTI_PinSource10) || \
|
||||
((PINSOURCE) == EXTI_PinSource11) || \
|
||||
((PINSOURCE) == EXTI_PinSource12) || \
|
||||
((PINSOURCE) == EXTI_PinSource13) || \
|
||||
((PINSOURCE) == EXTI_PinSource14) || \
|
||||
((PINSOURCE) == EXTI_PinSource15))
|
||||
|
||||
/**
|
||||
* SYSCFG memoryremap
|
||||
* @}
|
||||
*/
|
||||
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
|
||||
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
|
||||
|
||||
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || ((REMAP) == SYSCFG_MemoryRemap_SRAM))
|
||||
/**
|
||||
* SYSCFG Cortex-M0 LOCKUP_LOCK
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SYSCFG_Lockup_TIM1Break_OFF ((uint8_t)0x00)
|
||||
#define SYSCFG_Lockup_TIM1Break_ON ((uint8_t)0x01)
|
||||
|
||||
#define IS_SYSCFG_LOCKUP_TIM1BREAK_ONOFF(ONOFF) (((ONOFF) == SYSCFG_Lockup_TIM1Break_OFF) || \
|
||||
((ONOFF) == SYSCFG_Lockup_TIM1Break_ON) )
|
||||
|
||||
/*
|
||||
*SYSYCFG CFGR1 registers mask
|
||||
*/
|
||||
#define MEM_REMAP_MASK ((uint32_t)0xFFFFFFC)
|
||||
#define MEM_LOCKUP_OUT_MASK ((uint32_t)0x7FFFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void SYSCFG_DeInit(void);
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
|
||||
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
|
||||
void SYSCFG_Lockup_Tim1BreakConfig(uint8_t Lockup_lockOnOff);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__HK32F030M_SYSCFG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
967
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_tim.h
Normal file
967
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_tim.h
Normal file
@@ -0,0 +1,967 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_tim.h
|
||||
* @version V1.0.0
|
||||
* @date 2019-12-25
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_TIM_H
|
||||
#define __HK32F030M_TIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/** @addtogroup TIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief TIM Time Base Init structure definition
|
||||
* @note This sturcture is used with all TIMx.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
|
||||
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
|
||||
This parameter can be a value of @ref TIM_Counter_Mode */
|
||||
|
||||
uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
|
||||
Auto-Reload Register at the next update event.
|
||||
This parameter must be a number between 0x0000 and 0xFFFF. */
|
||||
|
||||
uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
|
||||
This parameter can be a value of @ref TIM_Clock_Division_CKD */
|
||||
|
||||
uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
|
||||
reaches zero, an update event is generated and counting restarts
|
||||
from the RCR value (N).
|
||||
This means in PWM mode that (N+1) corresponds to:
|
||||
- the number of PWM periods in edge-aligned mode
|
||||
- the number of half PWM period in center-aligned mode
|
||||
This parameter must be a number between 0x00 and 0xFF.
|
||||
@note This parameter is valid only for TIM1. */
|
||||
} TIM_TimeBaseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Output Compare Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
||||
|
||||
uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_state */
|
||||
|
||||
uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_state
|
||||
@note This parameter is valid only for TIM1. */
|
||||
|
||||
uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF
|
||||
for TIM2) */
|
||||
|
||||
uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
||||
|
||||
uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||
@note This parameter is valid only for TIM1. */
|
||||
|
||||
uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||
@note This parameter is valid only for TIM1. */
|
||||
|
||||
uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||
@note This parameter is valid only for TIM1. */
|
||||
} TIM_OCInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Input Capture Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t TIM_Channel; /*!< Specifies the TIM channel.
|
||||
This parameter can be a value of @ref TIM_Channel */
|
||||
|
||||
uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint16_t TIM_ICSelection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
||||
uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between 0x0 and 0xF */
|
||||
} TIM_ICInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM_BDTR structure definition
|
||||
* @note This sturcture is used only with TIM1.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
|
||||
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
|
||||
uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
|
||||
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
|
||||
uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
|
||||
This parameter can be a value of @ref TIM_Lock_level */
|
||||
|
||||
uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
|
||||
switching-on of the outputs.
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
|
||||
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
||||
|
||||
uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
|
||||
This parameter can be a value of @ref TIM_Break_Polarity */
|
||||
|
||||
uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
|
||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
} TIM_BDTRInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Input Capture Init structure definition
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup TIM_Exported_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM6))
|
||||
|
||||
|
||||
/* LIST1: TIM 1 */
|
||||
#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1)
|
||||
|
||||
/* LIST2: TIM 1 */
|
||||
#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1))
|
||||
|
||||
/* LIST3: TIM 1, 2 */
|
||||
#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2))
|
||||
|
||||
/* LIST4: TIM 1, 2 */
|
||||
#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2))
|
||||
|
||||
/* LIST5: TIM 1, 2 */
|
||||
#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2))
|
||||
|
||||
/* LIST6: TIM 1, 2 */
|
||||
#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2))
|
||||
|
||||
/* LIST7: TIM 1, 2, 6 */
|
||||
#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM6))
|
||||
|
||||
/* LIST8: TIM 1, 2 */
|
||||
#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2))
|
||||
|
||||
/* LIST9: TIM 1, 2, 6 */
|
||||
#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM6))
|
||||
|
||||
/* LIST10: TIM 1, 2, 6 */
|
||||
#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
||||
((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM6))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_and_PWM_modes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCMode_Timing ((uint16_t)0x0000)
|
||||
#define TIM_OCMode_Active ((uint16_t)0x0010)
|
||||
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
|
||||
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
|
||||
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
|
||||
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
|
||||
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
|
||||
((MODE) == TIM_OCMode_Active) || \
|
||||
((MODE) == TIM_OCMode_Inactive) || \
|
||||
((MODE) == TIM_OCMode_Toggle)|| \
|
||||
((MODE) == TIM_OCMode_PWM1) || \
|
||||
((MODE) == TIM_OCMode_PWM2))
|
||||
#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
|
||||
((MODE) == TIM_OCMode_Active) || \
|
||||
((MODE) == TIM_OCMode_Inactive) || \
|
||||
((MODE) == TIM_OCMode_Toggle)|| \
|
||||
((MODE) == TIM_OCMode_PWM1) || \
|
||||
((MODE) == TIM_OCMode_PWM2) || \
|
||||
((MODE) == TIM_ForcedAction_Active) || \
|
||||
((MODE) == TIM_ForcedAction_InActive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_One_Pulse_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OPMode_Single ((uint16_t)0x0008)
|
||||
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
|
||||
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
|
||||
((MODE) == TIM_OPMode_Repetitive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Channel
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_Channel_1 ((uint16_t)0x0000)
|
||||
#define TIM_Channel_2 ((uint16_t)0x0004)
|
||||
#define TIM_Channel_3 ((uint16_t)0x0008)
|
||||
#define TIM_Channel_4 ((uint16_t)0x000C)
|
||||
|
||||
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
||||
((CHANNEL) == TIM_Channel_2) || \
|
||||
((CHANNEL) == TIM_Channel_3) || \
|
||||
((CHANNEL) == TIM_Channel_4))
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
||||
((CHANNEL) == TIM_Channel_2) || \
|
||||
((CHANNEL) == TIM_Channel_3))
|
||||
#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
||||
((CHANNEL) == TIM_Channel_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Clock_Division_CKD
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
|
||||
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
|
||||
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
|
||||
#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
|
||||
((DIV) == TIM_CKD_DIV2) || \
|
||||
((DIV) == TIM_CKD_DIV4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Counter_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CounterMode_Up ((uint16_t)0x0000)
|
||||
#define TIM_CounterMode_Down ((uint16_t)0x0010)
|
||||
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
|
||||
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
|
||||
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
|
||||
#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
|
||||
((MODE) == TIM_CounterMode_Down) || \
|
||||
((MODE) == TIM_CounterMode_CenterAligned1) || \
|
||||
((MODE) == TIM_CounterMode_CenterAligned2) || \
|
||||
((MODE) == TIM_CounterMode_CenterAligned3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCPolarity_High ((uint16_t)0x0000)
|
||||
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
|
||||
#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
|
||||
((POLARITY) == TIM_OCPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_N_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
|
||||
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
|
||||
#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
|
||||
((POLARITY) == TIM_OCNPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_state
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OutputState_Disable ((uint16_t)0x0000)
|
||||
#define TIM_OutputState_Enable ((uint16_t)0x0001)
|
||||
#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
|
||||
((STATE) == TIM_OutputState_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_N_state
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
|
||||
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
|
||||
#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
|
||||
((STATE) == TIM_OutputNState_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Capture_Compare_state
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CCx_Enable ((uint16_t)0x0001)
|
||||
#define TIM_CCx_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
|
||||
((CCX) == TIM_CCx_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Capture_Compare_N_state
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CCxN_Enable ((uint16_t)0x0004)
|
||||
#define TIM_CCxN_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
|
||||
((CCXN) == TIM_CCxN_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Break_Input_enable_disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_Break_Enable ((uint16_t)0x1000)
|
||||
#define TIM_Break_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
|
||||
((STATE) == TIM_Break_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Break_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
|
||||
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
|
||||
#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
|
||||
((POLARITY) == TIM_BreakPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_AOE_Bit_Set_Reset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
|
||||
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
|
||||
((STATE) == TIM_AutomaticOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Lock_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
|
||||
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
|
||||
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
|
||||
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
|
||||
#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
|
||||
((LEVEL) == TIM_LOCKLevel_1) || \
|
||||
((LEVEL) == TIM_LOCKLevel_2) || \
|
||||
((LEVEL) == TIM_LOCKLevel_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
|
||||
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
|
||||
((STATE) == TIM_OSSIState_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
|
||||
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
|
||||
((STATE) == TIM_OSSRState_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Idle_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
|
||||
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
|
||||
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
|
||||
((STATE) == TIM_OCIdleState_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_N_Idle_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
|
||||
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
|
||||
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
|
||||
((STATE) == TIM_OCNIdleState_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
|
||||
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
|
||||
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
|
||||
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
|
||||
((POLARITY) == TIM_ICPolarity_Falling)|| \
|
||||
((POLARITY) == TIM_ICPolarity_BothEdge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
||||
connected to IC1, IC2, IC3 or IC4, respectively */
|
||||
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
||||
connected to IC2, IC1, IC4 or IC3, respectively. */
|
||||
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
|
||||
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
|
||||
((SELECTION) == TIM_ICSelection_IndirectTI) || \
|
||||
((SELECTION) == TIM_ICSelection_TRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
|
||||
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
|
||||
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
|
||||
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
|
||||
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
|
||||
((PRESCALER) == TIM_ICPSC_DIV2) || \
|
||||
((PRESCALER) == TIM_ICPSC_DIV4) || \
|
||||
((PRESCALER) == TIM_ICPSC_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_IT_Update ((uint16_t)0x0001)
|
||||
#define TIM_IT_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_IT_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_IT_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_IT_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_IT_COM ((uint16_t)0x0020)
|
||||
#define TIM_IT_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_IT_Break ((uint16_t)0x0080)
|
||||
#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
|
||||
|
||||
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
|
||||
((IT) == TIM_IT_CC1) || \
|
||||
((IT) == TIM_IT_CC2) || \
|
||||
((IT) == TIM_IT_CC3) || \
|
||||
((IT) == TIM_IT_CC4) || \
|
||||
((IT) == TIM_IT_COM) || \
|
||||
((IT) == TIM_IT_Trigger) || \
|
||||
((IT) == TIM_IT_Break))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_External_Trigger_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
||||
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
||||
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
||||
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
||||
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
|
||||
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
|
||||
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
|
||||
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Internal_Trigger_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_TS_ITR0 ((uint16_t)0x0000)
|
||||
#define TIM_TS_ITR1 ((uint16_t)0x0010)
|
||||
#define TIM_TS_ITR2 ((uint16_t)0x0020)
|
||||
#define TIM_TS_ITR3 ((uint16_t)0x0030)
|
||||
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
||||
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
||||
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
||||
#define TIM_TS_ETRF ((uint16_t)0x0070)
|
||||
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
||||
((SELECTION) == TIM_TS_ITR1) || \
|
||||
((SELECTION) == TIM_TS_ITR2) || \
|
||||
((SELECTION) == TIM_TS_ITR3) || \
|
||||
((SELECTION) == TIM_TS_TI1F_ED) || \
|
||||
((SELECTION) == TIM_TS_TI1FP1) || \
|
||||
((SELECTION) == TIM_TS_TI2FP2) || \
|
||||
((SELECTION) == TIM_TS_ETRF))
|
||||
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
||||
((SELECTION) == TIM_TS_ITR1) || \
|
||||
((SELECTION) == TIM_TS_ITR2) || \
|
||||
((SELECTION) == TIM_TS_ITR3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_TIx_External_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
||||
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
||||
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_External_Trigger_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
||||
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
||||
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
|
||||
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Prescaler_Reload_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
||||
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
||||
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
|
||||
((RELOAD) == TIM_PSCReloadMode_Immediate))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Forced_Action
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
||||
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
||||
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
|
||||
((ACTION) == TIM_ForcedAction_InActive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Encoder_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
||||
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
||||
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
||||
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
|
||||
((MODE) == TIM_EncoderMode_TI2) || \
|
||||
((MODE) == TIM_EncoderMode_TI12))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup TIM_Event_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_EventSource_Update ((uint16_t)0x0001)
|
||||
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_EventSource_COM ((uint16_t)0x0020)
|
||||
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_EventSource_Break ((uint16_t)0x0080)
|
||||
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Update_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
|
||||
or the setting of UG bit, or an update generation
|
||||
through the slave mode controller. */
|
||||
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
|
||||
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
|
||||
((SOURCE) == TIM_UpdateSource_Regular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Preload_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
||||
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
|
||||
((STATE) == TIM_OCPreload_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Fast_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
||||
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
|
||||
((STATE) == TIM_OCFast_Disable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Clear_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
||||
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
|
||||
((STATE) == TIM_OCClear_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Trigger_Output_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
||||
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
||||
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
||||
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
||||
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
||||
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
||||
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
||||
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
||||
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
|
||||
((SOURCE) == TIM_TRGOSource_Enable) || \
|
||||
((SOURCE) == TIM_TRGOSource_Update) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC1) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC4Ref))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
||||
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
||||
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
||||
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
||||
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
|
||||
((MODE) == TIM_SlaveMode_Gated) || \
|
||||
((MODE) == TIM_SlaveMode_Trigger) || \
|
||||
((MODE) == TIM_SlaveMode_External1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Master_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
||||
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
|
||||
((STATE) == TIM_MasterSlaveMode_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_FLAG_Update ((uint16_t)0x0001)
|
||||
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_FLAG_COM ((uint16_t)0x0020)
|
||||
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_FLAG_Break ((uint16_t)0x0080)
|
||||
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
|
||||
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
|
||||
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
|
||||
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
|
||||
#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
|
||||
((FLAG) == TIM_FLAG_CC1) || \
|
||||
((FLAG) == TIM_FLAG_CC2) || \
|
||||
((FLAG) == TIM_FLAG_CC3) || \
|
||||
((FLAG) == TIM_FLAG_CC4) || \
|
||||
((FLAG) == TIM_FLAG_COM) || \
|
||||
((FLAG) == TIM_FLAG_Trigger) || \
|
||||
((FLAG) == TIM_FLAG_Break) || \
|
||||
((FLAG) == TIM_FLAG_CC1OF) || \
|
||||
((FLAG) == TIM_FLAG_CC2OF) || \
|
||||
((FLAG) == TIM_FLAG_CC3OF) || \
|
||||
((FLAG) == TIM_FLAG_CC4OF))
|
||||
|
||||
|
||||
#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Filer_Value
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_External_Trigger_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_OCReferenceClear
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
|
||||
#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
|
||||
#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
|
||||
((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* TimeBase management ********************************************************/
|
||||
void TIM_DeInit(TIM_TypeDef* TIMx);
|
||||
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
||||
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
||||
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
|
||||
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
|
||||
void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
|
||||
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
|
||||
uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
|
||||
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
|
||||
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
|
||||
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
|
||||
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
|
||||
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
|
||||
/* Advanced-control timers (TIM1) specific features*******************/
|
||||
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
|
||||
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
|
||||
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
|
||||
/* Output Compare management **************************************************/
|
||||
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
|
||||
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
|
||||
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
|
||||
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
|
||||
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
|
||||
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
|
||||
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
|
||||
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
|
||||
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
|
||||
/* Input Capture management ***************************************************/
|
||||
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||
uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
|
||||
uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
|
||||
uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
|
||||
uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
|
||||
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||
|
||||
/* Interrupts and flags management ***************************************/
|
||||
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
|
||||
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
|
||||
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
||||
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
||||
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
||||
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
||||
|
||||
/* Clocks management **********************************************************/
|
||||
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
|
||||
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
||||
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
|
||||
uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
||||
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter);
|
||||
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
|
||||
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
||||
|
||||
|
||||
/* Synchronization management *************************************************/
|
||||
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
||||
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
|
||||
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
|
||||
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
|
||||
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter);
|
||||
|
||||
/* Specific interface management **********************************************/
|
||||
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
|
||||
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
||||
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__HK32F030M_TIM_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
541
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_usart.h
Normal file
541
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_usart.h
Normal file
@@ -0,0 +1,541 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_usart.h
|
||||
* @version V1.0.1
|
||||
* author Rakan.Z/wing.Wang
|
||||
* @date 2019-12-17
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_USART_H
|
||||
#define __HK32F030M_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint32_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control*/
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) ((PERIPH) == USART1)
|
||||
|
||||
#define IS_USART_1_PERIPH(PERIPH) ((PERIPH) == USART1)
|
||||
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint32_t)0x00000000)
|
||||
#define USART_WordLength_9b USART_CR1_M /* should be ((uint32_t)0x00001000) */
|
||||
#define USART_WordLength_7b ((uint32_t)0x10001000)
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b) || \
|
||||
((LENGTH) == USART_WordLength_7b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint32_t)0x00000000)
|
||||
#define USART_StopBits_2 USART_CR2_STOP_1
|
||||
#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint32_t)0x00000000)
|
||||
#define USART_Parity_Even USART_CR1_PCE
|
||||
#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx USART_CR1_RE
|
||||
#define USART_Mode_Tx USART_CR1_TE
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
|
||||
((MODE) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
|
||||
#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
|
||||
#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
|
||||
#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Clock_Disable ((uint32_t)0x00000000)
|
||||
#define USART_Clock_Enable USART_CR2_CLKEN
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint32_t)0x00000000)
|
||||
#define USART_CPOL_High USART_CR2_CPOL
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint32_t)0x00000000)
|
||||
#define USART_CPHA_2Edge USART_CR2_CPHA
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint32_t)0x00000000)
|
||||
#define USART_LastBit_Enable USART_CR2_LBCL
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_MuteMode_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
|
||||
#define USART_WakeUp_AddressMark USART_CR1_WAKE
|
||||
#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Address_Detection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_AddressLength_4b ((uint32_t)0x00000000)
|
||||
#define USART_AddressLength_7b USART_CR2_ADDM7
|
||||
#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
|
||||
((ADDRESS) == USART_AddressLength_7b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_StopMode_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
|
||||
#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
|
||||
#define USART_WakeUpSource_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
|
||||
#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
|
||||
((SOURCE) == USART_WakeUpSource_StartBit) || \
|
||||
((SOURCE) == USART_WakeUpSource_RXNE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
|
||||
#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower USART_CR3_IRLP
|
||||
#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DE_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DEPolarity_High ((uint32_t)0x00000000)
|
||||
#define USART_DEPolarity_Low USART_CR3_DEP
|
||||
#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
|
||||
((POLARITY) == USART_DEPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Inversion_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_InvPin_Tx USART_CR2_TXINV
|
||||
#define USART_InvPin_Rx USART_CR2_RXINV
|
||||
#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
|
||||
((PIN) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_AutoBaudRate_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
|
||||
#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
|
||||
#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
|
||||
((MODE) == USART_AutoBaudRate_FallingEdge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_OVR_DETECTION
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
|
||||
#define USART_OVRDetection_Disable USART_CR3_OVRDIS
|
||||
#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
|
||||
((OVR) == USART_OVRDetection_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup USART_Request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Request_ABRRQ USART_RQR_ABRRQ
|
||||
#define USART_Request_SBKRQ USART_RQR_SBKRQ
|
||||
#define USART_Request_MMRQ USART_RQR_MMRQ
|
||||
#define USART_Request_RXFRQ USART_RQR_RXFRQ
|
||||
#define USART_Request_TXFRQ USART_RQR_TXFRQ
|
||||
|
||||
#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
|
||||
((REQUEST) == USART_Request_RXFRQ) || \
|
||||
((REQUEST) == USART_Request_MMRQ) || \
|
||||
((REQUEST) == USART_Request_SBKRQ) || \
|
||||
((REQUEST) == USART_Request_ABRRQ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
#define USART_FLAG_REACK USART_ISR_REACK
|
||||
#define USART_FLAG_TEACK USART_ISR_TEACK
|
||||
#define USART_FLAG_WU USART_ISR_WUF
|
||||
#define USART_FLAG_RWU USART_ISR_RWU
|
||||
#define USART_FLAG_SBK USART_ISR_SBKF
|
||||
#define USART_FLAG_CM USART_ISR_CMF
|
||||
#define USART_FLAG_BUSY USART_ISR_BUSY
|
||||
#define USART_FLAG_ABRF USART_ISR_ABRF
|
||||
#define USART_FLAG_ABRE USART_ISR_ABRE
|
||||
#define USART_FLAG_EOB USART_ISR_EOBF
|
||||
#define USART_FLAG_RTO USART_ISR_RTOF
|
||||
#define USART_FLAG_nCTSS USART_ISR_CTS
|
||||
#define USART_FLAG_CTS USART_ISR_CTSIF
|
||||
#define USART_FLAG_LBDF USART_ISR_LBDF
|
||||
#define USART_FLAG_TXE USART_ISR_TXE
|
||||
#define USART_FLAG_TC USART_ISR_TC
|
||||
#define USART_FLAG_RXNE USART_ISR_RXNE
|
||||
#define USART_FLAG_IDLE USART_ISR_IDLE
|
||||
#define USART_FLAG_ORE USART_ISR_ORE
|
||||
#define USART_FLAG_NE USART_ISR_NE
|
||||
#define USART_FLAG_FE USART_ISR_FE
|
||||
#define USART_FLAG_PE USART_ISR_PE
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_ISR_LBDF) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
|
||||
((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
|
||||
((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
|
||||
((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
|
||||
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
|
||||
((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
|
||||
((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
|
||||
((FLAG) == USART_FLAG_LBDF) || ((FLAG) == USART_FLAG_CTS) || \
|
||||
((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
|
||||
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @brief USART Interrupt definition
|
||||
* USART_IT possible values
|
||||
* Elements values convention: 0xZZZZYYXX
|
||||
* XX: Position of the corresponding Interrupt
|
||||
* YY: Register index
|
||||
* ZZZZ: Flag position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_WU ((uint32_t)0x00140316)
|
||||
#define USART_IT_CM ((uint32_t)0x0011010E)
|
||||
#define USART_IT_EOB ((uint32_t)0x000C011B)
|
||||
#define USART_IT_RTO ((uint32_t)0x000B011A)
|
||||
#define USART_IT_PE ((uint32_t)0x00000108)
|
||||
#define USART_IT_TXE ((uint32_t)0x00070107)
|
||||
#define USART_IT_TC ((uint32_t)0x00060106)
|
||||
#define USART_IT_RXNE ((uint32_t)0x00050105)
|
||||
#define USART_IT_IDLE ((uint32_t)0x00040104)
|
||||
#define USART_IT_LBD ((uint32_t)0x00080206)
|
||||
#define USART_IT_CTS ((uint32_t)0x0009030A)
|
||||
#define USART_IT_ERR ((uint32_t)0x00000300)
|
||||
#define USART_IT_ORE ((uint32_t)0x00030300)
|
||||
#define USART_IT_NE ((uint32_t)0x00020300)
|
||||
#define USART_IT_FE ((uint32_t)0x00010300)
|
||||
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
|
||||
((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
|
||||
((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Global_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
|
||||
#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
|
||||
#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
|
||||
#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
|
||||
void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
|
||||
|
||||
/* STOP Mode functions ********************************************************/
|
||||
void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
|
||||
|
||||
/* AutoBaudRate functions *****************************************************/
|
||||
void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
|
||||
/* Multi-Processor Communication functions ************************************/
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
|
||||
void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
|
||||
|
||||
/* LIN mode functions *********************************************************/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Half-duplex mode function **************************************************/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Smartcard mode functions ***************************************************/
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
|
||||
void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
|
||||
|
||||
/* IrDA mode functions ********************************************************/
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* RS485 mode functions *******************************************************/
|
||||
void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
|
||||
void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
|
||||
void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
|
||||
void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
|
||||
void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_USART_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
86
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_wwdg.h
Normal file
86
badge_firmware/driver/HK32F030M_Driver/inc/hk32f030m_wwdg.h
Normal file
@@ -0,0 +1,86 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file hk32f030m_wwdg.h
|
||||
* @version V1.0.1
|
||||
* author Rakan.Z/wing.Wang
|
||||
* @date 2019-12-15
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HK32F030M_WWDG_H
|
||||
#define __HK32F030M_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hk32f030m.h"
|
||||
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||
((PRESCALER) == WWDG_Prescaler_8))
|
||||
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the WWDG configuration to the default reset state ****/
|
||||
void WWDG_DeInit(void);
|
||||
|
||||
/* Prescaler, Refresh window and Counter configuration functions **************/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
|
||||
/* WWDG activation functions **************************************************/
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HK32F030M_WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user