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Bootloader fixes and updates

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- Add canary value for bootloader entry
- Fix initial GPIO config for this application
This commit is contained in:
true
2023-11-12 16:59:53 -08:00
parent 60bd8d88b7
commit 00e0dcecf3
16 changed files with 391 additions and 161 deletions
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80
bootloader_hk32f030m_uart_xmodem/driver/CMSIS/HK32F030M/Source/system_hk32f030m.c
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@@ -121,47 +121,49 @@ void SystemInit(void)
*/
static void SetSysClock(void)
{
/*reload the hsi trimming value to the bit3~bit13 of RCC_CR register */
uint32_t u32HSIFLASH = 0;
uint32_t u32RCC_CR = 0;
uint32_t u32HSITemp = 0;
uint16_t u16HSITempH = 0;
uint16_t u16HSITempL = 0;
u32HSIFLASH = *(uint32_t *) 0x1FFFF820;
u16HSITempH = (uint16_t)(u32HSIFLASH>>16);
u16HSITempL = (uint16_t)(u32HSIFLASH);
if(!(u16HSITempH & u16HSITempL))
{
u32HSITemp = RCC->CR;
u32HSITemp &= (uint32_t)((uint32_t)~(RCC_CR_HSITRIM|RCC_CR_HSICAL));
u32RCC_CR = (uint32_t)(((u16HSITempL & 0x001F) <<3) | (((u16HSITempL>>5) & 0x003F)<<8));
RCC->CR |= u32RCC_CR;
}
/*end*/
#if(SYSCLK_SOURCE==SYSCLK_SRC_HSI8M)
// reload the HSI trimming value to bits 3~13 of RCC_CR register
// note: cannot find documentation for the actual values of this register
// but upon looking it appears to be inverted nybbles
// no idea what the high 5 bits are for...
uint32_t u32HSIFLASH = 0;
uint32_t u32HSITemp = 0;
uint16_t u16HSITempH = 0;
uint16_t u16HSITempL = 0;
u32HSIFLASH = *(uint32_t *)0x1FFFF820;
u16HSITempH = (uint16_t)(u32HSIFLASH >> 16);
u16HSITempL = (uint16_t)(u32HSIFLASH);
if((u16HSITempH ^ u16HSITempL) == 0xffff) {
// valid constants found; load to registers
u32HSITemp = RCC->CR & ~(RCC_CR_HSITRIM | RCC_CR_HSICAL);
u32HSITemp |= (uint32_t)(
((u16HSITempL & 0x001F) << 3) | // HSITRIM (RCC_CR[7:3], 5 bits)
(((u16HSITempL) & 0x07e0) << 3)); // HSICAL (RCC_RC[13:8], 6 bits)
RCC->CR = u32HSITemp;
}
// set system clock
#if (SYSCLK_SOURCE == SYSCLK_SRC_HSI8M)
SetSysClockToHSI();
#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI16M)
#elif (SYSCLK_SOURCE == SYSCLK_SRC_HSI16M)
SetSysClockToHSI();
#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI32M)
#elif (SYSCLK_SOURCE == SYSCLK_SRC_HSI32M)
SetSysClockToHSI();
#elif(SYSCLK_SOURCE == SYSCLK_SRC_LSI)
#elif (SYSCLK_SOURCE == SYSCLK_SRC_LSI)
SetSysClockToLSI();
#elif(SYSCLK_SOURCE == SYSCLK_SCR_EXTCLK_IO)
#elif (SYSCLK_SOURCE == SYSCLK_SCR_EXTCLK_IO)
SetSysClockToEXTCLK();
#endif
/* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */
// If none of the define above is enabled, the HSI is used as System clock source (default after reset)
}
#ifdef SYSCLK_FREQ_HSI
static void SetSysClockToHSI(void)
{
__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
__IO uint32_t ACRreg = 0;
__IO uint32_t RCCHCLKReg = 0;
__IO uint32_t RCCPCLKReg = 0;
uint32_t work;
/* Enable HSI */
RCC->CR |= RCC_CR_HSION;
@@ -179,26 +181,14 @@ static void SetSysClockToHSI(void)
} while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSIRDY) != RESET) {
HSIStatus = (uint32_t)0x01;
} else {
HSIStatus = (uint32_t)0x00;
}
if (HSIStatus == (uint32_t)0x01) {
/* Flash wait state */
ACRreg = FLASH->ACR;
ACRreg &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR = (uint32_t)(SET_FLASH_LATENCY | ACRreg);
FLASH->ACR = SET_FLASH_LATENCY;
/* HCLK = configured divided value from SYSCLK (which will later be set to HSI32M) */
RCCHCLKReg = RCC->CFGR;
RCCHCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_HPRE_Msk);
RCC->CFGR = (uint32_t)(SET_HPRE_DIV | RCCHCLKReg);
/* PCLK = HCLK */
RCCPCLKReg = RCC->CFGR;
RCCPCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_PPRE_Msk);
RCC->CFGR = (uint32_t)(RCC_CFGR_PPRE_DIV1|RCCPCLKReg);
work = RCC->CFGR;
work &= (uint32_t)((uint32_t)~(RCC_CFGR_HPRE | RCC_CFGR_PPRE));
RCC->CFGR = (uint32_t)(SET_HPRE_DIV | RCC_CFGR_PPRE_DIV1 | work);
/* Select HSI32M as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
@@ -210,7 +200,7 @@ static void SetSysClockToHSI(void)
/* If clock fails to start, the application will have wrong clock configuration.
* User can add some code here to deal with this error
*/
}
}
}
#elif (SYSCLK_SOURCE == SYSCLK_SRC_LSI)