416 lines
13 KiB
C
416 lines
13 KiB
C
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/**
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******************************************************************************
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* @file system_hk32f030m.c
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* @author laura.C
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* @version V1.0
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* @brief API file of system clk config
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* @changelist
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******************************************************************************
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*/
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/*
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This file configures the system clock as follows:
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*=============================================================================
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* Supported hk32f030m device
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*-----------------------------------------------------------------------------
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* System Clock source | HSI32M
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 32000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 32000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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*/
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#include "hk32f030m.h"
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/* system clock source */
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#define SYSCLK_SRC_HSI8M 0x2
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#define SYSCLK_SRC_HSI16M 0x3
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#define SYSCLK_SRC_HSI32M 0x4
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#define SYSCLK_SRC_LSI 0x5
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#define SYSCLK_SCR_EXTCLK_IO 0x6
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#define SYSCLK_SOURCE SYSCLK_SRC_HSI32M
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/* vector table location */
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// #define VECT_TAB_SRAM
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#ifndef VECT_TAB_OFFSET
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#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
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#endif
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uint32_t System_SysClk; // SYSCLK which feeds AHB, ADC, USART, etc. System clock.
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uint32_t System_HClk; // HCLK which feeds core, AHB bus, memory. CPU clock.
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#if(SYSCLK_SOURCE==SYSCLK_SRC_HSI8M)
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#define SYSCLK_FREQ_HSI 32000000
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#define HCLK_FREQ 8000000
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#define SET_FLASH_LATENCY FLASH_Latency_0
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#define SET_HPRE_DIV RCC_CFGR_HPRE_DIV4
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static void SetSysClockToHSI(void);
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI16M)
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#define SYSCLK_FREQ_HSI 32000000
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#define HCLK_FREQ 16000000
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#define SET_FLASH_LATENCY FLASH_Latency_0
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#define SET_HPRE_DIV RCC_CFGR_HPRE_DIV2
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static void SetSysClockToHSI(void);
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI32M)
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#define SYSCLK_FREQ_HSI 32000000
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#define HCLK_FREQ 32000000
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#define SET_FLASH_LATENCY FLASH_Latency_1
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#define SET_HPRE_DIV RCC_CFGR_HPRE_DIV1
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static void SetSysClockToHSI(void);
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_LSI)
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#define SYSCLK_FREQ_LSI LSI_VALUE
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uint32_t SystemCoreClock = SYSCLK_FREQ_LSI;
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static void SetSysClockToLSI(void);
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#elif(SYSCLK_SOURCE == SYSCLK_SCR_EXTCLK_IO)
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#define SYSCLK_FREQ_EXTCLK EXTCLK_VALUE
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uint32_t SystemCoreClock = SYSCLK_FREQ_EXTCLK;
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static void SetSysClockToEXTCLK(void);
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#endif
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static void SetSysClock(void);
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/**
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* @brief Setup the microcontroller system.
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* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FFB81C;
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/* Reset USARTSW[1:0], I2CSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFFEC;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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SetSysClock();
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#ifdef VECT_TAB_SRAM
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SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE; /* Vector Table Relocation in Internal SRAM. */
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#else
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// FLASH->INT_VEC_OFFSET = VECT_TAB_OFFSET ; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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* @brief Configures the System clock frequency, HCLK, PCLK prescalers.
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* @param None
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* @retval None
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*/
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static void SetSysClock(void)
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{
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/*reload the hsi trimming value to the bit3~bit13 of RCC_CR register */
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uint32_t u32HSIFLASH = 0;
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uint32_t u32RCC_CR = 0;
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uint32_t u32HSITemp = 0;
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uint16_t u16HSITempH = 0;
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uint16_t u16HSITempL = 0;
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u32HSIFLASH = *(uint32_t *) 0x1FFFF820;
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u16HSITempH = (uint16_t)(u32HSIFLASH>>16);
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u16HSITempL = (uint16_t)(u32HSIFLASH);
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if(!(u16HSITempH & u16HSITempL))
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{
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u32HSITemp = RCC->CR;
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u32HSITemp &= (uint32_t)((uint32_t)~(RCC_CR_HSITRIM|RCC_CR_HSICAL));
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u32RCC_CR = (uint32_t)(((u16HSITempL & 0x001F) <<3) | (((u16HSITempL>>5) & 0x003F)<<8));
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RCC->CR |= u32RCC_CR;
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}
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/*end*/
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#if(SYSCLK_SOURCE==SYSCLK_SRC_HSI8M)
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SetSysClockToHSI();
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI16M)
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SetSysClockToHSI();
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_HSI32M)
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SetSysClockToHSI();
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#elif(SYSCLK_SOURCE == SYSCLK_SRC_LSI)
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SetSysClockToLSI();
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#elif(SYSCLK_SOURCE == SYSCLK_SCR_EXTCLK_IO)
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SetSysClockToEXTCLK();
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#endif
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/* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */
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}
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#ifdef SYSCLK_FREQ_HSI
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static void SetSysClockToHSI(void)
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{
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__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
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__IO uint32_t ACRreg = 0;
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__IO uint32_t RCCHCLKReg = 0;
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__IO uint32_t RCCPCLKReg = 0;
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/* Enable HSI */
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RCC->CR |= RCC_CR_HSION;
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/* Set flash programming clock to 2MHz using HSI32M directly
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* Datasheet and RM was updated in 2023 which derated flash programming from 4MHz
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* 0x07 = 4MHz, 0x08 = 2MHz. change as you see fit */
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RCC->CFGR4 &= ~(RCC_RCC_CFGR4_FLITFCLK_PRE | RCC_RCC_CFGR4_FLITFCLK_SE);
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RCC->CFGR4 |= (((uint32_t)0x08) << RCC_RCC_CFGR4_FLITFCLK_PRE_Pos);
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/* Wait until HSI is ready; if timeout is reached, then exit */
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do {
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HSIStatus = RCC->CR & RCC_CR_HSIRDY;
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StartUpCounter++;
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} while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_HSIRDY) != RESET) {
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HSIStatus = (uint32_t)0x01;
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} else {
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HSIStatus = (uint32_t)0x00;
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}
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if (HSIStatus == (uint32_t)0x01) {
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/* Flash wait state */
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ACRreg = FLASH->ACR;
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ACRreg &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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FLASH->ACR = (uint32_t)(SET_FLASH_LATENCY | ACRreg);
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/* HCLK = configured divided value from SYSCLK (which will later be set to HSI32M) */
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RCCHCLKReg = RCC->CFGR;
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RCCHCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_HPRE_Msk);
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RCC->CFGR = (uint32_t)(SET_HPRE_DIV | RCCHCLKReg);
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/* PCLK = HCLK */
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RCCPCLKReg = RCC->CFGR;
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RCCPCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_PPRE_Msk);
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RCC->CFGR = (uint32_t)(RCC_CFGR_PPRE_DIV1|RCCPCLKReg);
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/* Select HSI32M as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
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/* Wait until HSI is active as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);
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} else {
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/* If clock fails to start, the application will have wrong clock configuration.
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* User can add some code here to deal with this error
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*/
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}
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}
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#elif (SYSCLK_SOURCE == SYSCLK_SRC_LSI)
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static void SetSysClockToLSI(void)
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{
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__IO uint32_t StartUpCounter = 0, LSIStatus = 0;
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/* Enable LSI */
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RCC->CSR |= RCC_CSR_LSION;
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/* Wait till LSI is ready and if Time out is reached exit */
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do{
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LSIStatus = RCC->CSR & RCC_CSR_LSIRDY;
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StartUpCounter++;
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} while((LSIStatus == 0) && (StartUpCounter != STARTUP_TIMEOUT));
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if ((RCC->CSR & RCC_CSR_LSIRDY) != RESET)
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{
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LSIStatus = (uint32_t)0x01;
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}
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else
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{
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LSIStatus = (uint32_t)0x00;
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}
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if (LSIStatus == (uint32_t)0x01)
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{
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/* Flash wait state */
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FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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FLASH->ACR |= (uint32_t)FLASH_Latency_0;
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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/* PCLK = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
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/* Select HSI as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_LSI;
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/* Wait till LSI is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_LSI)
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{
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}
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}
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else
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{ /* If fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */
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}
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};
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#elif (SYSCLK_SOURCE == SYSCLK_SCR_EXTCLK_IO)
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static void SetSysClockToEXTCLK(void)
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{
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__IO uint32_t StartUpCounter = 0, EXTCLKStatus = 0;
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__IO uint32_t ACRreg = 0;
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__IO uint32_t RCCHCLKReg = 0;
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__IO uint32_t RCCPCLKReg = 0;
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//enable EXTIO PA1/PD7/PB5/PC5
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/* Configure PA1 as CLOCK input */
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RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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// RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
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// GPIO_InitTypeDef GPIO_InitStructure;
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
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// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
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// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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// GPIO_Init(GPIOD, &GPIO_InitStructure);
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// RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
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// GPIO_InitTypeDef GPIO_InitStructure;
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
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// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
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// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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// GPIO_Init(GPIOB, &GPIO_InitStructure);
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// RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
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// GPIO_InitTypeDef GPIO_InitStructure;
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
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// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
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// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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// GPIO_Init(GPIOC, &GPIO_InitStructure);
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/*CLOCK select */
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RCC->CFGR4 &= (uint32_t)~(RCC_RCC_CFGR4_EXTCLK_SEL);
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RCC->CFGR4 |= (uint32_t)RCC_CFGR4_EXTCLK_SEL_PA1;
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// RCC->CFGR4 |= (uint32_t)RCC_CFGR4_EXTCLK_SEL_PB5;
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// RCC->CFGR4 |= (uint32_t)RCC_CFGR4_EXTCLK_SEL_PC5;
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// RCC->CFGR4 |= (uint32_t)RCC_CFGR4_EXTCLK_SEL_PD7;
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/* Enable EXTCLK */
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RCC->CR |= RCC_CR_EXTCLKON;
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/* Wait till LSI is ready and if Time out is reached exit */
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do{
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EXTCLKStatus = RCC->CR & RCC_CR_EXTCLKRDY;
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StartUpCounter++;
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} while((EXTCLKStatus == 0) && (StartUpCounter != STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_EXTCLKRDY) != RESET)
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{
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EXTCLKStatus = (uint32_t)0x01;
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}
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else
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{
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EXTCLKStatus = (uint32_t)0x00;
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}
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if (EXTCLKStatus == (uint32_t)0x01)
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{
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/* Flash wait state */
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ACRreg= FLASH->ACR;
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ACRreg &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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if (SystemCoreClock <= 16000000)
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FLASH->ACR = (uint32_t)(FLASH_Latency_0|ACRreg);
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else if(SystemCoreClock <= 32000000)
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FLASH->ACR = (uint32_t)(FLASH_Latency_1|ACRreg);
|
||
|
|
else
|
||
|
|
FLASH->ACR = (uint32_t)(FLASH_Latency_2|ACRreg);
|
||
|
|
|
||
|
|
|
||
|
|
RCCHCLKReg = RCC->CFGR;
|
||
|
|
RCCHCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_HPRE_Msk);
|
||
|
|
/* HCLK = SYSCLK */
|
||
|
|
RCC->CFGR = (uint32_t)(RCC_CFGR_HPRE_DIV1|RCCHCLKReg);
|
||
|
|
|
||
|
|
RCCPCLKReg = RCC->CFGR;
|
||
|
|
RCCPCLKReg &= (uint32_t)((uint32_t)~RCC_CFGR_PPRE_Msk);
|
||
|
|
/* PCLK = HCLK */
|
||
|
|
RCC->CFGR = (uint32_t)(RCC_CFGR_PPRE_DIV1|RCCPCLKReg);
|
||
|
|
|
||
|
|
|
||
|
|
/* Select EXTCLK as system clock source */
|
||
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_EXTCLK;
|
||
|
|
|
||
|
|
/* Wait till EXTCLK is used as system clock source */
|
||
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_EXTCLK)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{ /* If fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||
|
|
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||
|
|
* be used by the user application to setup the SysTick timer or configure
|
||
|
|
* other parameters.
|
||
|
|
*
|
||
|
|
* @note Each time the core clock (HCLK) changes, this function must be called
|
||
|
|
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||
|
|
* based on this variable will be incorrect.
|
||
|
|
* @param None
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SystemCoreClockUpdate (void)
|
||
|
|
{
|
||
|
|
uint32_t tmp = 0, presc = 0;
|
||
|
|
|
||
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
||
|
|
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||
|
|
|
||
|
|
switch (tmp) {
|
||
|
|
case RCC_CFGR_SWS_EXTCLK: // EXTCLK used as system clock
|
||
|
|
SystemCoreClock = EXTCLK_VALUE;
|
||
|
|
break;
|
||
|
|
case RCC_CFGR_SWS_LSI: // LSI used as system clock
|
||
|
|
SystemCoreClock = LSI_VALUE;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case RCC_CFGR_SWS_HSI: // HSI used as system clock
|
||
|
|
default:
|
||
|
|
SystemCoreClock = HCLK_FREQ;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Compute HCLK clock frequency ----------------*/
|
||
|
|
/* Get HCLK prescaler */
|
||
|
|
tmp = RCC->CFGR & RCC_CFGR_HPRE;
|
||
|
|
tmp = tmp >> 4;
|
||
|
|
presc = AHBPrescTable[tmp];
|
||
|
|
/* HCLK clock frequency */
|
||
|
|
SystemCoreClock = SystemCoreClock/presc;
|
||
|
|
}
|