d95af918fa
lots of code copied over, things filled in to hopefully get the LED matrix lighting up. untested.
412 lines
11 KiB
C
412 lines
11 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32x035_rcc.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2023/04/06
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* Description : This file provides all the RCC firmware functions.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32x035_rcc.h"
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/* RCC registers bit mask */
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/* CTLR register bit mask */
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#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
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/* CFGR0 register bit mask */
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#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
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#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
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/* RSTSCKR register bit mask */
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#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
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/* RCC Flag Mask */
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#define FLAG_Mask ((uint8_t)0x1F)
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/* CFGR0 register byte 4 (Bits[31:24]) base address */
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#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
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static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
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/*********************************************************************
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* @fn RCC_DeInit
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*
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* @brief Resets the RCC clock configuration to the default reset state.
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* Note-
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* HSE can not be stopped if it is used directly or through the PLL as system clock.
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* @return none
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*/
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void RCC_DeInit(void)
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{
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RCC->CTLR |= (uint32_t)0x00000001;
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RCC->CFGR0 |= (uint32_t)0x00000050;
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RCC->CFGR0 &= (uint32_t)0xF8FFFF5F;
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}
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/*********************************************************************
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* @fn RCC_AdjustHSICalibrationValue
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*
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* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
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*
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* @param HSICalibrationValue - specifies the calibration trimming value.
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* This parameter must be a number between 0 and 0x1F.
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*
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* @return none
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*/
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void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
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{
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uint32_t tmpreg = 0;
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tmpreg = RCC->CTLR;
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tmpreg &= CTLR_HSITRIM_Mask;
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tmpreg |= (uint32_t)HSICalibrationValue << 3;
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RCC->CTLR = tmpreg;
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}
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/*********************************************************************
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* @fn RCC_HSICmd
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*
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* @brief Enables or disables the Internal High Speed oscillator (HSI).
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*
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* @param NewState - ENABLE or DISABLE.
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*
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* @return none
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*/
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void RCC_HSICmd(FunctionalState NewState)
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{
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if(NewState)
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{
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RCC->CTLR |= (1<<0);
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}
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else{
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RCC->CTLR &= ~(1<<0);
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}
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}
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/*********************************************************************
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* @fn RCC_HCLKConfig
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*
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* @brief Configures the AHB clock (HCLK).
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*
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* @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
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* the system clock (SYSCLK).
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* RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
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* RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
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* RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3.
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* RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
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* RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5.
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* RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6.
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* RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7.
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* RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
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* RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
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* RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32.
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* RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
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* RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
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* RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
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*
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* @return none
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*/
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void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
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{
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uint32_t tmpreg = 0;
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tmpreg = RCC->CFGR0;
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tmpreg &= CFGR0_HPRE_Reset_Mask;
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tmpreg |= RCC_SYSCLK;
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RCC->CFGR0 = tmpreg;
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}
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/*********************************************************************
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* @fn RCC_GetClocksFreq
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*
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* @brief The result of this function could be not correct when using
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* fractional value for HSE crystal.
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*
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* @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
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* the clocks frequencies.
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*
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* @return none
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*/
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void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
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{
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uint32_t tmp = 0, presc = 0;
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RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
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tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
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tmp = tmp >> 4;
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presc = APBAHBPrescTable[tmp];
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if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8)
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{
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RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc;
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}
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else
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{
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RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
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}
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RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency;
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RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency;
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}
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/*********************************************************************
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* @fn RCC_AHBPeriphClockCmd
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*
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* @brief Enables or disables the AHB peripheral clock.
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*
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* @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
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* RCC_AHBPeriph_DMA1.
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* RCC_AHBPeriph_SRAM.
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* RCC_AHBPeriph_USBFS.
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* RCC_AHBPeriph_USBPD
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* Note-
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* SRAM clock can be disabled only during sleep mode.
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* NewState: ENABLE or DISABLE.
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*
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* @return none
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*/
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void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
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{
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if (NewState != DISABLE)
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{
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RCC->AHBPCENR |= RCC_AHBPeriph;
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}
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else
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{
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RCC->AHBPCENR &= ~RCC_AHBPeriph;
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}
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}
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/*********************************************************************
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* @fn RCC_APB2PeriphClockCmd
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*
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* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
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*
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* @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
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* RCC_APB2Periph_AFIO.
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* RCC_APB2Periph_GPIOA.
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* RCC_APB2Periph_GPIOB.
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* RCC_APB2Periph_GPIOC.
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* RCC_APB2Periph_ADC1.
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* RCC_APB2Periph_TIM1.
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* RCC_APB2Periph_SPI1.
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* RCC_APB2Periph_USART1.
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* NewState - ENABLE or DISABLE
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*
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* @return none
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*/
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void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
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{
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if (NewState != DISABLE)
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{
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RCC->APB2PCENR |= RCC_APB2Periph;
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}
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else
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{
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RCC->APB2PCENR &= ~RCC_APB2Periph;
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}
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}
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/*********************************************************************
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* @fn RCC_APB1PeriphClockCmd
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*
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* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
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*
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* @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
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* RCC_APB1Periph_TIM2.
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* RCC_APB1Periph_TIM3.
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* RCC_APB1Periph_WWDG.
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* RCC_APB1Periph_USART2.
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* RCC_APB1Periph_USART3.
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* RCC_APB1Periph_USART4
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* RCC_APB1Periph_I2C1.
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* RCC_APB1Periph_PWR.
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* NewState - ENABLE or DISABLE.
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*
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* @return none
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*/
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void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
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{
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if (NewState != DISABLE)
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{
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RCC->APB1PCENR |= RCC_APB1Periph;
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}
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else
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{
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RCC->APB1PCENR &= ~RCC_APB1Periph;
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}
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}
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/*********************************************************************
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* @fn RCC_AHBPeriphResetCmd
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*
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* @brief Forces or releases AHB peripheral reset.
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*
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* @param RCC_AHBPeriph - specifies the AHB peripheral to reset.
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* RCC_AHBPeriph_USBFS.
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* RCC_AHBPeriph_IO2W.
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* RCC_AHBPeriph_USBPD.
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* NewState: ENABLE or DISABLE.
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*
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* @return none
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*/
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void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
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{
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if (NewState != DISABLE)
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{
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RCC->AHBPCENR |= RCC_AHBPeriph;
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}
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else
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{
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RCC->AHBPCENR &= ~RCC_AHBPeriph;
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}
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}
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/*********************************************************************
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* @fn RCC_APB2PeriphResetCmd
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*
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* @brief Forces or releases APB (APB2) peripheral reset.
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*
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* @param RCC_APB2Periph - specifies the APB2 peripheral to reset.
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* RCC_APB2Periph_AFIO.
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* RCC_APB2Periph_GPIOA.
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* RCC_APB2Periph_GPIOB.
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* RCC_APB2Periph_GPIOC.
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* RCC_APB2Periph_ADC1.
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* RCC_APB2Periph_TIM1.
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* RCC_APB2Periph_SPI1.
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* RCC_APB2Periph_USART1.
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* NewState - ENABLE or DISABLE
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*
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* @return none
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*/
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void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
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{
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if (NewState != DISABLE)
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{
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RCC->APB2PRSTR |= RCC_APB2Periph;
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}
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else
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{
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RCC->APB2PRSTR &= ~RCC_APB2Periph;
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}
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}
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/*********************************************************************
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* @fn RCC_APB1PeriphResetCmd
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*
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* @brief Forces or releases APB (APB1) peripheral reset.
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*
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* @param RCC_APB1Periph - specifies the APB1 peripheral to reset.
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* RCC_APB1Periph_TIM2.
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* RCC_APB1Periph_TIM3.
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* RCC_APB1Periph_WWDG.
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* RCC_APB1Periph_USART2.
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* RCC_APB1Periph_USART3.
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* RCC_APB1Periph_USART4
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* RCC_APB1Periph_I2C1.
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* RCC_APB1Periph_PWR.
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* NewState - ENABLE or DISABLE.
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*
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* @return none
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*/
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void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
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{
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if (NewState != DISABLE)
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{
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RCC->APB1PRSTR |= RCC_APB1Periph;
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}
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else
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{
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RCC->APB1PRSTR &= ~RCC_APB1Periph;
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}
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}
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/*********************************************************************
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* @fn RCC_MCOConfig
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*
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* @brief Selects the clock source to output on MCO pin.
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*
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* @param RCC_MCO - specifies the clock source to output.
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* RCC_MCO_NoClock - No clock selected.
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* RCC_MCO_SYSCLK - System clock selected.
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* RCC_MCO_HSI - HSI oscillator clock selected.
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*
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* @return none
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*/
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void RCC_MCOConfig(uint8_t RCC_MCO)
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{
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*(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO;
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}
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/*********************************************************************
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* @fn RCC_GetFlagStatus
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*
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* @brief Checks whether the specified RCC flag is set or not.
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*
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* @param RCC_FLAG - specifies the flag to check.
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* RCC_FLAG_HSIRDY - HSI oscillator clock ready.
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* RCC_FLAG_OPARST - OPA reset.
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* RCC_FLAG_PINRST - Pin reset.
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* RCC_FLAG_PORRST - POR/PDR reset.
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* RCC_FLAG_SFTRST - Software reset.
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* RCC_FLAG_IWDGRST - Independent Watchdog reset.
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* RCC_FLAG_WWDGRST - Window Watchdog reset.
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* RCC_FLAG_LPWRRST - Low Power reset.
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*
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* @return FlagStatus - SET or RESET.
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*/
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FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
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{
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uint32_t tmp = 0;
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uint32_t statusreg = 0;
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FlagStatus bitstatus = RESET;
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tmp = RCC_FLAG >> 5;
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if (tmp == 1)
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{
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statusreg = RCC->CTLR;
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}
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else
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{
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statusreg = RCC->RSTSCKR;
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}
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tmp = RCC_FLAG & FLAG_Mask;
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if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
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{
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bitstatus = SET;
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}
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else
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{
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bitstatus = RESET;
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}
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return bitstatus;
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}
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/*********************************************************************
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* @fn RCC_ClearFlag
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*
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* @brief Clears the RCC reset flags.
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* Note-
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* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
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* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
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* @return none
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*/
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void RCC_ClearFlag(void)
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{
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RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
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}
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